Maintenance/ Discontinued

Transcription

1 CCD Linear Image Seor MNA -Bit High-Speed High-Resolution CCD Linear Image Seor Overview The MNA is a high-speed high-resolution CCD linear image seor having low dark output floating photodiodes in the photodetector region and CCD analog shift registers for read out. It provides large output at a high S/N ratio for visible light inputs over a wide range of wavelength. Features floating photodiodes and n-channel buried type CCD shift registers for read out are integrated in a single chip. Use of photodiodes with a new structure has made the dark output voltage very low. An A size document can be read with a high resolution of dpi. Permits high speed scanning of a data rate of MHz. High blue respoivity of a maximum respoivity ratio of % (typ.) at 4nm, and smooth spectral respoe over the entire visible region. A large signal output of 4m (typ.) can be obtained at saturation, and the hold type waveform output makes signal processing easy. Operation with a single + positive power supply. Block Diagram OS DS identifies the pin position. DD R C C SUB 9 B B B OS DS OG R D D SS A A TG PG 4 B C 4 9 B B D D 4 Pin Assignments D D4 9 4 (Top iew) WDIP-C-4D IS OS DS DD R C C B B IS SUB Application Graphic, character, and numeral read out in fax machines, image scanners, etc. OS DS OG 4 9 R D D SS A A TG PG B to B : Black reference pixels D to D 4 : Dummy invalid pixels

2 CCD Linear Image Seor Absolute Maximum Ratings (Ta= C, SS=) Parameter Symbol Rating Unit DD SUB. to +. to + Power supply voltage IS OG PG. to +. to +. to + Input pin voltage Output pin voltage Operating temperature range Storage temperature range I O Topr Tstg. to +. to + to + 4 to + C C Operating Conditio oltage conditio (Ta= to + C, SS=) MNA Power supply voltage DD... IS test pin voltage Substrate voltage Output gate voltage Photo storage gate voltage TG test pin voltage High level Low level Shift gate clock High level Shift gate clock Low level Reset gate clock High level Reset gate clock Low level IS SUB OG PG TG H L SH SL RH IS =DD SUB=DD PG=OG TG=SS Note DD. DD DD. DD. DD. RL Note ) There is no problem in operation even when the High level is a voltage equal to about DD, it is preferable to set this at a value close to the standard value coidering the load on the clock driver particularly at high speed drives and the increase in the dark signal output voltage due to the heat generation in the chip. Timing conditio (Ta= to + C) Shift register clock frequency fc... MHz f C=f R=/T Reset clock frequency fr... MHz Shift register clock rise time Shift register clock fall time Shift clock rise time Shift clock fall time Shift clock set up time Shift clock pulse width Shift clock hold time Reset clock rise time Reset clock fall time Reset clock set up time Reset clock pulse width Reset clock hold time t Cr t Cf t Sr t Sf t Ss tsw t Sh trr trf trs trw trh Note..T 4.. µs µs Note ) The lag characteristic becomes better if the shift clock pulse width is made long if there is no problem in the timing generation. Note ) The standard values of the timing conditio given above are merely for guidance and need not be taken as valued strictly required for operation. Determine the optimum values by experimentation depending on the actually used driving frequency and signal processing method.

3 MNA CCD Linear Image Seor Electrical Characteristics Clock input capacitance (Ta= to + C) Shift register clock input capacitance C A, C A C B, C B IN = pf Reset clock input capacitance Shift clock input capacitance C R C S f=mhz pf pf * A, A, B, and B are respectively connected to D, D, C, and C internally. DC characteristics Power supply current IDD ma DD =+ IS test pin leak current IIS ma Photo storage gate leak current IPG µa DD =+ Output gate pin leak current IOG µa AC characteristics Signal output set up time * t OS Signal output hold time t OW * OS output level: =m Optical Characteristics <Ipection conditio> Ta= C DD = IS = SUB = (DC), OG = PG =4. (DC), H = (pulse), SH = RH = (pulse) f C =f R =MHz, T int (accumulation time)=ms Light source: Daylight type fluorescent lamp Optical system: A slit with an aperture dimeio of mm mm is used at a distance of mm from the seor (equivalent to F=). This parameters are ipected by signal multiplex with channels and which correspond to the output of both OS and DS (channel ) and the output of both OS and DS (channel ) respectively. Before multiplex the channels and, the OS and DS signals should be respectively through unity gain differential amplifiers with input impedances of k Ohms or more, carrying out zero level DC clamping of each channel. These specificatio apply to the valid pixels excluding the dummy pixels D to D4. Respoivity Photo respoe non-uniformity Bit non-uniformity Saturation output voltage Saturation exposure Dark signal output voltage Dark signal output non-uniformity Shift register total trafer efficiency Dynamic range Modulation trafer function R PRNU BNU SAT SE DRK DSNU STTE DR MTFR Note Note Note Note 4 Note Dark condition, see Note Dark condition, see Note Note Note 9 Note ±.. /lx s % % lx s m m % % * The definitio of the parameters are given in Note ) to Note ) on the following page.

4 CCD Linear Image Seor MNA Optical Characteristics (continued) Note ) Respoivity (R) This is the value obtained by dividing the average output voltage () of the valid pixels by the exposure (lx s). The exposure (lx s) is the product of the illumination inteity (lx) and the accumulation time (s). Since the respoivity changes with the spectral distribution of the light source used, care should be taken when using a light source other than the daylight type fluorescent lamp specified in the ipection conditio. Note ) Photo respoe non-uniformity (PRNU) The photo respoe non-uniformity (PRNU) is defined by the following equation, where X ave is the average output voltage of the valid pixels and x is the absolute value of the difference between the maximum and minimum voltage, when the surface of the photo-sites is illuminated with light having a uniform distribution over the entire surface. PRNU= x (%) X ave The incident light inteity shall be % of the standard saturation llight inteity. Note ) Bit non-uniformity (BNU) This is defined by the following equation where the output voltage of each pixel among the pixels is denoted by Xi (i = to ) when the photodetector region is illuminated by a light of uniform illumination inteity distribution, and the average output voltage of the pixels near the ith pixel is denoted by X local-ave. (a total of pixels with pixels before and pixels after that pixel). Here, the max. operation coists of comparing with the absolute value and assigning the sign of the numerator. BNU=max. ( Xi X X local-ave. ) (%) local-ave. The incident light inteity shall be % of the standard saturation llight inteity. Note 4) Saturation output voltage ( SAT ) This is the output voltage at the point beyond which it is not possible to maintain the linearity of the photoelectric conversion characteristics as the exposure is increased. (The exposure at this point is called the saturation exposure.) Note ) Saturation Exposure (SE) This is the exposure beyond which it is not possible to maintain the linearity of the output voltage as the exposure is increased. When designing the equipment using these devices, make sure that the incident light exposure is set with sufficient margin so that the CCD never gets saturated. Note ) Dark signal output voltage ( DRK ) This is defined as the average of the output from the active pixels in the dark condition at Ta= C, T int =ms. Since normally the dark signal output voltage gets doubled for every to C increase in Ta and is proportional to T int, it is necessary to convert the value if Ta andt int are different from the ipection conditio given above. (See the figure below.) Note ) Dark signal non-uniformity (DSNU) This is defined as the difference between the maximum value among the output voltages from the valid pixels at Ta= C and T int =ms and DRK. (See the figure below.) DRK DSNU Note ) Shift register total trafer efficiency (STTE) This is given by the following equation where the average output voltage of all the pixels is denoted by Xave. and the larger of the output voltages of the dummy pixels following the dummy pixel D4 is denoted by Xr when the photodetector region is illuminated by a light of uniform illumination inteity distribution. STTE= X ave. X r X (%) ave. Note 9) Dynamic range (DR) This is defined by the following equation. DR= SAT DRK Since the dark signal output voltage is proportional to the accumulation time, the dynamic range becomes wider when the accumulation time is shorter. This value is not a guaranteed value, but is merely a reference value. Note ) Modulation trafer function (MTF R ) This is defined by the following equation where the average output voltages of the pixels with the white pattern and the pixels with the black pattern are respectively denoted by W and B when a black and white stripe pattern (in which the black and white patter alternate at every pixel) is projected on the photodetector region in phase (equivalent to the Nyquist spatial frequency). MTF = R W + W B B (%) This value is a measure of resolution of the seor. This parameter is not a guaranteed value but is merely a reference value. Pattern on photodetector Output waveform of CCD B W Zero level

5 MNA CCD Linear Image Seor Pin Descriptio Pin No. Symbol Pin name Condition OS DS OG Signal output Compeation output Output gate 4 R D Reset clock D SS Ground A Internally connected to D. 9 A TG PG Test pin Photo storage gate Internally connected to D. Connect externally to SS. Shift clock gate IS Test pin Connect externally to DD. 4 B Internally connected to C. 9 B SUB C C R DD DS OS Substrate Reset clock Power supply Compeation output Signal output Internally connected to C. Connect externally to DD. Cotruction of the Image Seor The MNA can be made up of the three sectio ofa) photo detector region, b) CCD trafer region (shift register), and c) output region. a) Photo detector region The photoelectric conversion device coists of a µm floating photodiode and a µm channel stopper for each pixel, and of these devices are linearly arranged side by side at a pitch of 9µm. The photo detector's windows are 9µm 9µm squares and light incident on areas other than these windows is optically shut out. The photo detector is provided with optically shielded pixels (black dummy pixels) which serve as the black reference. b) CCD Trafer region (shift register) The light output that has been photoelectrically converted is traferred to the CCD trafer for each odd and even pixel at the timing of the shift clock ( ). The optical signal electric charge traferred to this analog shift register is successively traferred out and guided to the output region. A buried type CCD that can be driven by a two phase clock (, ) is used for the analog shift register. c) Output region The signal charge that is traferred to the output region is sent to the detector where impedance traformation is done using two source follower stages.

6 CCD Linear Image Seor MNA Timing Diagram () I/O timing () Drive timing Signal output voltage (m) t Ss t Sr t Sf 9% % % t SW R R DS OS DS OS t Sh % Graphs and Characteristics Characteristics under standard operating condition Light source: Daylight flourescent lamp ( ) ( ) R ( ) R DS (DS ) OS (OS ) t Cr t Cf 9% t OS Integration Time (Tint.) B B B 9 B D B B B Photoelectric Conversion Characteristics D Relative respoivity (%) t RS T 4 t Rr 9% % % % t RW t Oh Effective signal output period D % D 4 % t Rh 9% % % t Rf Reset field through level Note) Blank feed level Repeat the trafer pulses (, ) for more than 9 periods. () Timing condition measuring circuit Drive circuit A C C A C B B C C C C R C R 4 C C =C =C =pf C =pf C =C =pf Spectral Respoe Characteristics 4 Under standard operating condition Exposure (lx s) 4 Wavelength (nm)

7 MNA CCD Linear Image Seor Drive Circuit Diagram (Digital Section) + GND C.µF Ω R A A B B R 4 Xtal-SC. MHz R 9 R.kΩ C + Ω + + C.µF C9 C µf µf µf C C.µF.µF 9 4 PGTG A A SS D D R OG DSOS MNA R IS B BSUBIC C DD DSOS 4 9 R Ω R Ω EXT INT 9 LS 4 R 4 C 4.µF C.µF R + + Ω 4 9 /- /- LS LS C µf C µf R 4.kΩ R 4 Ω R 9 Ω LS 4 R Ω R kω 9 R kω R9 Ω R R R R4 DSCN kω A C pf A C 4 C C C µf.µf SCA R 4 kω C 4 C 4 µf C 4 R 4 SCA.kΩ R 4 kω.µf R 4 Ω R44 Ω C4 C 4 µf + R 4.kΩ C 44.µF 9 LHCG R4 Ω + C 4 C 4 p + C 49.µF (R49 ~ R,C ~ C, ~ ) DI A C4 LS4 9 R R Ω 9 A EXT C 4 / 9 9 R B LS INT 4 C A C 9 Ω 9 9 R 9 R pf 4 4 R R R Ω A 4 9 R Ω 9 9 C R 4 LS LS LS Ω TRIGGER + 4 R 4 R R 9 4 R C 4pF C C R µf.µf R R R Connect a.µf capacitor between the 4 4 CC and GND pi of each TTL IC (C 9 to C ). 4.kΩ 4.kΩ 4.kΩ A stands for the following circuit. 4 µf Ω (R to R ) (C to C ).µf (C to C ) Drive Circuit Diagram (Analog Section) B A C4µF The circuit configuration of this part is the same as the OS side amplifier. A DD D + R 4 Ω SCA IDEO OUTPUT R 4 kω GND IDEO OUTPUT The drive circuit shown here is sample drive circuit when evaluating the first stage of the MNA and any other drive circuit can be used as long as the operating conditio are satisfied.

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