RF Power LDMOS Transistor N--Channel Enhancement--Mode Lateral MOSFET

Transcription

1 Freescale Semiconductor Technical Data Document Number: AFT18H3574S Rev., 3/214 RF ower LDMOS Transistor N--Channel nhancement--mode Lateral MOSFT This 63 W asymmetrical Doherty RF power LDMOS transistor is designed or cellular base station applications covering the requency range o 185 to 1995 MHz. 18 MHz Typical Doherty Single--Carrier W--CDMA erormance: V DD =28Vdc, I DQA = 8 ma, V GSB =.7Vdc, out = 63 W Avg., Input Signal AR = 9.9 robability on CCDF. G ps (db) Output AR (db) ACR (dbc) MHz, 63 W AVG., 28 V AIRFAST RF OWR LDMOS TRANSISTOR 185 MHz MHz MHz MHz Typical Doherty Single--Carrier W--CDMA erormance: V DD =28Vdc, I DQA = 8 ma, V GSB =.4Vdc, out = 63 W Avg., Input Signal AR = 9.9 robability on CCDF. Frequency G ps (db) Output AR (db) ACR (dbc) NI -123S -4L2L 193 MHz MHz MHz Carrier 6 VBW A (1) Features Advanced High erormance In--ackage Doherty Greater Negative Gate--Source Voltage Range or Improved Class C Operation esigned or Digital redistortion rror Correction Systems In Tape and Reel. R6 Suix = 15 Units, 56 mm Tape Width, 13--inch Reel. RF ina /V GSA RF inb /V GSB eaking 3 (Top View) RF outa /V DSA RF outb /V DSB VBW (1) B Figure 1. in Connections 1. Device cannot operate with the V DD current supplied through pin 3 and pin 6., 214. All rights reserved. 1

2 Table 1. Maximum Ratings Rating Symbol Value Unit Drain--Source Voltage V DSS --.5, +65 Vdc Gate--Source Voltage V GS., +1 Vdc Operating Voltage V DD 32, + Vdc Storage Temperature Range T stg 5 to +15 C Case Operating Temperature Range T C to +15 C Operating Junction Temperature Range (1,2) T J to +225 C CW T C =25 C Derate above 25 C Table 2. Thermal Characteristics CW W W/ C Characteristic Symbol Value (2,3) Unit Thermal Resistance, Junction to Case Case Temperature 79 C, 63 W W--CDMA, 28 Vdc, I DQA = 8 ma, V GSB =.7 Vdc, 184 MHz Table 3. SD rotection Characteristics Test Methodology Human Body Model (per JSD22--A114) 2 Machine Model (per IA/JSD22--A115) Charge Device Model (per JSD22--C11) R JC.43 C/W Table 4. lectrical Characteristics (T A =25 C unless otherwise noted) Characteristic Symbol Min Typ Max Unit O Characteristics (4) Zero Gate Voltage Drain Leakage Current (V DS =65Vdc,V GS =Vdc) I DSS 1 Adc Zero Gate Voltage Drain Leakage Current (V DS =28Vdc,V GS =Vdc) Gate--Source Leakage Current (V GS =5Vdc,V DS =Vdc) On Characteristics - Side A (4) Gate Threshold Voltage (V DS =1Vdc,I D = 14 Adc) Gate Quiescent Voltage (V DD =28Vdc,I DA = 8 madc, Measured in Functional Test) Drain--Source On--Voltage (V GS =1Vdc,I D =1.4Adc) On Characteristics - Side B (4) Gate Threshold Voltage (V DS =1Vdc,I D = 24 Adc) Drain--Source On--Voltage (V GS =1Vdc,I D =2.4Adc) Class I DSS 1 Adc I GSS 1 Adc V GS(th) Vdc V GSA(Q) Vdc V DS(on) Vdc V GS(th) Vdc V DS(on) Vdc 1. Continuous use at maximum temperature will aect MTTF. 2. MTTF calculator available at Select Sotware & Tools/Development Tools/Calculators to access MTTF calculators by product. 3. Reer to AN1955, Thermal Measurement Methodology o RF ower Ampliiers. Go to Select Documentation/Application Notes -- AN ach side o device measured separately. (continued) IV B 2

3 Table 4. lectrical Characteristics (T A =25 C unless otherwise noted) (continued) Characteristic Symbol Min Typ Max Unit Functional Tests (1,2) (In Freescale Doherty Test Fixture, 5 ohm system) V DD =28Vdc,I DQA = 8 ma, V GSB =.7V, out = 63 W Avg., = 185 MHz, Single--Carrier W--CDMA, IQ Magnitude Clipping, Input Signal AR = 9.9 robability on CCDF. ACR measured in 3.84 MHz Channel 5 MHzOset. ower Gain G ps db Drain iciency % Output eak--to--average robability on CCDF AR db Adjacent Channel ower Ratio ACR dbc Load Mismatch (In Freescale Test Fixture, 5 ohm system) I DQA = 8 ma, = 184 MHz, 1 sec ulse Width, 1% Duty Cycle VSWR 1:1 at 32 Vdc, 36 W ulse Output ower No Device Degradation (3 db Input Overdrive rom 21 W ulse Rated ower) Typical erormance (2) (In Freescale Doherty Test Fixture, 5 ohm system) V DD =28Vdc,I DQA = 8 ma, V GSB =.7Vdc, MHz Bandwidth 1 db Compression oint, CW 1dB 22 W 3 db Compression oint (3) 3dB 32 W AM/M (Maximum value measured at the 3dB compression point across the MHz bandwidth) VBW Resonance oint (IMD Third Order Intermodulation Inlection oint) VBW res 11 MHz Gain Flatness in 75 MHz out =63WAvg. G F.2 db Gain Variation over Temperature ( C to+85 C) G.8 db/ C Output ower Variation over Temperature 1dB.9 db/ C ( C to+85 C) (4) 1. art internally matched both on input and output. 2. Measurements made with device in an asymmetrical Doherty coniguration. 3. 3dB = avg + 7. db where avg is the average output power measured using an unclipped W--CDMA single--carrier input signal where output AR is compressed to 7. probability on CCDF. 4. xceeds recommended operating conditions. See CW operation data in Maximum Ratings table. 3

4 V GGA -- C15 V DDA C1 C11 C3 C13 C9 C5 R1 C C21 C7 R3 Z1 AFT18H3574S Rev. 6 D55983 C1 C17 C18 C6 C19 C2 R2 CUT OUT ARA C14 C8 C22 C4 C2 C12 -- V DDB V GGB C16 Figure 2. Test Circuit Component Layout MHz Table 5. Test Circuit Component Designations and Values MHz art Description art Number Manuacturer C1, C2, C3, C4 2 pf Chip Capacitors ATC6F2JT25XT ATC C5, C6 12 pf Chip Capacitors ATC6F12JT25XT ATC C7, C8 8.2 pf Chip Capacitors ATC6F8R2JT25XT ATC C9, C1, C11, C12, C13, C14 1 F Chip Capacitors C575X7S2A16K23KB TDK C15, C16 22 F, 63 V lectrolytic Capacitors SK63M22B5S-115 YAGO C17.8 pf Chip Capacitor ATC6FR8BT25XT ATC C18.9 pf Chip Capacitor ATC6FR9BT25XT ATC C pf Chip Capacitor ATC6F1R2BT25XT ATC C2.2 pf Chip Capacitor ATC6FR2BT25XT ATC C21, C F Chip Capacitors C3225X7R2A225KT TDK R1, R2 2.2, 1/4 W Chip Resistors CRCW1262R2JNA Vishay R3 5, 1 W Chip Resistor CW121T5GBK ATC Z1 17 MHz Band 9, 5 db Directional Coupler X3C191--5S Anaren CB Rogers RO435B,.2, r =3.66 D55983 MTL 4

5 G ps, OWR GAIN (db) TYICAL CHARACTRISTICS MHz V DD =28Vdc, out =63W(Avg.),I DQA = 8 ma V GSB =.7 Vdc, Single--Carrier W--CDMA, 3.84 MHz Channel Bandwidth, Input Signal AR = 9.9 db robability on CCDF G ps ARC ACR 6 17 IRL , FRQUNCY, DRAIN FFICINCY Figure 3. Single -Carrier Output eak -to -Average Ratio Compression (ARC) Broadband out = 63 Watts Avg. ACR (dbc) ARC (db) IMD, INTRMODULATION DISTORTION (dbc) 5 5 V DD =28Vdc, out = 32 W (), I DQA = 8 ma, V GSB =.7Vdc Two--Tone Measurements, (1 + 2)/2 = Center Frequency o 184 MHz IM7--L IM7--U IM3--U IM3--L IM5--L IM5--U TWO--TON SACING Figure 4. Intermodulation Distortion roducts versus Two -Tone Spacing G ps, OWR GAIN (db) OUTUT COMRSSION AT.1% ROBABILITY ON CCDF (db) 1 db = 4 W ACR V DD =28Vdc,I DQA = 8 ma, V GSB =.7Vdc = 184 MHz, Single--Carrier W--CDMA 3.84 MHz Channel Bandwidth, Input Signal AR = 9.9 robability on CCDF db = 63 W db = 85 W ARC G ps RAIN FFICINCY ACR (dbc) out, OUTUT OWR (WATTS) Figure 5. Output eak -to -Average Ratio Compression (ARC) versus Output ower 5

6 G ps, OWR GAIN (db) TYICAL CHARACTRISTICS MHz V DD =28Vdc,I DQA = 8 ma 188 MHz V GSB =.7 Vdc, Single--Carrier W--CDMA, 3.84 MHz Channel Bandwidth 185 MHz 184 MHz ACR G ps 188 MHz 185 MHz 184 MHz 185 MHz 184 MHz 188 MHz Input Signal AR = robability on CCDF out, OUTUT OWR (WATTS) AVG. Figure 6. Single -Carrier W -CDMA ower Gain, Drain iciency and ACR versus Output ower , DRAIN FFICINCY ACR (dbc) Gain 16 GAIN (db) V DD =28Vdc in =dbm 13 I DQA = 8 ma V GSB =.7Vdc , FRQUNCY Figure 7. Broadband Frequency Response 6

7 Table 6. Carrier Side Load ull erormance Maximum ower Tuning V DD =28Vdc,I DQA = 789 ma, ulsed CW, 1 sec(on), 1% Duty Cycle Max Output ower 1dB Z (1) load Gain (db) (dbm) (W) j j j j j j j j j AM/M Max Output ower 3dB Z (2) load Gain (db) (dbm) (W) j j j j j j j j j (1) Load impedance or optimum 1dB power. (2) Load impedance or optimum 3dB power. = Measured impedance presented to the input o the device at the package reerence plane. = Impedance as measured rom gate contact to ground. Z load = Measured impedance presented to the output o the device at the package reerence plane. AM/M Table 7. Carrier Side Load ull erormance Maximum Drain iciency Tuning V DD =28Vdc,I DQA = 789 ma, ulsed CW, 1 sec(on), 1% Duty Cycle Max Drain iciency 1dB Z (1) load Gain (db) (dbm) (W) j j j j j j j j j AM/M Max Drain iciency 3dB Z (2) load Gain (db) (dbm) (W) j j j j j j j j j (1) Load impedance or optimum 1dB eiciency. (2) Load impedance or optimum 3dB eiciency. = Measured impedance presented to the input o the device at the package reerence plane. = Impedance as measured rom gate contact to ground. Z load = Measured impedance presented to the output o the device at the package reerence plane. AM/M Input Load ull Tuner and Test Circuit Device Under Test Output Load ull Tuner and Test Circuit Z load 7

8 Table 8. eaking Side Load ull erormance Maximum ower Tuning V DD =28Vdc,V GSB =.8Vdc, ulsed CW, 1 sec(on), 1% Duty Cycle Max Output ower 1dB Z (1) load Gain (db) (dbm) (W) j j j j j j j j j AM/M Max Output ower 3dB Z (2) load Gain (db) (dbm) (W) j j j j j j j j j (1) Load impedance or optimum 1dB power. (2) Load impedance or optimum 3dB power. = Measured impedance presented to the input o the device at the package reerence plane. = Impedance as measured rom gate contact to ground. Z load = Measured impedance presented to the output o the device at the package reerence plane. AM/M Table 9. eaking Side Load ull erormance Maximum Drain iciency Tuning V DD =28Vdc,V GSB =.8Vdc, ulsed CW, 1 sec(on), 1% Duty Cycle Max Drain iciency 1dB Z (1) load Gain (db) (dbm) (W) j j j j j j j j j AM/M Max Drain iciency 3dB Z (2) load Gain (db) (dbm) (W) j j j j j j j j j (1) Load impedance or optimum 1dB eiciency. (2) Load impedance or optimum 3dB eiciency. = Measured impedance presented to the input o the device at the package reerence plane. = Impedance as measured rom gate contact to ground. Z load = Measured impedance presented to the output o the device at the package reerence plane. AM/M Input Load ull Tuner and Test Circuit Device Under Test Output Load ull Tuner and Test Circuit Z load 8

9 1dB - TYICAL CARRIR SID LOAD ULL CONTOURS 184 MHz IMAGINARY RAL Figure 8. 1dB Load ull Output ower Contours (dbm) IMAGINARY RAL Figure 9. 1dB Load ull iciency Contours IMAGINARY RAL Figure 1. 1dB Load ull Gain Contours (db) IMAGINARY RAL Figure 11. 1dB Load ull AM/M Contours Gain Drain iciency Linearity Output ower NOT: = Maximum Output ower = Maximum Drain iciency 9

10 3dB - TYICAL CARRIR SID LOAD ULL CONTOURS 184 MHz IMAGINARY RAL Figure 12. 3dB Load ull Output ower Contours (dbm) IMAGINARY RAL Figure 13. 3dB Load ull iciency Contours IMAGINARY IMAGINARY RAL Figure 14. 3dB Load ull Gain Contours (db) RAL Figure 15. 3dB Load ull AM/M Contours NOT: = Maximum Output ower Gain Drain iciency Linearity Output ower = Maximum Drain iciency 1

11 1dB - TYICAL AKING SID LOAD ULL CONTOURS 184 MHz IMAGINARY RAL Figure 16. 1dB Load ull Output ower Contours (dbm) IMAGINARY RAL Figure 17. 1dB Load ull iciency Contours IMAGINARY RAL Figure 18. 1dB Load ull Gain Contours (db) 17 IMAGINARY RAL Figure 19. 1dB Load ull AM/M Contours Gain Drain iciency Linearity Output ower NOT: = Maximum Output ower = Maximum Drain iciency 11

12 3dB - TYICAL AKING SID LOAD ULL CONTOURS 184 MHz IMAGINARY RAL Figure 2. 3dB Load ull Output ower Contours (dbm) IMAGINARY RAL Figure 21. 3dB Load ull iciency Contours IMAGINARY RAL Figure 22. 3dB Load ull Gain Contours (db) IMAGINARY RAL Figure 23. 3dB Load ull AM/M Contours Gain Drain iciency Linearity Output ower NOT: = Maximum Output ower = Maximum Drain iciency 12

13 ALTRNAT CHARACTRIZATION MHz V GGA -- C15 V DDA C1 C11 C13 C9 R1 C C3 C7 R3 Z1 AFT18H3574S Rev. 6 C17 C5 C6 C18 C1 R2 CUT OUT ARA C8 C12 C19 D55813 C2 C14 C4 -- C16 V DDB V GGB Figure 24. Test Circuit Component Layout MHz Table 1. Test Circuit Component Designations and Values MHz art Description art Number Manuacturer C1, C2, C3, C4 15 pf Chip Capacitors ATC6F15JT25XT ATC C5, C6, C8 8.2 pf Chip Capacitors ATC6F8R2JT25XT ATC C7 3.9 pf Chip Capacitor ATC6F3R9JT25XT ATC C9, C1, C11, C12, C13, C14 1 F Chip Capacitors C575X7SA16K23KB TDK C15, C16 22 F, 63 V lectrolytic Capacitors SK63M22B5S-115 YAGO C17, C19.2 pf Chip Capacitors ATC6FR2BT25XT ATC C18.9 pf Chip Capacitor ATC6FR9BT25XT ATC R1, R2 2.2, 1/4 W Chip Resistors CRCW1262R2JNA Vishay R3 5, 1 W Chip Resistor CW121T5GBK ATC Z1 17 MHz Band 9, 5 db Directional Coupler X3C191--5S Anaren CB Rogers RO435B,.2, r =3.66 D55813 MTL 13

14 G ps, OWR GAIN (db) TYICAL CHARACTRISTICS MHz V DD =28Vdc, out =63W(Avg.)I DQA = 8 ma V 5.5 GSB =.4 Vdc, Single--Carrier W--CDMA, 3.84 MHz Channel Bandwidth, Input Signal AR = 9.9 db robability on CCDF ARC ACR , FRQUNCY Figure 25. Single -Carrier Output eak -to -Average Ratio Compression (ARC) Broadband out = 63 Watts Avg. G ps , DRAIN FFICINCY ACR (dbc) ARC (db) G ps, OWR GAIN (db) V DD =28Vdc,I DQA = 8 ma V GSB =.4Vdc Single--Carrier W--CDMA 193 MHz 196 MHz 1995 MHz 1995 MHz 196 MHz 193 MHz 1995 MHz 193 MHz out, OUTUT OWR (WATTS) AVG. ACR 196 MHz 3.84 MHz Channel Bandwidth 1 Input Signal AR = 9.9 robability on CCDF G ps Figure 26. Single -Carrier W -CDMA ower Gain, Drain iciency and ACR versus Output ower , DRAIN FFICINCY ACR (dbc) 2 18 Gain 16 GAIN (db) V DD =28Vdc in =dbm 1 I DQA = 8 ma V GSB =.4Vdc , FRQUNCY Figure 27. Broadband Frequency Response 14

15 Table 11. Carrier Side Load ull erormance Maximum ower Tuning V DD =28Vdc,I DQA = 79 ma, ulsed CW, 1 sec(on), 1% Duty Cycle Max Output ower 1dB Z (1) load Gain (db) (dbm) (W) j j j j j j j j j AM/M Max Output ower 3dB Z (2) load Gain (db) (dbm) (W) j j j j j j j j j (1) Load impedance or optimum 1dB power. (2) Load impedance or optimum 3dB power. = Measured impedance presented to the input o the device at the package reerence plane. = Impedance as measured rom gate contact to ground. Z load = Measured impedance presented to the output o the device at the package reerence plane. AM/M Table 12. Carrier Side Load ull erormance Maximum Drain iciency Tuning V DD =28Vdc,I DQA = 79 ma, ulsed CW, 1 sec(on), 1% Duty Cycle Max Drain iciency 1dB Z (1) load Gain (db) (dbm) (W) j j j j j j j j j AM/M Max Drain iciency 3dB Z (2) load Gain (db) (dbm) (W) j j j j j j j j j (1) Load impedance or optimum 1dB eiciency. (2) Load impedance or optimum 3dB eiciency. = Measured impedance presented to the input o the device at the package reerence plane. = Impedance as measured rom gate contact to ground. Z load = Measured impedance presented to the output o the device at the package reerence plane. AM/M Input Load ull Tuner and Test Circuit Device Under Test Output Load ull Tuner and Test Circuit Z load 15

16 Table 13. eaking Side Load ull erormance Maximum ower Tuning V DD =28Vdc,V GSB =.8Vdc, ulsed CW, 1 sec(on), 1% Duty Cycle Max Output ower 1dB Z (1) load Gain (db) (dbm) (W) j j j j j j j j j AM/M Max Output ower 3dB Z (2) load Gain (db) (dbm) (W) j j j j j j j j j (1) Load impedance or optimum 1dB power. (2) Load impedance or optimum 3dB power. = Measured impedance presented to the input o the device at the package reerence plane. = Impedance as measured rom gate contact to ground. Z load = Measured impedance presented to the output o the device at the package reerence plane. AM/M Table 14. eaking Side Load ull erormance Maximum Drain iciency Tuning V DD =28Vdc,V GSB =.8Vdc, ulsed CW, 1 sec(on), 1% Duty Cycle Max Drain iciency 1dB Z (1) load Gain (db) (dbm) (W) j j j j j j j j j AM/M Max Drain iciency 3dB Z (2) load Gain (db) (dbm) (W) j j j j j j j j j (1) Load impedance or optimum 1dB eiciency. (2) Load impedance or optimum 3dB eiciency. = Measured impedance presented to the input o the device at the package reerence plane. = Impedance as measured rom gate contact to ground. Z load = Measured impedance presented to the output o the device at the package reerence plane. AM/M Input Load ull Tuner and Test Circuit Device Under Test Output Load ull Tuner and Test Circuit Z load 16

17 1dB - TYICAL CARRIR SID LOAD ULL CONTOURS 196 MHz IMAGINARY RAL Figure 28. 1dB Load ull Output ower Contours (dbm) IMAGINARY RAL Figure 29. 1dB Load ull iciency Contours IMAGINARY RAL Figure 3. 1dB Load ull Gain Contours (db) IMAGINARY RAL Figure 31. 1dB Load ull AM/M Contours Gain Drain iciency Linearity Output ower NOT: = Maximum Output ower = Maximum Drain iciency 17

18 3dB - TYICAL CARRIR SID LOAD ULL CONTOURS 196 MHz IMAGINARY RAL RAL Figure 32. 3dB Load ull Output ower Contours (dbm) Figure 33. 3dB Load ull iciency Contours IMAGINARY IMAGINARY RAL Figure 34. 3dB Load ull Gain Contours (db) IMAGINARY RAL Figure 35. 3dB Load ull AM/M Contours Gain Drain iciency Linearity Output ower NOT: = Maximum Output ower = Maximum Drain iciency 18

19 1dB - TYICAL AKING SID LOAD ULL CONTOURS 196 MHz IMAGINARY RAL Figure 36. 1dB Load ull Output ower Contours (dbm) IMAGINARY RAL Figure 38. 1dB Load ull Gain Contours (db) IMAGINARY IMAGINARY RAL Figure 37. 1dB Load ull iciency Contours RAL Figure 39. 1dB Load ull AM/M Contours Gain Drain iciency Linearity Output ower NOT: = Maximum Output ower = Maximum Drain iciency 19

20 3dB - TYICAL AKING SID LOAD ULL CONTOURS 196 MHz IMAGINARY IMAGINARY RAL 5.5 Figure 4. 3dB Load ull Output ower Contours (dbm) RAL Figure 42. 3dB Load ull Gain Contours (db) IMAGINARY IMAGINARY --8 RAL 6 58 Figure 41. 3dB Load ull iciency Contours RAL Figure 43. 3dB Load ull AM/M Contours Gain Drain iciency Linearity Output ower NOT: = Maximum Output ower = Maximum Drain iciency 2

21 ACKAG DIMNSIONS 21

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23 RODUCT DOCUMNTATION, SOFTWAR AND TOOLS Reer to the ollowing resources to aid your design process. Application Notes AN1955: Thermal Measurement Methodology o RF ower Ampliiers ngineering Bulletins B212: Using Data Sheet Impedances or RF LDMOS Devices Sotware lectromigration MTTF Calculator RF High ower Model.s2p File Development Tools rinted Circuit Boards For Sotware and Tools, do a art Number search at and select the art Number link. Go to the Sotware & Tools tab on the part s roduct Summary page to download the respective tool. RVISION HISTORY The ollowing table summarizes revisions to this document. Revision Date Description Mar. 214 Initial Release o Data Sheet 23

24 How to Reach Us: Home age: reescale.com Web Support: reescale.com/support Inormation in this document is provided solely to enable system and sotware implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or abricate any integrated circuits based on the inormation in this document. Freescale reserves the right to make changes without urther notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability o its products or any particular purpose, nor does Freescale assume any liability arising out o the application or use o any product or circuit, and speciically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters that may be provided in Freescale data sheets and/or speciications can and do vary in dierent applications, and actual perormance may vary over time. All operating parameters, including typicals, must be validated or each customer application by customer s technical experts. Freescale does not convey any license under its patent rights nor the rights o others. Freescale sells products pursuant to standard terms and conditions o sale, which can be ound at the ollowing address: reescale.com/salestermsandconditions. Freescale and the Freescale logo are trademarks o, Reg. U.S. at. & Tm. O. Airast is a trademark o All other product or service names are the property o their respective owners. 214 Document Number: AFT18H3574S 24 Rev., 3/214