RF Power LDMOS Transistor N--Channel Enhancement--Mode Lateral MOSFET

Transcription

1 Freescale Semiconductor Technical Data RF ower LDMOS Transistor N--Channel nhancement--mode Lateral MOSFT This 3 W symmetrical Doherty RF power LDMOS transistor is designed or cellular base station applications requiring very wide instantaneous bandwidth capability covering the requency range o 716 to 96 MHz. Document Number: AT7D16W4S Rev., 8/14 AT7D16W4SR3 78 MHz Typical Doherty Single--Carrier W--CDMA erormance: V DD =8Vdc, I DQA = 45 ma, V GSB =1.Vdc, out = 3 W Avg., Input Signal AR = 9.9 robability on CCDF. Frequency G ps (db) Output AR (db) ACR (dbc) 758 MHz MHz MHz MHz, 3 W AVG., 8 V AIRFAST RF OWR LDMOS TRANSISTOR 88 MHz Typical Doherty Single--Carrier W--CDMA erormance: V DD =8Vdc, I DQA = 45 ma, V GSB =1.3Vdc, out = 3 W Avg., Input Signal AR = 9.9 robability on CCDF. NI -78S -4L Frequency G ps (db) Output AR (db) ACR (dbc) 865 MHz MHz Carrier 895 MHz RF ina /V GSA 3 1 RF outa /V DSA Features esigned or Wide Instantaneous Bandwidth Applications Greater Negative Gate--Source Voltage Range or Improved Class C Operation Able to Withstand xtremely High Output VSWR and Broadband Operating Conditions esigned or Digital redistortion rror Correction Systems In Tape and Reel. R3 Suix = 5 Units, 3 mm Tape Width, 13--inch Reel. RF inb /V GSB (1) 4 RF outb /V DSB eaking (Top View) Figure 1. in Connections 1. in connections 1 and are DC coupled and RF independent., 14. All rights reserved. AT7D16W4SR3 1

2 Table 1. Maximum Ratings Rating Symbol Value Unit Drain--Source Voltage V DSS.5, +7 Vdc Gate--Source Voltage V GS 6., +1 Vdc Operating Voltage V DD 3, + Vdc Storage Temperature Range T stg 65 to +15 C Case Operating Temperature Range T C 4 to +15 C Operating Junction Temperature Range (1,) T J 4 to +5 C CW T C =5 C Derate above 5 C Table. Thermal Characteristics CW W W/ C Characteristic Symbol Value (,3) Unit Thermal Resistance, Junction to Case Case Temperature 77 C, 3 W W--CDMA, 8 Vdc, I DQA = 45 ma, V GSB = 1. Vdc, 78 MHz Table 3. SD rotection Characteristics Test Methodology Human Body Model (per JSD--A114) Machine Model (per IA/JSD--A115) Charge Device Model (per JSD--C11) R JC.63 C/W Table 4. lectrical Characteristics (T A =5 C unless otherwise noted) Characteristic Symbol Min Typ Max Unit O Characteristics (4,5) Zero Gate Voltage Drain Leakage Current (V DS =7Vdc,V GS =Vdc) Class I DSS 1 Adc A IV Zero Gate Voltage Drain Leakage Current (V DS =3Vdc,V GS =Vdc) Gate--Source Leakage Current (V GS =5Vdc,V DS =Vdc) On Characteristics - Side A (4,6) (Carrier) Gate Threshold Voltage (V DS =1Vdc,I D =11 Adc) Gate Quiescent Voltage (V DD =8Vdc,I DA = 45 madc, Measured in Functional Test) Drain--Source On--Voltage (V GS =1Vdc,I D =1.1Adc) On Characteristics - Side B (4,6) (eaking) Gate Threshold Voltage (V DS =1Vdc,I D =11 Adc) Drain--Source On--Voltage (V GS =1Vdc,I D =1.1Adc) I DSS 5 Adc I GSS 1 Adc V GS(th) Vdc V GS(Q) Vdc V DS(on) Vdc V GS(th) Vdc V DS(on).5..3 Vdc 1. Continuous use at maximum temperature will aect MTTF.. MTTF calculator available at Select Sotware & Tools/Development Tools/Calculators to access MTTF calculators by product. 3. Reer to AN1955, Thermal Measurement Methodology o RF ower Ampliiers. Go to Select Documentation/Application Notes -- AN V DDA and V DDB must be tied together and powered by a single DC power supply. 5. Side A and Side B are tied together or these measurements. 6. ach side o device measured separately. (continued) AT7D16W4SR3

3 Table 4. lectrical Characteristics (T A =5 C unless otherwise noted) (continued) Characteristic Symbol Min Typ Max Unit Functional Tests (1,,3) (In Freescale Doherty Test Fixture, 5 ohm system) V DD =8Vdc,I DQA = 45 ma, V GSB =1.Vdc, out =3WAvg., = 83 MHz, Single--Carrier W--CDMA, IQ Magnitude Clipping, Input Signal AR = 9.9 robability on CCDF. ACR measured in 3.84 MHz Channel 5 MHzOset. ower Gain G ps db Drain iciency % Output eak--to--average robability on CCDF AR db Adjacent Channel ower Ratio ACR dbc Load Mismatch (3) (In Freescale Doherty Test Fixture, 5 ohm system) I DQA = 45 ma, V GSB =1.Vdc,=78MHz VSWR 1:1 at 3 Vdc, 13 W ulse Output ower No Device Degradation (3 db Input Overdrive rom 85 W ulse Rated ower) Typical erormance (3) (In Freescale Doherty Test Fixture, 5 ohm system) V DD =8Vdc,I DQA = 45 ma, V GSB =1.Vdc, 758 to 83 MHz Bandwidth 1 db Compression oint, CW 1dB 79 W 3 db Compression oint (4) 3dB 186 W AM/M (Maximum value measured at the 3dB compression point across the MHz requency range) 18 VBW Resonance oint (IMD Third Order Intermodulation Inlection oint) VBW res 1 MHz Gain Flatness in 45 MHz out =3WAvg. G F.4 db Gain Variation over Temperature ( 3 C to+85 C) G.1 db/ C Output ower Variation over Temperature 1dB.3 db/ C ( 3 C to+85 C) (5) 1. V DDA and V DDB must be tied together and powered by a single DC power supply.. art internally matched both on input and output. 3. Measurement made with device in a symmetrical Doherty coniguration. 4. 3dB = avg + 7. db where avg is the average output power measured using an unclipped W--CDMA single--carrier input signal where output AR is compressed to 7. probability on CCDF. 5. xceeds recommended operating conditions. See CW operation data in Maximum Ratings table. AT7D16W4SR3 3

4 C31 -- C35 C3 V DDA V GGA C3 C8 R1 C7 R3 Z1 C8 R C9 C7 C1 C13 C9 C1 C14 C C11 C1 C15 C3 C C16 CUT OUT ARA C17 C C18 C1 C19 C C6 C3 C5 C4 C5 C6 V GGB C4 C34 V DDB AT7D16W4S Rev. 3 C33 -- C36 D5868 Note: V DDA and V DDB must be tied together and powered by a single DC power supply. Figure. AT7D16W4SR3 Test Circuit Component Layout MHz Table 5. AT7D16W4SR3 Test Circuit Component Designations and Values MHz art Description art Number Manuacturer C1, C, C3, C4, C5, C6 1 pf Chip Capacitors ATC6F11JT5XT ATC C7, C8 3 pf Chip Capacitors ATC6F3JT5XT ATC C9, C1, C11, C1 3.3 pf Chip Capacitors ATC6F3R3BT5XT ATC C13, C pf Chip Capacitors ATC6F4R7BT5XT ATC C14, C pf Chip Capacitors ATC6F6R8BT5XT ATC C17, C pf Chip Capacitors ATC6F5R6BT5XT ATC C19, C, C1, C 3.9 pf Chip Capacitors ATC6F3R9BT5XT ATC C3, C4, C5, C6.7 pf Chip Capacitors ATC6FR7BT5XT ATC C7, C3 1 F Chip Capacitors GRM31CR61H16KA1 Muruta C8, C9, C31, C33 1 F Chip Capacitors GRM31CR7A15KA1L Muruta C3, C34 1 F Chip Capacitors C575X7SA16M3KB TDK C35, C36 33 F, 63 V lectrolytic Capacitors MCRH63V337M13X1--RH Multicomp R1, R., 1/4 W Chip Resistors CRCW16RJNA Vishay R3 5, 1 W Termination 81A F Florida RF Labs Z1 6 9 MHz Band, 9, 3 db Hybrid Coupler CMX7Q3 RN Technologies CB Rogers RO435B,., r =3.66 D5868 MTL AT7D16W4SR3 4

5 TYICAL CHARACTRISTICS MHz G ps, OWR GAIN (db) 6 54 V DD =8Vdc, out =3W(Avg.),I DQA = 45 ma, V GSB =1.Vdc 5 Single--Carrier W--CDMA, 3.84 MHz Channel Bandwidth 5 4 Input Signal AR = 9.9 robability on CCDF G ps 1 4 ARC ACR , FRQUNCY, DRAIN FFICINCY Figure 3. Single -Carrier Output eak -to -Average Ratio Compression (ARC) Broadband out = 3 Watts Avg. ACR (dbc) ARC (db) IMD, INTRMODULATION DISTORTION (dbc) V DD =8Vdc, out = 3 W (), I DQA = 45 ma V GSB = 1. Vdc, Two--Tone Measurements (1 + )/ = Center Frequency o 78 MHz IM3--U IM5--U IM7--L IM3--L IM5--L IM7--U TWO--TON SACING Figure 4. Intermodulation Distortion roducts versus Two -Tone Spacing G ps, OWR GAIN (db) OUTUT COMRSSION AT.1% ROBABILITY ON CCDF (db) V DD =8Vdc,I DQA = 45 ma, V GSB =1.Vdc = 78 MHz, Single--Carrier W--CDMA --1dB=13.5W ACR db=19.9w 3.84 MHz Channel Bandwidth Input Signal AR = 9.9 robability on CCDF dB=3.W --5 ARC G ps RAIN FFICINCY ACR (dbc) out, OUTUT OWR (WATTS) Figure 5. Output eak -to -Average Ratio Compression (ARC) versus Output ower AT7D16W4SR3 5

6 TYICAL CHARACTRISTICS MHz 4 V DD =8Vdc,I DQA = 45 ma, V GSB =1.Vdc Single--Carrier W--CDMA G ps, OWR GAIN (db) 83 MHz MHz 78 MHz ACR MHz MHz 78 MHz 78 MHz MHz 83 MHz G ps MHz Channel Bandwidth 1 Input Signal AR = robability on CCDF out, OUTUT OWR (WATTS) AVG. Figure 6. Single -Carrier W -CDMA ower Gain, Drain iciency and ACR versus Output ower, DRAIN FFICINCY ACR (dbc) 4 Gain GAIN (db) V DD =8Vdc in =dbm I DQA = 45 ma V GSB =1.Vdc , FRQUNCY Figure 7. Broadband Frequency Response AT7D16W4SR3 6

7 Table 6. Carrier Side Load ull erormance Maximum ower Tuning V DD =8Vdc,I DQA = 438 ma, ulsed CW, 1 sec(on), 1% Duty Cycle Max Output ower 1dB Z (1) load Gain (db) (dbm) (W) j j j j j5.57. j j j j AM/M Max Output ower 3dB Z () load Gain (db) (dbm) (W) j j4.8.8 j j j j j j j (1) Load impedance or optimum 1dB power. () Load impedance or optimum 3dB power. = Measured impedance presented to the input o the device at the package reerence plane. = Impedance as measured rom gate contact to ground. Z load = Measured impedance presented to the output o the device at the package reerence plane. AM/M Table 7. Carrier Side Load ull erormance Maximum Drain iciency Tuning V DD =8Vdc,I DQA = 438 ma, ulsed CW, 1 sec(on), 1% Duty Cycle Max Drain iciency 1dB Z (1) load Gain (db) (dbm) (W) j j j j j j j j j AM/M Max Drain iciency 3dB Z () load Gain (db) (dbm) (W) j j j j j j j j j (1) Load impedance or optimum 1dB eiciency. () Load impedance or optimum 3dB eiciency. = Measured impedance presented to the input o the device at the package reerence plane. = Impedance as measured rom gate contact to ground. Z load = Measured impedance presented to the output o the device at the package reerence plane. AM/M Input Load ull Tuner and Test Circuit Device Under Test Output Load ull Tuner and Test Circuit Z load AT7D16W4SR3 7

8 Table 8. eaking Side Load ull erormance Maximum ower Tuning V DD =8Vdc,V GSB =1.Vdc, ulsed CW, 1 sec(on), 1% Duty Cycle Max Output ower 1dB Z (1) load Gain (db) (dbm) (W) j j j j j j j j j AM/M Max Output ower 3dB Z () load Gain (db) (dbm) (W) j j j j j j j j j (1) Load impedance or optimum 1dB power. () Load impedance or optimum 3dB power. = Measured impedance presented to the input o the device at the package reerence plane. = Impedance as measured rom gate contact to ground. Z load = Measured impedance presented to the output o the device at the package reerence plane. AM/M Table 9. eaking Side Load ull erormance Maximum Drain iciency Tuning V DD =8Vdc,V GSB =1.Vdc, ulsed CW, 1 sec(on), 1% Duty Cycle Max Drain iciency 1dB Z (1) load Gain (db) (dbm) (W) j j j j j j j j j AM/M Max Drain iciency 3dB Z () load Gain (db) (dbm) (W) j j j j j j j j j (1) Load impedance or optimum 1dB eiciency. () Load impedance or optimum 3dB eiciency. = Measured impedance presented to the input o the device at the package reerence plane. = Impedance as measured rom gate contact to ground. Z load = Measured impedance presented to the output o the device at the package reerence plane. AM/M Input Load ull Tuner and Test Circuit Device Under Test Output Load ull Tuner and Test Circuit Z load AT7D16W4SR3 8

9 1dB - TYICAL CARRIR SID LOAD ULL CONTOURS 79 MHz IMAGINARY RAL Figure 8. 1dB Load ull Output ower Contours (dbm) IMAGINARY RAL Figure 9. 1dB Load ull iciency Contours --18 IMAGINARY RAL Figure 1. 1dB Load ull Gain Contours (db) IMAGINARY RAL Figure 11. 1dB Load ull AM/M Contours NOT: = Maximum Output ower Gain Drain iciency Linearity Output ower = Maximum Drain iciency AT7D16W4SR3 9

10 3dB - TYICAL CARRIR SID LOAD ULL CONTOURS 79 MHz IMAGINARY RAL Figure 1. 3dB Load ull Output ower Contours (dbm) IMAGINARY RAL Figure 13. 3dB Load ull iciency Contours IMAGINARY RAL Figure 14. 3dB Load ull Gain Contours (db) IMAGINARY RAL Figure 15. 3dB Load ull AM/M Contours Gain Drain iciency Linearity Output ower NOT: = Maximum Output ower = Maximum Drain iciency AT7D16W4SR3 1

11 1dB - TYICAL AKING SID LOAD ULL CONTOURS 79 MHz IMAGINARY RAL Figure 16. 1dB Load ull Output ower Contours (dbm) IMAGINARY RAL Figure 17. 1dB Load ull iciency Contours IMAGINARY RAL Figure 18. 1dB Load ull Gain Contours (db) IMAGINARY RAL Figure 19. 1dB Load ull AM/M Contours Gain Drain iciency Linearity Output ower NOT: = Maximum Output ower = Maximum Drain iciency AT7D16W4SR3 11

12 3dB - TYICAL AKING SID LOAD ULL CONTOURS 79 MHz IMAGINARY RAL Figure. 3dB Load ull Output ower Contours (dbm) IMAGINARY RAL Figure 1. 3dB Load ull iciency Contours IMAGINARY RAL 16 Figure. 3dB Load ull Gain Contours (db) IMAGINARY RAL Figure 3. 3dB Load ull AM/M Contours Gain Drain iciency Linearity Output ower NOT: = Maximum Output ower = Maximum Drain iciency AT7D16W4SR3 1

13 MHz CHARACTRISTICS -- C7 V DDA C5 V GGA C3 C3 C R1 C7 R3 Z1 J1 J R C1 C9 C8 C19 C1 C11 C C1 C1 C C CUT OUT ARA C13 C14 C15 C16 J3 C18 C17 C5 C6 D59371 V GGB C4 C4 V DDB C6 AT7D16W4S MHz Rev C8 Note: V DDA and V DDB must be tied together and powered by a single DC power supply. Figure 4. AT7D16W4SR3 Test Circuit Component Layout MHz Table 1. AT7D16W4SR3 Test Circuit Component Designations and Values MHz art Description art Number Manuacturer C1, C, C3, C4, C5, C6 1 pf Chip Capacitors ATC6F11JT5XT ATC C7, C8 3 pf Chip Capacitors ATC6F3JT5XT ATC C9, C1 3.3 pf Chip Capacitors ATC6F3R3BT5XT ATC C11, C1 4.7 pf Chip Capacitors ATC6F4R7BT5XT ATC C13, C14, C15, C pf Chip Capacitors ATC6F5R6BT5XT ATC C17, C18.7 pf Chip Capacitors ATC6FR7BT5XT ATC C19, C 1 F Chip Capacitors GRM31CR61H16KA1 Muruta C, C1, C3, C4 1 F Chip Capacitors GRM31CR7A15KA1L Muruta C5, C6 1 F Chip Capacitors C575X7SA16M3KB TDK C7, C8 33 F, 63 V lectrolytic Capacitors MCRH63V337M13X1--RH Multicomp J1, J, J3 Copper Foil R1, R., 1/4 W Chip Resistors CRCW16RJNA Vishay R3 5, 1 W Termination 81A F Florida RF Labs Z1 6 9 MHz Band, 9, 3 db Hybrid Coupler CMX7Q3 RN Technologies CB Rogers RO435B,., r =3.66 D59371 MTL AT7D16W4SR3 13

14 G ps, OWR GAIN (db) TYICAL CHARACTRISTICS MHz V DD =8Vdc, out =3W(Avg.)I DQA = 45 ma V GSB = 1.3 Vdc Single--Carrier W--CDMA 3.84 MHz Channel Bandwidth, Input Signal AR = 9.9 robability on CCDF, FRQUNCY ARC ACR Figure 5. Single -Carrier Output eak -to -Average Ratio Compression (ARC) Broadband out = 3 Watts Avg. G ps , DRAIN FFICINCY ACR (dbc) ARC (db) 6 4 V DD =8Vdc,I DQA = 45 ma V GSB =1.3Vdc 88 MHz 895 MHz 865 MHz G ps, OWR GAIN (db) G ps 895 MHz ACR 865 MHz 88 MHz 865 MHz Single--Carrier W--CDMA 3.84 MHz Channel Bandwidth Input Signal AR = 9.9 db 1 robability on CCDF 1 1 out, OUTUT OWR (WATTS) AVG. 895 MHz 88 MHz Figure 6. Single -Carrier W -CDMA ower Gain, Drain iciency and ACR versus Output ower 4 3, DRAIN FFICINCY --3 ACR (dbc) Gain GAIN (db) V DD =8Vdc in =dbm I DQA = 45 ma V GSB =1.3Vdc , FRQUNCY Figure 7. Broadband Frequency Response AT7D16W4SR3 14

15 Table 11. Carrier Side Load ull erormance Maximum ower Tuning V DD =8Vdc,I DQA = 434 ma, ulsed CW, 1 sec(on), 1% Duty Cycle Max Output ower 1dB Z (1) load Gain (db) (dbm) (W) j j j j j j j j j AM/M Max Output ower 3dB Z () load Gain (db) (dbm) (W) j j j j j j j j j (1) Load impedance or optimum 1dB power. () Load impedance or optimum 3dB power. = Measured impedance presented to the input o the device at the package reerence plane. = Impedance as measured rom gate contact to ground. Z load = Measured impedance presented to the output o the device at the package reerence plane. AM/M Table 1. Carrier Side Load ull erormance Maximum Drain iciency Tuning V DD =8Vdc,I DQA = 434 ma, ulsed CW, 1 sec(on), 1% Duty Cycle Max Drain iciency 1dB Z (1) load Gain (db) (dbm) (W) j j j j j j j j j AM/M Max Drain iciency 3dB Z () load Gain (db) (dbm) (W) j j j j j j j j j (1) Load impedance or optimum 1dB eiciency. () Load impedance or optimum 3dB eiciency. = Measured impedance presented to the input o the device at the package reerence plane. = Impedance as measured rom gate contact to ground. Z load = Measured impedance presented to the output o the device at the package reerence plane. AM/M Input Load ull Tuner and Test Circuit Device Under Test Output Load ull Tuner and Test Circuit Z load AT7D16W4SR3 15

16 Table 13. eaking Side Load ull erormance Maximum ower Tuning V DD =8Vdc,V GSB =1.Vdc, ulsed CW, 1 sec(on), 1% Duty Cycle Max Output ower 1dB Z (1) load Gain (db) (dbm) (W) j j j j j j j j j AM/M Max Output ower 3dB Z () load Gain (db) (dbm) (W) j j j j j j j j j (1) Load impedance or optimum 1dB power. () Load impedance or optimum 3dB power. = Measured impedance presented to the input o the device at the package reerence plane. = Impedance as measured rom gate contact to ground. Z load = Measured impedance presented to the output o the device at the package reerence plane. AM/M Table 14. eaking Side Load ull erormance Maximum Drain iciency Tuning V DD =8Vdc,V GSB =1.Vdc, ulsed CW, 1 sec(on), 1% Duty Cycle Max Drain iciency 1dB Z (1) load Gain (db) (dbm) (W) j j j j j j j j j AM/M Max Drain iciency 3dB Z () load Gain (db) (dbm) (W) j j j j j j j j j (1) Load impedance or optimum 1dB eiciency. () Load impedance or optimum 3dB eiciency. = Measured impedance presented to the input o the device at the package reerence plane. = Impedance as measured rom gate contact to ground. Z load = Measured impedance presented to the output o the device at the package reerence plane. AM/M Input Load ull Tuner and Test Circuit Device Under Test Output Load ull Tuner and Test Circuit Z load AT7D16W4SR3 16

17 1dB - TYICAL CARRIR SID LOAD ULL CONTOURS 88 MHz IMAGINARY RAL Figure 8. 1dB Load ull Output ower Contours (dbm) IMAGINARY RAL Figure 9. 1dB Load ull iciency Contours IMAGINARY RAL Figure 3. 1dB Load ull Gain Contours (db) IMAGINARY RAL Figure 31. 1dB Load ull AM/M Contours Gain Drain iciency Linearity Output ower NOT: = Maximum Output ower = Maximum Drain iciency AT7D16W4SR3 17

18 3dB - TYICAL CARRIR SID LOAD ULL CONTOURS 88 MHz 6 IMAGINARY RAL Figure 3. 3dB Load ull Output ower Contours (dbm) IMAGINARY RAL Figure 33. 3dB Load ull iciency Contours IMAGINARY RAL Figure 34. 3dB Load ull Gain Contours (db) IMAGINARY RAL Figure 35. 3dB Load ull AM/M Contours Gain Drain iciency Linearity Output ower NOT: = Maximum Output ower = Maximum Drain iciency AT7D16W4SR3 18

19 1dB - TYICAL AKING SID LOAD ULL CONTOURS 88 MHz IMAGINARY IMAGINARY RAL Figure 36. 1dB Load ull Output ower Contours (dbm) RAL Figure 37. 1dB Load ull iciency Contours IMAGINARY RAL Figure 38. 1dB Load ull Gain Contours (db) IMAGINARY RAL Figure 39. 1dB Load ull AM/M Contours NOT: = Maximum Output ower Gain Drain iciency Linearity Output ower = Maximum Drain iciency AT7D16W4SR3 19

20 3dB - TYICAL AKING SID LOAD ULL CONTOURS 88 MHz 64 6 IMAGINARY RAL Figure 4. 3dB Load ull Output ower Contours (dbm) IMAGINARY RAL Figure 41. 3dB Load ull iciency Contours IMAGINARY IMAGINARY RAL Figure 4. 3dB Load ull Gain Contours (db) RAL Figure 43. 3dB Load ull AM/M Contours Gain Drain iciency Linearity Output ower NOT: = Maximum Output ower = Maximum Drain iciency AT7D16W4SR3

21 ACKAG DIMNSIONS AT7D16W4SR3 1

22 AT7D16W4SR3

23 RODUCT DOCUMNTATION, SOFTWAR AND TOOLS Reer to the ollowing resources to aid your design process. Application Notes AN1955: Thermal Measurement Methodology o RF ower Ampliiers ngineering Bulletins B1: Using Data Sheet Impedances or RF LDMOS Devices Sotware lectromigration MTTF Calculator RF High ower Model.sp File Development Tools rinted Circuit Boards For Sotware and Tools, do a art Number search at and select the art Number link. Go to the Sotware & Tools tab on the part s roduct Summary page to download the respective tool. The ollowing table summarizes revisions to this document. RVISION HISTORY Revision Date Description Aug. 14 Initial Release o Data Sheet AT7D16W4SR3 3

24 How to Reach Us: Home age: reescale.com Web Support: reescale.com/support Inormation in this document is provided solely to enable system and sotware implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or abricate any integrated circuits based on the inormation in this document. Freescale reserves the right to make changes without urther notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability o its products or any particular purpose, nor does Freescale assume any liability arising out o the application or use o any product or circuit, and speciically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters that may be provided in Freescale data sheets and/or speciications can and do vary in dierent applications, and actual perormance may vary over time. All operating parameters, including typicals, must be validated or each customer application by customer s technical experts. Freescale does not convey any license under its patent rights nor the rights o others. Freescale sells products pursuant to standard terms and conditions o sale, which can be ound at the ollowing address: reescale.com/salestermsandconditions. Freescale and the Freescale logo are trademarks o, Reg. U.S. at. & Tm. O. Airast is a trademark o All other product or service names are the property o their respective owners. 14 AT7D16W4SR3 Document Number: AT7D16W4S Rev. 4, 8/14