A VLSI Design for Digital Pre-distortion with Pipelined CORDIC Processors

Transcription

1 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.14, NO.6, DECEMBER, 2014 A VLSI Design for Digitl Pre-distortion with Pipelined CORDIC Processors Jong Kng Prk 1, Jun Young Moon 2, Kunghoon Kim 2, Youngoo Yng 1, nd Jong Te Kim 1,* Astrct In wireless communictions sstem, pre-distorter is often used to compenste for the nonliner distortions tht result from operting power mplifier ner the sturtion region, there improving sstem performnce nd incresing the spectrl efficienc for the communiction chnnels. This pper presents new VLSI design for the polnomil digitl pre-distorter (DPD). The proposed DPD uses Coordinte Rottion Digitl Computing (CORDIC) processor nd PD process with fullpipelined rchitecture. Due to its simple nd regulr structure, it cn e competitive design when compred to eisting polnomil-tpe nd pproimted DPDs. Implementing fifth-order distorter with the proposed design requires onl 43,000 logic gtes in 0.35 μm CMOS stndrd cell lirr. Inde Terms Power mplifier, pre-distorter, digitl pre-distorter, CORDIC, pipelined pre-distorter I. INTRODUCTION Conventionl rdio-frequenc power mplifiers (PA) operting with widend signls, such s tht of widend code division multiple ccess (WCDMA) nd wireless locl re network (WLAN), require high linerit due to spectrl efficienc provided. PA linerit Mnuscript received M. 5, 2014; ccepted Oct. 24, School of Electronic nd Electricl Eng., Sungkunkwn Univ., 300 Cheoncheon-dong Jngn-gu, Suwon, Geonggi-do , South Kore 2 Dept. of IT Convergence, Sungkunkwn Univ., 300 Cheoncheondong Jngn-gu, Suwon, Geonggi-do , South Kore E-mil : jtkim@skku.edu tht is used in vrile mplitude modultion methods is lso importnt with respect to trnsmission errors nd interference to djcent chnnels [1]. Generll, liner PA designs hve een limited their low energ efficienc. The increse in power consumption tht comes s result of the use of such liner PAs is n importnt issue for tter-powered moile devices. It would e clerl dvntgeous to mnge the trde-offs etween linerit nd energ efficienc, if the non-linerit of PAs cn e reduced vi eplicit signl processing techniques. One effective solution to compenste for the nonliner response of the PAs is to distort the signls prior to rriving t the PA [2]. The cscde composed of this predistorter (PD) nd PA give liner chrcteristic to the output of the PA. For pre-distorting needs to hve mthemticl model tht cn epress the reltion etween the mplitude (AM)/phse (PM) of its input nd output signls. Pre-distortion cn e estlished emulting the inversion of the chrcteristic function. A PD cn e implemented s n nlog or digitl circuit. The nlog PD is designed with pssive elements [3, 4] nd is simpler thn the digitl PD. However, it cnnot chnge its distortion chrcteristic nd suffers from ging s well s from temperture drift. On the other hnd, digitl PD (DPD) hs fleiilit in coping with environmentl chnges nd the chrcteristics of the pssive elements [1, 5]. While nlog PDs re sttionr, dptive DPDs cn e used to djust the LUT (Look-Up Tle) elements or polnomil coefficients tht determine the specific pre-distortion chrcteristics s the signl chnges. A DPD cn e re-configured so s to conform to the vrious communictions stndrds. The polnomil-tpe DPD [6-8] hs een implemented using nlog or digitl components. Direct

2 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.14, NO.6, DECEMBER, implementtion of higher order polnomils to compenste for the strong non-linerit of the PAs requires incresing computtionl compleit with comprtivel lrge mthemticl units [1]. Piecewise liner pproimtion [9] enles the ppliction of such higher order polnomils, ut degrdes the noise floor of the pre-distortion. In simpler pproch, DPD cn e esil implemented vi LUTs [10-13]. The LUT stores the pre-distorted AM/AM nd AM/PM dt of the PA tht re mpped to the corresponding inputs. When hundreds of smples or more re stored, dditionl sttic memor locks or register files re required, incresing the numer of trnsistors needed considerl. This pper introduces new VLSI design for implementing pre-distortion polnomils in DPD. It emplos full pipelined processing elements including Coordinte Rottion Digitl Computer (CORDIC) processor to cover domin conversion etween AM/PM nd in-phse nd qudrture (IQ) components. The CORDIC processor is used in clculting pre-distortion functions. Support for higher-order polnomil clcultions cn e chieved with its regulr structure. In Section 3, we show tht the implemented integrted circuit (IC) is more effective thn stnd-lone highperformnce digitl signl processor (DSP) solution. II. H/W DESIGN FOR DIGITAL PRE- DISTORTION DPD is tpicll used in feed-ck structure tht cn e dptivel djusted to reduce the errors etween the input nd the output of the PA. Fig. 1() shows the lock digrm for send DPD, IQ modultion, nd PA. Through the use of the inverse chrcteristics of nonlinerit of PA, the DPD distorts the IQ components of the signl prior to the IQ modultion nd PA. The predistortion errors cn e successivel converged to ero comprison to the PA output which is fed ck to the I I' Q DPD Q' DAC nd Modultor PA Re-configurtion Adpttion Procedure De- Modultor nd C Attenutor () Adptive pre-distortion flow to compenste for the non-linerit of the PA [16] DSP/ Appliction- Specific Processor Memor Su Sstem DPD C/DAC Eternl I/Fs () Implementtion of the pre-distortion from sstem-on--chip perspective Fig. 1. A pre-distortion rchitecture with DPD in communictions sstem.

3 720 JONG KANG PARK et l : A VLSI DESIGN FOR DIGITAL PRE-DISTORTION WITH PIPELINED CORDIC PROCESSORS input of the DPD. This itertive dption procedure might e fleile nd cn vr ccording to the communiction stndrds nd relevnt sstem requirements. Therefore, hrdwre (HW) nd softwre (SW) co-design would e desirle choice for such sstems, similr to tht of Refs The clcultion for the PD is performed sophisticted H/W lock, nd the DPD is dptivel configured nd mnged the SW code on the DSP s shown in Fig. 1(). In this pper, we focus on the efficient design of the clcultion units for the DPD, using the results of our previous stud [20]. 1. Proposed Technique for Implementing Pre-distortion The lock digrm for the proposed pre-distortion lock is shown in Fig. 2. I/Q-chnnel digitl signl from the nlog-to-digitl converter (C) goes to the input of the DPD. This discrete dt is then processed ech lock in the following order: pre-processor, multipleer (MUX), CORDIC processor in vectoring mode, demultipleer (DEMUX), PD, MUX, CORDIC processor in rottion mode, nd post-processor. The internl pipeline of the CORDIC processor in Fig. 2 performs two modes of opertions simultneousl. The rc-tngent nd squre root functions in vectoring mode eecutes AM-to-PM conversion nd the rottion mode of opertion in CORDIC processor converts PM signls to the AM domin its trigonometric functions. The detils for ech lock re descried s follows: The pre-processor djusts the fied-point formt of the eternl dt conforming to the inner dt tht is used in the CORDIC nd PD locks. Conversel, the postprocessor chnges the internl fied-point dt ccording to the output of the DPD. The MUX psses the dt to the first unit of the CORDIC processor nd controls its opertionl mode, whether the dt comes from the pre-processor or the PD lock. If it is from the pre-processor, MUX gives the dt to the CORDIC lock for the vectoring mode. Otherwise the lock would work in the rottion mode. DEMUX delivers the pre-distorted dt to the post-processor or the non-pre-distorted dt to the PD lock. The CORDIC processor performs the conversion etween the I/Q dt nd the AM/PM signl. It cn e lso used to implement the PD function, ut the eperimentl chip design hs een done using sophisticted clcultion lock. The CORDIC lgorithm nd its pipelined rchitecture re eplined in Section 2.3. The PD lock eecutes the pre-distortion of the AM/PM signl from the CORDIC processor. This will lso e further eplined in Section Fied-point Design for DPD When performing the rithmetic opertions in the DPD, the inr scling in fied-point formt where the integer clcultion is done with significnt numers is pplied to the results of the opertion. In this perspective, Fig. 3 shows the dt flow nd the relevnt dt formt Fig. 2. Block digrm of the DPD.

4 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.14, NO.6, DECEMBER, IQ {1,2,13} CORDIC (Vectoring) AM/PM {1,1,14} PD AM/PM {1,1,14} CORDIC (Rottion) IQ {1,2,13} Preprocessing Postprocessing IQ 14-it f i {1,1,14} m {1,4,11} p m {1,4,11} f i {1,1,14} IQ 14-it Fig. 3. Dt flow nd fied-point design for the DPD. used in the proposed DPD. The inputs of the DPD, which re the 14-it C output dt for the I/Q components, re epnded nd formtted to 16-it fied-point dt in the pre-processor. This formt consists of one sign it, two integer its, nd 13 frction its from the MSB to the LSB, nd the formt is mrked s {1, 2, 13}. The dt fter the pre-process is of {1, 2, 13}, nd the coefficients of the polnomil of the PD re used s {1, 4, 11} with scling fctor, to e further eplined in Section 2.4, in the form of {1, 1, 14}. The dt tht is reformtted the pre-processor is converted to the AM/PM domin fter ppling the vectoring mode process of the CORDIC lgorithm, nd it is then distorted the PD process. The dt is then converted to I/Q form the CORDIC rottion mode process nd is finll chnged to 14-it digitl-to-nlog converter (DAC) input formt the post-processor. The PA's input signl is then generted the DAC. 3. Signl Domin Conversion CORDIC Processor CORDIC is simple nd efficient lgorithm tht clcultes hperolic, trigonometric, nd even liner functions [14]. Its pipelined design onl requires dders, sutrctors, nd smll LUTs to support the necessr functions. The generlied i-th CORDIC itertions re defined s follows, - i+ 1 = i - i m di 2 i - i+ 1 = i + i di 2 i (1) i+ 1 = i - di f ( i). Assume tht X, Y, nd Z re the finl results fter the CORDIC itertions where d i, f(i), nd μ determine the modes of opertion, circulr/liner/hperolic nd rottion/vector modes. The itertion strts with initil vlues, 0, 0 nd 0 nd it ends with the finl vlues X, Y, Z, respectivel. Eq. (2) shows the results of the circulr rottion mode for the CORDIC lgorithm where K denotes constnt vlue. X = K( 0 cos 0-0 sin 0) Y = K( 0 cos 0-0 sin 0) (2) Z = 0 Eq. (3) shows the results of the circulr vectoring mode for the CORDIC lgorithm. 2 2 X = K ( 0-0 ) Y = 0 (3) - 1 Z = 0 + tn ( 0 / 0 ) In the circulr vectoring mode, s i gets closer to 0, ech i nd i converge to 2 2 K ( 0-0 ) nd tn ( 0 / 0 ), respectivel. The constnt K cn e eliminted multipling with the inverse of K fter the CORDIC itertions. In order to clculte the AM nd PM components of the signls in the proposed DPD, 0 nd 0 from Eq. (3) sustitute the I nd Q signls, respectivel, where 0 is initilied to 0. On the other hnd, in the rottion mode, if 0 nd 0 re initilied to the AM nd PM components with 0 =0, we cn otin the I component on X nd the Q component on Y using Eq. (2). Fig. 4 shows the dul-mode pipeline processing units of the CORDIC processor nd the corresponding clock-clock opertions proposed in our work. Both pre- nd

5 722 JONG KANG PARK et l : A VLSI DESIGN FOR DIGITAL PRE-DISTORTION WITH PIPELINED CORDIC PROCESSORS PU PU Vectoring mode Rottion mode 3rd 4th 15th 22th 23th 33th Fig. 4. Pipelined opertions nd clock ltenc in the dul-mode CORDIC processor. post-processing for the PD re ccomplished the shred CORDIC processor which consists of 13 unit stges where the design is nerl identicl to tht of tpicl pipeline rchitecture [15]. Ech unit cn work under one of two opertionl modes s result of the mode control signl. As the DPD works with the successive input dt, the MUX sends the dt to e converted to the I/Q or the AM/PM domin lterntel during ech clock ccle to the first stge of the CORDIC pipeline. At the third clock ccle, PU 0 otins the first I/Q component to e converted, s shown in the topmost pipeline stges of Fig. 4. At the fourth clock ccle, the output dt of PU 0 moves to PU 1 nd is still eing converted using the vectoring mode. This conversion is finished t the 15th clock ccle, nd then the corresponding AM/PM dt cn e fed into the PD lock. After 7 clock ccles pss, the first PD output cn enter PU 0 with the rottion mode. On the net clock, further I/Q dt to e converted to AM/PM enter the first stge in the vectoring mode. Since the PD lock produces distorted AM/PM signls tht should e converted to I/Q signl ever two clock ccles, the PU 0 opertes with vectoring nd rottion modes turns. Finll, t the 33rd clock ccle, the conversion of the first output dt would e finished the completion of 13 itertions. 4. The PD lock The inverse function of the PA non-linerit cn e defined s the m-th order the polnomil s follows, m ( m) n PD = n (5) n= 1 m P ( m) n DPD = p n A D + P D (6) n= 1 In Eqs. (5) nd (6), A D nd P D denote the AM nd PM of the originl signl to e mplified the PA. A DPD nd P DPD represent the pre-distorted AM nd PM components tht compenste the non-linerit of the PA. n nd p n represent the coefficients of the n-th term. Eq. (5) cn e re-constructed using Horner s recurrence formultion s

6 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.14, NO.6, DECEMBER, follows, (1) PD = m + m-1 (2) (1) PD = PD + m-2 M ( m-1) ( m-2) PD = PD + 1 ( m) ( m-1) PD = PD + 0 Eq. (6) cn e lso rewritten in similr w, (1) PDPD = pm + pm-1 (2) (1) PDPD = PDPD + pm-2 M ( m-1) ( m-2) PDPD = PDPD + p1 ( m) ( m-1) PDPD = PDPD + p0 (7) (8) Sometimes the PA's output cn e found to e smller thn the input wtching for the chrcteristic of nonlinerit. In this cse, the inverse function pplied to the DPD would hve lrger vlues thn the originl ones. Generll, the output rnge of the C covers the entire rnge of the DPD input with high resolution nd high ccurc. However, such inverse functions eceed the output rnge. Then, criticl errors cn occur. The scling fctor is used to prevent these over-rnged errors. For the inverse function to e pplied, we clculte the lrgest vlues of the output, nd we find the scling fctor tht mkes the output remin within the rnge of the DAC. The proposed DPD receives the pre-clculted scling fctor, nd djusts its output to e within the rnge multipling it with the determined vlue fter the PD opertion. III. EXPERIMENTS where 0 nd p 0 re initilied to 0 nd P D respectivel. As result of Eqs. (7) nd (8), PD cn e implemented m pipelined units tht clculte the form + s shown in Fig. 5. PD lso cn e implemented using the liner vectoring mode of the eisting CORDIC processor. Ech pipeline stge of the CORDIC is shown in Section 2.3, nd it cn e re-used to clculte Eqs. (7) nd (8). However, we implemented PD lock in our VLSI design tht will e shown in Section 3, emploed dders nd multipliers with pipeline registers. In this section, we present the results of the eperiments for the vlidtion of our proposed DPD. We otined the inverse function of the PA chrcteristic the 5th-order polnomil, nd the test dt re lso tken nling one of the rel PAs. The C nd DAC hve 20 MPSP output rte with 14-it resolution. The estimted function is defined s follows, PD = PDPD = PD A D A DPD APD 1 m m-1 m-2 APD 2 APD 1 m-3 m-n APD m-2 APD m A D P DPD PPD 1 p m p m-1 p m-2 PPD 2 PPD p 1 m-3 p m-n PPD m-2 p 1 PPD m-1 P D Fig. 5. A pipelined rchitecture for the PD lock.

7 724 JONG KANG PARK et l : A VLSI DESIGN FOR DIGITAL PRE-DISTORTION WITH PIPELINED CORDIC PROCESSORS () Fit plots for the AM-AM pre-distortion (< 2% error) Fig. 7. PSD plot of the PA output with/without the proposed DPD. Tle 1. Fied point design errors in the proposed DPD Output Components Error Amplitude (10-4 ) Avg. M. I Q () Fit plots for the AM-PM pre-distortion (< 0.04% error) Fig. 6. Fitting results using polnomil-sed model. where the mimum vlue of A DPD is Thus, the scling fctor ws tken s from the inversion of the mimum vlue. Fig. 6 depicts the comprtive plots for the trget chrcteristic dt nd the estimted models ove. The corresponding percentge errors re less thn 2% nd 0.04% for the AM-AM nd AM-PM predistortion, respectivel. Tle 1 summries the fied-point error of the proposed DPD. The errors re clculted compring the computtion results of the fied point design to the simultion vectors representing the idel floting numers. The input rnge of the I/Q-component is from to 0.5 nd the corresponding rnge of the output mplitude is etween 0 nd1/ 2 ( 0.707). As result, the errors in Tle 1 re smll enough to e considered negligile. We evluted the compensted linerit of the PA with the proposed DPD. Fig. 7 shows the power spectrum of the PA output. The lue line represents the originl output signl of PA where the spectrum shows the distorted chrcteristics due to the non-linerit of the PA. The red line represents the result of the PA output using the pre-distorted DPD output. As result of the nonlinerit of the PA, the PA output without the DPD (lue line) hs spectrl spreding with lrge side loes djcent to the centrl frequenc. The pre-distorted signl s result of the proposed design suppresses those outnd components of PA [20]. We designed our proposed DPD on the register trnsfer level (RTL) using Verilog HDL. An IC ws fricted for the DPD using stndrd CMOS 0.35 μm cell lirr, s depicted in Fig. 8. The snthesied result of the logic show the totl cell re to e estimted to hve 43,000 gtes, nd the trget clock speed ws of 40 MH. The implementtion results re summried in detil in Tle 2. Using chip testing equipment, oth functionl nd timing verifiction of the DPD IC were performed compring its outputs to the postsimultion results. We tested the implementtion vring the clock period from 15 ns to 35 ns, with 1 ns intervl. We lso verified the opertion correctness chnging the operting voltge from 2.2 V to 4.0 V. Ech condition ws tested for 30,000 input dt sets. Consequentl, we successfull vlidted the fricted DPD with MH clock speed from 2.7 V to 4.0 V suppl.

8 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.14, NO.6, DECEMBER, Fig. 8. Microphotogrph for the fricted DPD. Tle 2. VLSI implementtion results for the proposed design Technolog 0.35 μm CMOS 1-pol, 4-metl Operting clock freq./voltge 40 MH / 3.3V Gte sie Core sie Mimum output dt rte Power consumption (Active) PD 29,272 CORDIC 12,594 others 673 Totl 42,539 2,349 μm 1,348 μm 20 MSPS 62.5 mw Tle 3. Comprison results with the DSP implementtion result Eecution Time [μs] Proposed Pre/Post processor 0.2 < 0.1 I/Q AM/PM conversion PD Initil ltenc 3.5 Pipeline ltenc Tle 3 shows comprison of the results for the proposed HW design t 40 MH clock rte with the SW implementtion in commercil high performnce, fied-point DSP (TI TMS320C6415) where the operting clock frequenc ws of 780MH. Ech vrile for the SW code ws lso designed using fied-point level so tht we could sufficientl utilie the computing cpcit provided the trget DSP rchitecture. In our design, the numer of internl pipeline stges is more thn 30, so the initil ltenc for the first output of the DPD would e 3.5 μs. However, successive output cn e generted ever two clock ccles nd therefore, the miniml pipeline ltenc cn e of 100 ns. Conversel, the eecution time of the identicl SW functions on the DSP is more thn 5 μs, in spite of the trget operting clock frequenc rnging in the hundreds of MH. We cn see tht the min computtion components for the DPD cn e regulrl structured the pipelined VLSI design which is more effective thn the SW solution running on the instruction set rchitecture. To the est of our knowledge, there re no pulicied results for DPD logic design sed on stndrd cells tht re comprle to our stud. Insted, we use the eisting FPGA (Field Progrmmle Gte Arr) implementtion results for DPDs. Tle 4 summries the severl eperimentl results on Xilin FPGA devices. One of trget the designs to e compred with is the direct form polnomil DPD [21-23] nd the other tpe is the LUTsed distorter [22]. As shown in Tle 4, our design ws configured ll the sme trget FPGA devices tht were lred pplied to the eisting designs. For the comprison with the prtil result of [22], there re no ect prt nmes of the trget FPGA device specified in [22], ecept for the fmil nme s Virte-6. We chose the one of Virte-6 devices for these cses. For specific DPD design, ech column shows the djcent chnnel power rtio, numer of logic slice cells including flip-flops, specilied rithmetic unit cells (DSP48) including multipliers nd memor locks occupied in the trget FPGA. Compred to the eisting studies, our design hs the low hrdwre compleit on digitl logic circuits nd memor locks where its spectrl regrowth is well suppressed. IV. CONCLUSION This pper presents VLSI design for polnomil DPD using CORDIC processor. The CORDIC processor clcultes trigonometric function, converting n I/Q signl to AM/PM components nd vice vers. We implement the CORDIC processor to support oth two modes of opertion, vectoring nd rottion. Ech pipelined unit chnges its mode of opertion ever clock ccle. Including the PD lock, the proposed DPD is full pipelined design supporting high rte predistortion. B djusting onl the coefficients of the polnomil, it conforms to environmentl chnge. The prototpe IC ws successfull fricted nd vlidted on 0.35 μm CMOS technolog.

9 726 JONG KANG PARK et l : A VLSI DESIGN FOR DIGITAL PRE-DISTORTION WITH PIPELINED CORDIC PROCESSORS Tle 4. Hrdwre compleit comprison with other FPGA implementtion Design Adjcent chnnel power rtio [dbc] FPGA Logic sie [slices] DSP48 [slices] Block RAMs polnomil [21] XC4VSX polnomil [22] -60 Virte polnomil [23] -70 XC2VP50FF * Not used LUT [22] -60 Virte This work -60 XC4VSX Not used XC2VP50FF * Not used Virte-6 (XC6VCX75T) * indicting the numer of multipliers used in Virte-2 device (XC2VP50FF) Not used ACKNOWLEDGEMENTS This work ws supported IDEC (Integrted circuit Design Eduction Center) through the MPW (Multi- Project Wfer) Progrm. REFERENCES [1] I. Teikri, Digitl Pre-distortion Linerition Methods For RF Power Amplifiers, Disserttion, Helsinki Univ. of Tech., [2] J. K. Cvers, Amplifier Linerition Using Digitl Pre-distorter with Fst Adpttion nd Low Memor Requirements, IEEE Trns. On Vehiculr Tech., Vol. 39, No. 4, pp , [3] J. Nmiki, An utomticll controlled predistorter for multilevel qudrture mplitude modultion, IEEE Trns Commun., vol. COM-3 1, pp , [4] D. Hilom, S. Stpleton nd J. Cvers, An dptive direct conversion trnsmitter, Proc. of IEEE Vehiculr Tech., [5] Y. Ngt, Liner mplifiction technique for digitl moile communictions, Proc. of IEEE Vehiculr Tech., pp , [6] G. Budoin nd P. Jrdin, Adptive polnomil pre-distortion for linerition of power mplifiers in wireless communictions nd WLAN, Proc. of EUROCON 2001 Int. Conf. on Trends in Comm., vol. 1, pp , [7] E. Westesson, L. Sundström, Low-Power Comple Polnomil Pre-distorter Circuit in CMOS for RF Power Amplifier Linerition, proc. of 27 th ESSCIRC, pp , [8] M. Ghderi, S. Kumr, D. E. Dodds, Fst dptive polnomil I nd Q pre-distorter with glol optimition, proc. of IEE Comm., Vol. 143, No. 2, pp.78-86, [9] P. Kenington, High-linerit RF mplifier design, Artech House, [10] K. J. Muhonenm, K. Kvehrd, Look-Up Tle Techniques for Adptive Digitl Pre-distortion: A Development nd Comprison, IEEE Trns. On Vehiculr Tech., Vol. 49, No. 5, pp , [11] W. Woo, E. Prk, K. U-en nd S. Kenn, Widend pre-distortion linerition sstem for RF power mplifiers using n envelope modultion technique, Proc. of Rdio nd Wireless Conf., pp , [12] J. Sills nd R. Sperilich, Adptive power mplifier linerition digitl pre-distortion using genetic lgorithms, Proc. of IEEE Rdio nd Wireless Conf., pp , [13] J. Lee, S. Jeon, J. Kim, nd Y-W. Suh, Adptive HPA Linerition Technique for Prcticl ATSC DTV Sstem, IEEE Trns. On Brodcsting, Vol. 59, No.2, pp , [14] B. Prhmi, Computer Arithmetic : Algorithms nd Hrdwre Designs, pp , Oford Universit Press, [15] Q. Zhengu, A.C. Ce, R.T. Jones, M.R. Stn nd L. Chrles, CORDIC implementtion with prmeterile ASIC/SoC flow, Proc. of IEEE SouthestCon, pp.13-16, [16] D.E. Aschcher, Digitl Pre-distortion of Microwve Power Amplifiers, Disserttion, Vienn Univ. of Tech., [17] H. Gndhi, A Fleile Volterr-Bsed Adptive Digitl Pre-Distortion Solution for Widend RF Power Amplifier Linerition, IEEE Long Islnd

10 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.14, NO.6, DECEMBER, Section, [18] Tes Instruments, GC5322 Widend Digitl Pre- Distortion Trnsmit IC Solution, TI dtsheet, [19] B. Ogul, J. Lnger, J. Noguer, nd K. Visses, Softwre-progrmmle digitl pre-distortion on the Znq SoC, IFIP/IEEE 21st Int l Conf. on VLSI-SoC, pp , [20] K. Kim, S. Shim, J.T. Kim nd J.T. Kim, Digitl Predistorter with Pipelined Architecture Using CORDIC Processors, World Acdem of Science, Eng., nd Tech., Vol.4, pp , [21] S. Surnjn nd A. Dinh, FPGA Implementtion of Power Amplifier Linerier for n ETSI-SDR OFDM Trnsmitter, ZTE Comm., No.3, pp.22-27, [22] L. Gun nd A. Zhu, Low-Cost FPGA Implementtion of Volterr Series-Bsed Digitl Predistorter for RF Power Amplifiers, IEEE Trns. on Microwve Theor nd Techniques, Vol.58, No.4, pp , [23] N. Lshkrin nd C. Dick, FPGA Implementtion of Digitl Predistortion Lineriers for Widend Power Amplifiers, Proc. of SDR, Jong Kng Prk received BS nd MS degrees in Electric, Electronics nd Computer Engineering in 2001, 2003 nd Ph.D. degree in Electric nd Electronics Engineering from Sungkunkwn Universit, Kore in From 2008 to 2013, he ws with Smsung Electronics s senior engineer. He is now reserch professor, school of Electronic nd Electricl Engineering, Sungkunkwn Universit. His current reserch interests include the digitl logic design, sensor ICs, emedded sstem nd soft error nlsis nd tolernce techniques for VLSI designs. Jun Young Moon received BS degree in electric engineering in 2013 from Sungkunkwn Universit, Kore. He is currentl working towrd the MS degree in the Deprtment of IT Convergence in Sungkunkwn Universit. His reserch interests include the digitl logic design nd emedded sstem pltforms. Kunghoon Kim received BS degree in electric nd electronics engineering in 2009 nd received MS degree in deprtment of moile sstem engineering in 2011 from Sungkunkwn Universit, Kore. From 2009, he joined Smsung Electronics s n engineer. His current reserch interests include the secured emedded sstem pltforms nd softwre solutions. Youngoo Yng (S'99-M'02) ws orn in Hmng, Kore, in He received the Ph.D. degree in electricl nd electronic engineering from the Pohng Universit of Science nd Technolog(Postech), Pohng, Kore, in From 2002 to 2005, he ws with Skworks Solutions Inc., Newur Prk, CA, where he designed power mplifiers for vrious cellulr hndsets. Since Mrch 2005, he hs een with the School of Informtion nd Communiction Engineering, Sungkunkwn Universit, Suwon, Kore, where he is currentl n ssocite professor. His reserch interests include power mplifier design, RF trnsmitters, RFIC design, integrted circuit design for RFID/USN sstems, nd modeling of high power mplifiers or devices. Jong Te Kim is Professor t the School of Electronic nd Electricl Engineering, Sungkunkwn Universit, where he hs een since He received the BS degree in electronics engineering from Sungkunkwn Universit in Kore in 1982 nd the MS nd PhD degrees in electricl nd computer engineering t the Universit of Cliforni, Irvine, in 1987 nd 1992, respectivel. From 1991 to 1993 he ws with the Aerospce Corportion in Elsegundo, Cliforni. He ws full-time lecturer t Chunuk Ntionl Universit in Kore from 1993 to His reserch interests include SoC design nd design methodolog, emedded sstems, nd multi-core processor rchitecture.