Design Techniques for Low Power High Bandwidth Upconversion in CMOS

Transcription

1 Design Techniques for Low Power High Bndwidth Upconversion in CMOS Crl De Rnter Ktholieke Universiteit Leuven Dept. Elektrotechniek, fd. ESAT-MICAS Ksteelprk Arenerg 10 B-3001 Leuven, Belgium Michiel Steyert ABSTRACT An upconvertor topology for low power, high ndwidth pplictions is presented. Using specific circuit techniques nd locl circuit-level optimiztion, the power consumption of the totl system comprising n on-chip LC-type VCO, polyphse network qudrture genertor, liner mixer lock nd n RF-current uffer, hs een minimized. A chip hs een designed nd mnufctured in 0.25µm CMOS technology. The VCO oscilltes etween 1.68 GHz nd 2 GHz. Driven y n externl LO, the trnsmitter opertes from 900 MHz up to 2 GHz. At 2 GHz, the upconvertor trnsmits -12 dbm into 50 Ω with linerity of more thn -35 dbc for se nd signls up to 33 MHz. Ctegories nd Suject Descriptors B.7.m [Integrted Circuits]: Miscellneous Anlog RF CMOS Design Generl Terms Design Keywords Low power, Anlog, Upconversion, Oscilltors, RF Design, CMOS 1. INTRODUCTION 1.1 Wireless Systems In the post-gsm er few new communiction stndrds for moile nd portle devices re witing for eing introduced into the usiness nd consumer mrkets. The recently Now working t RF Mgic, Sn Diego Permission to mke digitl or hrd copies of ll or prt of this work for personl or clssroom use is grnted without fee provided tht copies re not mde or distriuted for profit or commercil dvntge nd tht copies er this notice nd the full cittion on the first pge. To copy otherwise, to repulish, to post on servers or to redistriute to lists, requires prior specific permission nd/or fee. ISLPED 02, August 12-14, 2002, Monterey, Cliforni, USA Copyright 2002 ACM /02/ $5.00. dopted UMTS-stndrd, operting in the 2 GHz rnge is such cndidte to e selected for the implementtion of new moile services on devices like PDA s or cell phones. This stndrd implements dt rtes for moile terminls up to 384 kps over ndwidth of 5 MHz using CDMA [1]. For portle devices slptops, generlly higher dt trnsmission rtes re required. Stndrds s IEEE re eing developed, providing dt rte of 55 Mps over ndwidth of 15 MHz using 64 QAM modultion with Trellis coding [2]. This speed of wireless trnsmission is lso envisged y the Hiperln/2 [3] stndrd tht 0 dt rtes up to 54 Mps over chnnel MHz wide. Here OFDM is implemented using 52 suchnnels of which 48 re used s dt chnnels. According to [2], SNR of more thn 20 db is needed in the receiver to operte t BER of 10 5 or etter when receiving 64 QAM+TCM-modulted signl. The trnsmitter will need n SNR tht is even higher to ensure proper system opertion. The UMTS stndrd mentioned in the previous prgrph lso defines n indoor wireless trnsmission speed up to 2 Mps for non-moving (portle) devices, using the sme ndwidth of 5 MHz. As comprison: the chnnel ndwidth of GSM system is 200 khz, the needed SNR is out 9 db ([4]). Conclusion of this very rief overview is tht in the chip-sets tht re to provide high dt rtes, signl with high SNR nd ndwidth some order of mgnitudes lrger thn for firstgenertion moile terminls, must e delt with. 1.2 Previous rt A lot of effort hs een spent in the design in CMOS of complete trnsceiver systems for low dt rte, i.e. smll nd, moile systems. This resulted in some successful designs in oth reserch nd commercil environments [5, 6, 7]. Recent reserch hs shown the possile use of CMOS upconvertor tht comines low power consumption with sufficient power output t frequencies up to 2.4 GHz in system with dt rtes lredy n order of mgnitude higher thn those of first nd second genertion wireless devices [8]. 1.3 This pper In this pper, some circuit techniques re presented tht hve een used in n upconvertor implemented in 0.25µm CMOS technology. The focus lies on techniques tht enle the trnsmission of se nd signl with lrge nd- 237

2 Replic Bising width nd high SNR, without creting lrge increse in power consumption. In first section, design overview dels with the glol topology of the upconvertor, the used design methodology nd the RF-MOST model used for circuit simultions. Then, the uilding locks re reported in detil, strting with the LC-oscilltor. The following section hndles the polyphse network. Section 5 nd Section 6 del with the implementtion of the liner mixer lock nd of the output uffer, respectively. Section 7 discusses the mesurements. After tht, the conclusions re formulted. 2. DESIGN OVERVIEW 2.1 Glol Topology Fig. 1 shows the lock schemtic of the implemented upconvertor topology. The first lock is n LC-type VCO, tht delivers differentil signl to the polyphse network. By this network it is converted into qudrture LO signl. The input of the polyphse network is coupled cpcitively to the oscilltor nd the output is directly connected to the qudrture mixer lock. The se nd input of the mixer lock is differentil qudrture signl, pplied externlly. A high pss network cts s n RF/LF splitter t the output of the mixer lock to short ll low frequency components to ground while pssing ll RF signls to the RF current mplifier. A 50 Ω output mtch is implemented s series inductor nd prllel cpcitor using on-chip components. 2.2 Design Methodology The design methodology used is imed t minimiztion of the totl power consumption nd consists of glol design on lock-specifiction level nd locl optimiztion on circuit level for ech functionl lock or set of functionl locks. Together with the indiction of the specific circuit techniques used, this locl optimiztion will e discussed for ech prt seprtely. 2.3 RF-MOST modelling At the strt of the design, no RF-models for the MOStrnsistors were ville. Therefore, trnsistor sucircuit hs een constructed using the following pproch ([9]): From the ville BSIM3-models n intrinsic MOST model is derived y setting ll junction-res to zero; The junctions re dded s diodes in the RF-MOST sucircuit, resulting in higher ccurcy of the junction cpcitor vlues for low finger numers; Source, drin nd sustrte resistors re dded to the sucircuit; A lyout-relted coupling cpcitor etween source nd drin is dded; A physicl gte resistnce is dded. In simultions, the non-qusi-sttic effect hs een found to e negligile for the uilding locks nd frequencies used in this design. Therefore, it is not dded to the RF-MOST sucircuit. 3. LC-TYPE VCO 3.1 Topology nd Design The implemented topology for the VCO is shown in Fig. 2. Vis Cc3 c c Mp1 Cc1 Iis Vctrl + - Mn1 Cc2 R1 Cc2 R1 Mn1 Figure 2: VCO topology with cpcitively coupled gin cell trnsistors The LC-tnk of the oscilltor is constructed using n onchip symmetricl coil nd PN-junction diodes of which the cpcitnce vlue is controlled y voltge V Ctrl. The inductor hs centrl tp to which the pmost is current source Mp1 is connected. The 1/f noise of this current source is reduced y setting the chnnel length to 2µm insted of the miniml 0.25µm. To further restrin 1/f-noise of this trnsistor from entering the circuit, the centrl tp is decoupled y the lrge on-chip cpcitor Cc1. The gin cell consists of nmost pir Mn1, of which the gtes re coupled to the LC-tnk y cpcitors Cc2. These cpcitors effectively decouple the DC output level of the oscilltor from the DC ising voltge of the gin cell. Here, the gin cell ising is done y replic ising of the pmost current source Mp1 connected in series with nmost diode Mn1c hving the sme spect rtio s the gin cell trnsistors. The gte of ech gin cell trnsistor Mn1 is connected to the resulting replic is voltge using lrge resistor (R1) s depicted in Fig. 2. Cpcitor Cc3is low impednce to ground for the noise current of the two resistors. 3.2 Optimiztion The optimiztion of the VCO consists of two prts. First, glol optimiztion of the VCO hs een done using n inhouse tool [10]. Secondly, n optiml vlue for resistors R1 nd cpcitorcc3 of Fig. 2 hs een determined, minimizing the influence on the phse noise of the VCO. This optimiztion hs een performed sed on circuit simultions using proprietry phse noise simultor [11]. Since the DC level t the output of the oscilltor cn e chosen freely, n optiml vlue is pplied tht mximizes the output voltge swing. The result is tht no uffers re needed fter the VCO to drive the polyphse network. Since the role of these uffers is to provide low output impednce t RF frequencies, considerle mount of power cn now e sved. Moreover, setting the DC voltge to this optiml vlue simultneously mximizes the symmetry of the oscilltor signl. According to [12] this ensures low upconversion of common-mode 1/f noise (e.g. the 1/f noise current from Mp1). 238

3 VCO + - Polyphse Network Qudrture Mixer High Pss Network RF Current Amplifier Output Mtching 50 Ohm Lod Qudrture Bse Bnd Signl Figure 1: Glol upconvertor topology 4. POLYPHASE NETWORK A four stge polyphse network is used to generte qudrture LO signl for rod rnge of input frequencies. In one version of the test chip, the polyphse network is driven y n externl differentil LO to hve lrger frequency rnge for testing. For this lock the power consumption is lowered s compred with trditionl topology y omitting the output uffers of the polyphse network nd directly coupling the polyphse network to the gtes of the mixer trnsistors. This direct coupling demnds n optimiztion over three uilding locks. The coupling cpcitor etween VCO nd polyphse network, the totl network resistnce nd the size of the mixer trnsistors ll influence t the sme time the output current of the mixer lock. The gol of the optimiztion is to mximize this output current, while minimizing the influence of the coupling on the phse noise of the VCO. The influence of the circuit elements specified ove re s follows: the polyphse network hs loding effect on the VCO, lowering its oscilltion mplitude nd deteriorting the phse noise; the polyphse network is loded y the input cpcitnce of the mixer lock, lowering the output mplitude of the polyphse network; the mplitude t the output of the polyphse network directly influences the output current of the mixer lock; lso the size of the mixer trnsistors directly influences the output current. It is cler tht the entnglement s descried ove necessittes locl optimiztion over set of functionl locks, eing VCO, polyphse network nd mixer lock. Fig. 3 shows the Imge Rtio (IR) of the output signl of the implemented polyphse network, with nd without simulted worst-cse mismtch effects for yield of 99.9%. 5. LINEAR MIXER BLOCK The used qudrture liner mixer topology, including the high pss network t its output, is depicted in Fig. 4. To otin good performnce of liner mixer lock, the following requirements must e fulfilled [13]: to void LO upconversion: zero DC voltge drop etween source nd drin of the mixer trnsistors; Imge Rejection [db] Simulted Imge Rejection of the Polyphse Network Without mismtch With mismtch Frequency [Hz] Figure 3: Simulted IRof the generted qudrture signl BBI+ BBQ+ Cc1 Cc1 Cc1c Cc1d LOI+ Mn1 LOQ+ Mn1 BBI- LOI- Mn1c BBQ- LOQ- Mn1d 2nd Order High Pss Network L1 Cc2 To RF Buffer Figure 4: Mixer topology with high pss network to void upconversion of the se nd frequency f BB to f LO ± 2.f BB : t the drin/source, low impednce to ground for DC up to 2.f BBmx,withf BBmx the mximl se nd frequency; to void degenertion of the RF output: low impednce for RF signls t the mixers output nd t the mixers input. These requirements hve een implemented s follows: the zero DC voltge drop is relized y simply pplying send input signl with zero DC vlue. (The mixer output is lso t DC ground due to the inductor of the high pss network.); 239

4 the high pss network relizes low impednce to ground for low frequencies nd low impednce to the input of the current uffer for high frequencies; the input stge of the current uffer relizes low impednce for RF signls t the mixers output; the on-chip cpcitors Cc1 in Fig. 4 relize low impednce to ground for RF signls t the mixers input. In this uilding lock, optimiztion is necessry for the on-chip inductor nd the coupling cpcitor of the high pss network. This optimiztion is to ensure tht the second requirement given ove is met nd lso tht low frequencies re restrined from entering the RF current uffer. A power efficient implementtion is relized y choosing pssive network to discriminte etween high nd low frequencies. An lterntive would e to use n ctive second order filter. Since the pss-nd strts round 900 MHz nd goes up to 2 GHz, this solution would consume n mount of power tht is comprle to the power usge of the input stge of the RF current uffer. Moreover, the pssive solution llows further enlrgement of the trnsmission ndwidth without power penlty y implementing higher order pssive network, leit t the cost of lrger re consumption. 6. TWO-STAGE CURRENT BUFFER 6.1 Topology The demnds for the current uffer re twofold: low input impednce for high frequencies to ensure proper mixer opertion; power-efficient current mplifiction with sufficient output power. The used uffer topology is depicted in Fig. 5. The input uffer hs n input dmittnce of gm Mn1 t frequencies ove the GBW of the feedck loop, nd of gm Mn1.G for frequencies elow the ndwidth of the loop, with G the DC gin of the feedck loop [13]. Since the GBW of the loop is certinly lower thn 2 GHz, the only wy to otin low input impednce is y ensuring high vlue for gm Mn1. This is ccomplished y sending sufficient current through the input stge of the uffer. The mplifiction stges of the current uffer re current mirrors with rtio M > 1. In the first stge, rtio of 2 is used, nd in the second stge rtio of 3. The first stge is coupled cpcitively to the second stge. Thus, pmost is current source Mp2 only hs to e sized to supply the is current for Mn3, lowering the prsitic cpcitnce of Mp2. The (lrge) mirror current of Mn2 is flowing through n on-chip inductive lod connected to Vdd low. The voltge of Vdd low cnemdelowerthn Vdd uffer, ecuse only single trnsistor hs to e set into sturtion. The power usge of this lock is minimized y optimiztion of the lod inductnce nd couple cpcitnce to otin mximum current trnsfer efficiency of one stge to nother. 6.2 Inductor Optimiztion The inductors used s lod for the mirror trnsistors Mn2 nd Mn3 in Fig. 5 re optimized to otin mximum current efficiency, in other words, minimum current loss. Therefore, they re designed towrds mximum prllel resistnce Rp for n inductnce vlue Ls tht mximizes the 3 db ndwidth of the uffer. The optiml inductor, hving mximum Rp for this vlue of Ls, is found using vrint of tool for VCO optimiztion [10]. This tool uses the inductor extrction progrm FstHenry ([14]) to clculte the vlues of the inductnce Ls nd the series resistnce Rs of coil with given geometry. An optimiztion lgorithm (ASA [15]) is used to find the optiml coil geometry y minimiztion of cost function. In this cse, the cost function CF is constructed s follows: Q coil =2πf 0 Ls/Rs Rp = Rs(1 + Q 2 coil) Cost Ls = Ls wnted Ls /Ls wnted CF = w 1 Cost Ls + w 2 (Rp 1 ) Here, f 0 is the mximum frequency of interest, Q coil is the qulity fctor of the inductor nd Ls wnted is the trget vlue for the inductnce. Weight fctor w 1 issettolow vlue if Ls Ls wnted nd to high vlue otherwise, while w 2 hs constnt medium vlue. By minimiztion of this cost function, n inductor geometry is found tht hs n inductnce vlue close to Ls wnted nd mximum vlue for Rp. In fct, y choosing the weight-vlues ppropritely, the optimizer is llowed to mke trde-off etween vlue for Ls differing slightly from the trget nd higher vlue for Rp. 7. CHIP PHOTO & MEASUREMENTS VCO PF network Figure 6: Chip photogrph A photo of the chip, processed in 0.25µm technology, is given in Fig. 6. The used technology provides MMC (metlmetl) cpcitors nd hs sustrte resistivity of 15 Ω.cm. The VCO is situted in the top left corner. Right from it, the four stge polyphse network cn e seen. The two coils with smll width nd five turns re the two lod inductors with high Rp from the current uffer. The two other coils re 240

5 Vdduffer Input Stge 2nd Stge Vdduffer Mp1 Vddlow Mp2 Vddlow Vcscn Mn1 L1 Ccouple L2 50 Ohm Mtch RF in Lmtch RF out Mn2 Mn3 Cmtch Figure 5: Two-stge RF uffer with low impednce input stge the inductor of the high pss network nd of the mtching network. The chip mesures 1.8x2.3 mm 2 Fig. 7 shows the tuning chrcteristic of the on-chip VCO, s mesured on wire-onded smple. The oscilltor oper Tuning rnge of oscilltor 20 Frequency [GHz] Output Power HD2 [dbc] HD3 [dbc] Pout [dbm] Vctrl [V] Figure 7: Tuning rnge of the on-chip VCO tes for vrctor control voltges from 2 Vdown to 0.15 V, nd hs n oscilltion frequency vrying from 1.68 GHz up to 2 GHz, while using 20 mw from 2 Vpower supply. The full set of chrcteristics of the VCO is depicted in Tle 1. Tle 1: Mesured VCO Specifictions Phse 1 MHz for f osc =2GHz -128 dbc Vdd 2V Tuning Rnge 17% Center Frequency 1.84 GHz Power Usge 20 mw To demonstrte the linerity of the upconvertor nd its usility for high ndwidth pplictions, mesurements hve een performed on flip-chip onded smple, driven y n externl oscilltor. For se nd frequencies f BB up to 33 MHz nd n LO frequency f LO of 2 GHz, the hrmonic components t f LO ± 2.f BB nd f LO ± 3.f BB re represented reltive to the output power s HD2 respectively HD3 in Fig. 8. Similr results re otined t LO frequencies of 900 MHz nd 1.5 GHz. Also shown in this plot is the mesured output power. For se nd frequencies up to 16.7 MHz, the output power is lrger thn -12 dbm nd up to 33 MHz the distortion is lower thn -35 dbc Bse Bnd frequency [MHz] Figure 8: Output linerity nd power vs. se nd input frequency A more common wy to express output linerity is the use of OIP2 nd OIP3. These cn e derived from IM2 resp. IM3, eing the second nd third order intermodultion products reltive to the power P Out in the fundmentl tone. By definition, OIP2(3) is the extrpolted vlue for P Out tht results in n IM2(3) of 0 db in plot of IM2(3) vs. P Out. Under conditions of low distortion (low power levels), following reltionships hold [16]: IM2=2HD2 (1) IM3=3HD3 (2) IM2 P Out (3) IM3 POut 2 (4) From (1) nd (2) it follows tht IM2 nd IM3 cn e clculted from HD2 nd HD3 y sutrcting 3.0 db resp. 4.8 db from the mesured distortion vlues. This method is used here s n pproximtion for two-tone mesurements. Equtions (3) nd (4) show tht one intermodultion (or distortion) mesurement theoreticlly suffices to otin vlue for OIP2 nd OIP3. However, for liner mixer (4) is not vlid for low vlues of the output power, ccording to [13]. Then, IM3 is proportionl to P Out. 241

6 Since mesurements of HD2 nd HD3 hve een performed t one vlue of P Out only, no decisive nswer cn e given to the question whether the mesured P Out should e regrded s high or low. Therefore, Tle 2 gives oth theoreticl vlues for OIP3. The norml one is indicted y OIP3 3 nd the one vlid for low power vlues in liner mixer is indicted y OIP3 2. The vlue tht would e derived from extrpolted mesurements will e somewhere in etween those vlues. Tle 2: Clculted vlues for f BB 2.5 MHz 16.7 MHz 33 MHz OIP2 26 dbm 29 dbm 22 dbm OIP dbm 2.2 dbm -0.3 dbm OIP dbm 21.2 dbm 18.2 dbm From the resoning ove, the representility of OIP3 s single numer for the linerity performnce of liner mixer seems questionle. Moreover, n upconvertor will never e used t or in the region of the output power levels indicted y OIP2 or OIP3. However, the intermodultion or distortion t the mximum output power level of the upconvertor relly is n importnt specifiction. Therefore, the mesured hrmonic distortion expressed s HD2 nd HD3 is used to quntify the performnce of this upconvertor. As lredy mentioned, vlues for IM2 resp. IM3 cn e clculted from these distortion mesurements using (1) nd (2), respectively. Tle 3: Mesured Specifictions of the Trnsmitter P BBin -3.5 dbm Vdd uffer 2V Vdd low 1.3 V Noise < -133 dbc/hz Power 25 mw F LO HD2 HD3 P Out 900 MHz -34 dbc -42 dbc -10 dbm 1.5 GHz -37 dbc -42 dbc -8.5 dbm 2GHz -44 dbc -38 dbc -12 dbm ll mesured for f BB =16.7 MHz In Tle 3 the mesured specifictions for the upconvertor re summrized, using the sme setup s ove. For n f BB of 16.7 MHz the distortion nd output power t LO frequencies of 900 MHz, 1.5 GHz nd 2 GHz re given. 8. CONCLUSION In this pper, n upconvertor topology hs een presented for which mesurements show tht se nd signls with ndwidth up to 33 MHz cn e upconverted to RF frequencies up to 2 GHz in stndrd CMOS technology. A pssive high pss network is used to llow the upconversion to e done with distortion low enough for higher order modultion schemes without the introduction of dditionl power drin. The power used y the upconvertor is lower thn 25 mw. The test chip is shown to keeps its functionlity t LO frequencies down to 900 MHz. An on-chip VCO is cpcitively coupled to polyphse network tht directly drives the mixer trnsistors. Thus, power-hungry uffering t RF-frequencies is voided. The power consumption of the VCO is 20 mw. Specific circuit techniques nd locl optimiztion t circuit level of the uilding locks hve een used during design to otin glol power minimiztion. 9. REFERENCES [1] E.T.S.I. Universl Moile Telecommunictions System; UE Rdio trnsmission nd Reception (FDD), ETSI TS [2] J. Kroguz. High-rte wireless personl re networks. IEEE Communictions Mgzine, 39(12):96 102, Dec [3] E.T.S.I. HIPERLAN Type 2, System Overview, ETSI TR [4] J. Crols nd M. Steyert. CMOS Wireless Trnsceiver Design. Kluwer Acdemic Pulishers, [5] A. Rofougrn, G. Chng, J. J. Rel, J. Y.-C. Chng, M. Rofougrn, nd P. J. C. et l. A single-chip 900 MHz spred-spectrum wireless trnsceiver in 1 µm CMOS-prt I.IEEE Journl of Solid-Stte Circuits, 33(4): , Apr [6] Silicon Lortories. Aero Si [7] A.Ajjikuttir,C.Leung,E.-S.Khoo,M.Choke,R.Singh, T.-H. Teo, et l. A fully-integrted CMOS RFIC for luetooth pplictions. In Digest of Tech. Ppers of Int. Solid-Stte Circuit Conference, pges , Sn Frncisco, Fe [8] A. Zolfghri, A. Chn, nd B. Rzvi. A 2.4 GHz 34 mw CMOS trnsceiver for frequency-hopping nd direct-sequence pplictions. In Digest of Tech. Ppers of Int. Solid-Stte Circuit Conference, pges , Sn Frncisco, Fe [9] C. Enz nd Y. Cheng. MOS Trnsistor Modelling Issues for RF Circuit Design in Anlog Circuit Design. Kluwer Acdemic Pulishers, [10] C. De Rnter, B. De Muer, G. Vn der Pls, P. Vncorenlnd, M. Steyert, G. Gielen, nd W. Snsen. CYCLONE: Automted design nd lyout of RF LC-oscilltors. In Proceedings IEEE Design Automtion Conference, pges 11 14, Los Angeles, June [11] B. D. Smedt nd G. Gielen. Accurte simultion of phse noise in oscilltors. In Proceedings Europen Solid-Stte Circuits Conference, pges , Southmpton, UK, Sept [12] A. Hjimiri nd T. H. Lee. A generl theory of phse noise in electricl oscilltors. IEEE Journl of Solid-Stte Circuits, 33(2): , Fe [13] M. Borremns nd M. Steyert. A 2 V, low distortion, 1 GHz CMOS up-conversion mixer. IEEE Journl of Solid-Stte Circuits, 33(3): , Mr [14] M. Kmon, L. M. Silveir, et l. FstHenry USER S GUIDE: version 3.0; ftp://rle-vlsi.mit.edu/pu/fsthenry. Msschusetts Institute of Technology, [15] L. Inger. Adptive Simulted Anneling (ASA); Cltech Alumni Assocition, [16] J. Jnssens. Deep sumicron CMOS cellulr receiver front-ends. PhD Thesis, Ktholieke Universiteit Leuven,