Mixed CMOS PTL Adders

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1 Anis do XXVI Congresso d SBC WCOMPA l I Workshop de Computção e Aplicções de julho de 2006 Cmpo Grnde, MS Mixed CMOS PTL Adders Déor Mott, Reginldo d N. Tvres Engenhri em Sistems Digitis Universidde Estdul do Rio Grnde do Sul (UERGS) Guí, RS Brzil Astrct. This pper presents simple method to design mixed CMOS PTL dders. The ide is to comine conventionl sttic CMOS gtes with psstrnsistor logic (PTL). With this strtegy is possile to design dders with smller numer of trnsistors nd reduced current consumption when compred with CMOS version. 1. Introduction In this pper we present method to design full dders with reduced current consumption. The method is sed on comining conventionl CMOS sttic gtes with pss-trnsistors logic (PTL). Full dders nd rithmetic circuits re frequently used s prt of opertive units nd processors. Becuse of rithmetic opertions re intensively used, the design of n dder circuit with low current consumption is required. Low current consumption is n importnt key for deep-sumicron-designs (DSM). PTL is frequently used to improve the design of rithmetic nd logic circuits. Sometimes different PTL design techniques re employed in order to chieve high speed or lower power dissiption s shown in [Yno, Ymnk, et.l.,1990][ Suzuki, Ohkuo, et.l., 1993]. Some synthesis techniques tht comine conventionl sttic CMOS gtes nd pss-trnsistor gtes re lredy proposed such s [Yng nd Ciesielsky 1999][Ynin, Sptnekr nd Bmji, 1998]. Pss-trnsistors design is n interesting re of the digitl integrted circuits, nd severl synthesis techniques were developed such s [Yng nd Ciesielsky, 1999][Scholl nd Becker, 1999][Ynin, Sptnekr nd Bmji, 1998][Tvres nd Berkelr, 1999]. Pss-trnsistors cn e employed to design logic circuits with reduced numer of trnsistors when compred with conventionl sttic CMOS. It cn e verified for some logic functions such s multiplexer nd exclusive-or. When the numer of trnsistors is reduced, we cn decrese the numer of lyout elements nd prsitic cpcitnces. Severl prsitic cpcitnces re chrging nd dischrging during signl propgtion, nd some current is consumed. Therefore, PTL design cn e used to remove some trnsistors, nd, it my e importnt to reduce the current consumption. However, some electricl prolems must e ddressed. There re situtions in which the input signl of PTL gte is pssed to the output node, ut the output signl sometimes cn e degrded. For instnce, the 1 input logic vlue when trnsmitted through NMOS trnsistor cnnot chrge the output prsitic cpcitnce to level. The mximum voltge stored y the output cpcitnce is -Vth. Vth is the threshold voltge of the NMOS trnsistor. The sme hppens when PMOS trnsistor is eing considered. In this cse the 0 input logic vlue when trnsmitted is not totlly propgted, nd Vth voltge remins stored in the output cpcitnce. 34

2 In this pper we propose design technique le to reduce the current demnded y full dder circuit. The min ide is to design full dder circuit with CMOS nd PTL gtes. A complete full dder design description cn e found in [Rey, Chndrksn nd Nikolic 2003]. 2. Mixed CMOS nd PTL Gtes Becuse pss-trnsistor cn propgte logic signl with some electricl degrdtion, technique to regenerte eventul pss signls is necessry. The technique presented in this pper is simple. It consists of inserting pss-trnsistor gte etween two sttic CMOS gtes. There re two importnt points ehind this ide: first, n pproprite trnsistor sizing of the sttic CMOS gte should e used in order to gurntee the norml output swing voltge levels. Second, only single pss-trnsistor is inserted etween two CMOS sttic logic pth. Note tht chin of pss-trnsistors my slow down the signl propgtion, nd, therefore it is not ttrctive s n implementtion option for dder circuits where the crry signl my e propgted through long pth. 3. Full Adders An dder circuit cn e implemented with exclusive-or (XOR) gtes, nd crry propgtion circuit cn e implemented with AND, NAND, OR, NOR nd Inverter gtes. Figure 1. Full Adder logic circuit. The leftmost circuit is n ordinry Full Adder. The rightmost circuit is Full Adder implemented with 2-input gtes nd inverters. The ordinry full dder circuit is shown in figure 1. The circuit cn e decomposed on simple 2-input gtes. In this new decomposed circuit there re more opportunities to insert pss-trnsistor gtes. Exclusive-or gtes cn e implemented not only with conventionl sttic CMOS gtes, ut lso with pss-trnsistor logic. However, n exclusive-or gte when implemented with sttic CMOS hs significnt cost. The cost is normlly mesured in terms of trnsistors re or its dely. Also comintion of trnsistor re nd dely my e used to reflect the cost. An importnt point is tht gte must drive n output 35

3 cpcitnce under time constrint. Then lrger trnsistors re necessry to drive the output lod depending on the numer of trnsistors in series, the internl gte cpcitnces, nd the output lod. Unfortuntely, lrger trnsistors my increse re nd current consumption. An exclusive-or function cn e implemented y 2-input NAND logic circuit. A NAND gte hs importnt fetures to chieve some performnce. For exmple, NAND cn compute the output quickly. A NAND is fster thn NOR gte. A low fnout NAND cn e designed with minimum size for N nd P trnsistors. An equivlent logic expression sed on NAND opertions cn e completely generted through logic trnsformtions such s: = + =.. A sttic circuit implementtion of this expression cn e seen in figure 2. The 2-input XOR circuit sed on sttic CMOS NAND gtes hs cost of 16 trnsistors. Output Out Figure 2. A 2-input XOR circuit. The leftmost circuit is sttic CMOS version. The rightmost circuit is mixed XOR gte. A mixed CMOS PTL implementtion of XOR gte is simple. It strts with 2- input NAND pss-trnsistor gte. This gte cn e implemented y sic PMOS- NMOS pss-trnsistor structure. The rightmost circuit from figure 2 shows the psstrnsistor circuit structure. Note tht 4 pss-trnsistors re used, nd they replce 12 trnsistors used in the sttic circuit. The totl numer of trnsistors is reduced to 8, i.e., this circuit performs XOR logic function with hlf of trnsistors of the sttic version. The crry propgtion function cn e descried y the logic expression: + c + c. This expression is esily trnsformed in n equivlent expression such s:... c.. c. This lst expression is sed on NAND opertions. A CMOS sttic crry propgtion circuit cn e implemented directly. It is shown in figure 3. 36

4 Cout Figure 3. Sttic CMOS crry propgtion circuit. The mixed crry propgtion circuit is shown in figure 4. As done efore, sttic NAND gtes were replced y PMOS-NMOS pss-trnsistor structures. An input inverter is used to generte the complementry input. Note tht pss-trnsistor circuits re inserted etween sttic gtes. Unfortuntely, in the crry propgtion circuit the numer of trnsistors remins the sme for oth designs. Cout Figure 4. Mixed crry propgtion circuit. When we compre the numer of trnsistor we see tht the conventionl sttic CMOS full dder uses 54 trnsistors, nd the mixed version is implemented with 38 trnsistors. The reduction in terms of trnsistors is out 30%. 4. Experiments A 4-input full dder circuit with sttic CMOS gtes nd 4-input full dder circuit sed on mixed gtes were simulted with SPICE from Berkeley. All trnsistors hve the sme size of 1µm. All possile input vectors were used to perform the electricl 37

5 simultion. The technology employed in the simultion ws the 0.13µm from Berkeley, nd 1.5V s reference voltge. Figure 5 shows the grphicl current ehvior of the oth dder circuits. The green curve represents the current consumption of the sttic CMOS 4-input dder, nd the red curve represents the current consumption from the mixed 4-input dder. For ech it position minimum size inverter ws used s lod. The grphic shows close current curves, ut they re not equl. For this experiment the mixed dder current consumption is out 20% lower thn the conventionl sttic CMOS. When we increse the lod up to 5 times the mixed dder current consumption is out 10% lower. 4.1 Crry Propgtion Dely Figure 5. Current consumption sttic dder x mixed dder. Severl full dders were uilt with sizes of 4, 8, 12, 16, 20, 24, 28 e 32 inputs. SPICE simultions were done in order to check the crry propgtion dely. The dely ws mesured from the first crry-in it position to the lst crry-out it position. An pproprite input vector ws pplied in order to gurntee the propgtion of the crry signl. The figure 6 shows the delys for ech dder simulted. As one cn see, the mixed circuits hve lmost the sme dely when compred with the conventionl CMOS version. But, the crry dely of the mixed gtes increses when the numer of inputs increses significntly. Dely (ns) Crry- out Dely X Input its 3,9 3,6 3,3 3,0 2,7 2,4 2,1 1,8 1,5 1,2 0,9 0,6 0,3 0, Input Bits CMOS complementry Pss trnsistor logic Figure 6. Full Adder dely. 38

6 5. Conclusion This pper presented technique tht cn e useful in reducing re nd current consumption of dder circuits. Adders re logic circuits tht re used in severl pplictions, nd, therefore, design techniques le to improve some performnce re desired. This technique is le to reduce the trnsistor re in 30%, nd the reduction in terms of current consumption cn e etween 10% nd 20%. However, some dely penlty my occur for lrge dders. A possile solution is to replce the mixed crry propgtion circuit y the conventionl circuit since the numer of trnsistors is the sme, nd in this cse the trnsistor re re comprle. PMOS-NMOS pss-trnsistors cn generte signls with some electricl degrdtion. However, in the full dder design we considered this prolem. For exmple, ll PMOS pss-trnsistors re ttched to. In this cse only the NMOS trnsistor is responsile to propgte 1 nd 0 logic signls. It is very importnt ecuse the propgtion of poor signls is reduced considerly. References Scholl, C. nd Becker, B. On the Genertion of Multiplexer Circuits for Pss Trnsistor Logic. In Proc. Interntionl Workshop on Logic Synthesis, Rey, M. Jn, Chndrksn, A. nd Nikolic, B. Digitl Integrted Circuits, Second Edition. Edited y Prentice-Hll. Tvres, R. nd Berkelr, M. Reducing Switching Activity in Pss Trnsistor Circuits. In Proc. Interntionl Workshop on Logic Synthesis, Suzuki, M., Ohkuo, N., Shino, T., Ymnk, T., Shimizu, A., Sski, K. nd Nkgome, Y. A 1.5-ns 32- CMOS ALU in Doule Pss Trnsistor Logic. In IEEE Journl of Solid Stte Circuits, Vol.28, NO.11, Novemer Ynin, J., Sptnekr, S. nd Bmji, C. A Fst Glol Gte Collpsing Technique for High Performnce Designs using Sttic CMOS nd Pss Trnsistor Logic. In Proc. Interntionl Conference on Computer Design, Yng, C. nd Ciesielsky, M. Synthesis for Mixed CMOS/PTL Logic. In Proc. Interntionl Workshop on Logic Synthesis, Yno, K., Ymnk, T., Nishid, T., Sito, M., Shimohigshi, A. nd Shimizu, A. A 3.8-ns CMOS 16x16- Multiplier Using Complementry Pss-Trnsistor Logic. In IEEE Journl of Solid Stte Circuits, Vol.25, NO.2, April

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