We are IntechOpen, the world s leading publisher of Open Access books Built by scientists, for scientists. International authors and editors

Transcription

1 We re IntechOpen, the world s leding pulisher of Open Access ooks Built y scientists, for scientists 3,5 8,.7 M Open ccess ooks ville Interntionl uthors nd editors Downlods Our uthors re mong the 5 Countries delivered to TOP % most cited scientists.% Contriutors from top 5 universities Selection of our ooks indexed in the Book Cittion Index in We of Science Core Collection (BKCI) Interested in pulishing with us? Contct ook.deprtment@intechopen.com Numers displyed ove re sed on ltest dt collected. For more informtion visit

2 4 Design Methodology with System Genertor in Simulink of FHSS Trnsceiver on FPGA Sntigo T. Pérez, Crlos M. Trvieso, Jesús B. Alonso nd José L. Vásquez Signls nd Communictions Deprtment, University of Ls Plms de Grn Cnri Deprtment of Computer Science, University of Cost Ric Spin Cost Ric. Introduction This study ims to descrie design method for Field Progrmmle Gte Arry (FPGA) (Mxfield, 4) pplied, in prticulr, to the design of Frequency Hopping Spred Spectrum (FHSS) trnsceiver (Simon et l., 994). Simulink (MthWorks, ) is tool integrted in Mtl, which llows the design of systems using lock digrms in fst nd flexile wy. Xilinx is one of the most importnt FPGA mnufcturers nd provides System Genertor (Xilinx, ), it is design environment over Simulink for FPGA sed on the method descried. The design is sed on previous FHSS trnsceiver designed for indoor wireless opticl communictions mde with discrete components (Pérez et l., 3). One of the improvements in the proposed system is the physicl integrtion.. The physicl device Initilly, there were severl lterntives for the system hrdwre. In principle, n Appliction Specific Integrted Circuit (ASIC) cn e used (Mxfield, 4), ut to configure these devices must e sent to the mnufcturer, which increses development time nd mkes more expensive the prototype. This technology chieves good physicl performnces: low re, low power consumption nd miniml delys. At the other extreme Digitl Signl Processor (DSP) cn e used which re very chep (Mxfield, 4). The DSPs do not hve the est physicl performnces; normlly they occupy mximum re, hve high power consumption nd mximum dely. In fct, when the volume of clculus is high, esily they do not hve rel time response. This is ecuse the rchitecture is rigid, in oth dt nd opertions formts. In the middle re FPGA, which hve resonle cost for the design of prototypes; in generl n intermedite cost to the two previous cses. The FPGA hve significnt physicl enefits, without reching the performnces of ASIC. FPGAs hve enefits outweigh the

3 94 Applictions of MATLAB in Science nd Engineering DSP ecuse the FPGA finl rchitecture cn e configured in fully flexile wy, in oth dt nd opertions size. It must e emphsized tht FPGA re integrted circuits reprogrmmle y the designer nd cn e used for different projects, or in project during its different phses. The FPGAs re lso ville in the mrket on printed circuit ords, with power nd progrmming connectors, uxiliry memories nd input-output pins; this void to design nd construct the printed circuit ord, nd mkes it idel for prototyping design. 3. Design methodology A trnsceiver cn e designed using discrete electronic components. In generl, the overll design is not flexile nd highly dependent on technology nd ville devices, hs long design time, occupies lrge re, hs high power consumption nd high delys nd low mximum operting frequency. In generl, the trend is to integrte the design in digitl integrted circuit nd plce round the necessry externl components; this elimintes the previous inconveniences. It must e emphsized tht these designs cn e esily portle etween devices, even from different mnufcturers. This portility is possile ecuse the design cn e descried with stndrd hrdwre description lnguge (HDL). In digitl systems, when floting point rithmetic is used, the rnge nd precision cn e djusted with the numer of its of exponent nd mntiss, it is then possile to otin wide rnge nd high precision in this type of representtion. However, floting point opertions require mny hrdwre resources nd long time execution (Huck & DeHon, 8). On the other hnd, the fixed point rithmetic requires fewer hrdwre resources, ut the rnge nd precision cn e improved only y incresing the numer of its. If the numer of its is constnt, to increse the rnge cuses decrese in the precision. It is possile to use fixed point rithmetic in most pplictions when the rnge of signls is known or cn e determined y sttisticl methods. In fixed point rithmetic the 's complement representtion is used ecuse its rithmetic rules re simpler thn the 's complement representtion. Ordinrily the systems cn e designed using stndrd hrdwre description lnguge: VHDL (Very High Speed Integrted Circuit Hrdwre Description Lnguge) (Pedroni, 4) or Verilog (Plnitkr, 3). Mnul coded of complex systems using one of these lnguges is little flexile nd hs gret design time. To solve these prolems severl design progrms hve een developed. One of them is the System Genertor from Xilinx, which is instlled in Simulink. 3. System genertor When System Genertor is instlled some Blocksets (Fig. ) re included in Simulink of Mtl. Ech lock is configured fter opening its dilog window, this permits fst nd flexile designs. Bsiclly, System Genertor llows minimizing the time spent y the designer for the description nd simultion of the circuit. On the other hnd, the design is flexile; it is possile to chnge the design prmeters nd check quickly the effect on the performnces nd the rchitecture of the system. The functionl simultion is possile even efore the compiltion of the model designed. The compiltion genertes the files of the structurl description of the system in stndrd hrdwre description lnguge for the Integrted System Environment (ISE) for Xilinx FPGAs.

4 Design Methodology with System Genertor in Simulink of FHSS Trnsceiver on FPGA 95 Fig.. System Genertor Blocksets in Simulink The FPGA oundry in the Simulink model is defined y Gtewy In nd Gtewy locks. The Gtewy In lock converts the Simulink floting point input to fixed point formt, sturtion nd rounding modes cn e defined y the designer. The Gtewy lock converts the FPGA fixed point formt to Simulink doule numericl precision floting point formt. In the System Genertor the designer does not perceive the signls s its; insted, the its re grouped in signed or unsigned fixed point formt. The opertors force signls to chnge utomticlly to the pproprite formt in the outputs. A lock is not hrdwre circuit necessrily; it reltes with others locks to generte the pproprite hrdwre. The designer cn include locks descried in hrdwre description lnguge, finite stte mchine flow digrm, Mtl files, etc. The System Genertor simultions re it nd cycle ccurte, this mens results seen in simultion exctly mtch the results tht re seen in hrdwre. The Simulink signls re shown s floting point vlues, which mkes esier to interpret them. The System Genertor simultions re fster thn trditionl hrdwre description lnguge simultors, nd the results re esier for nlyzing. Otherwise, the VHDL nd Verilog code re not portle to other FPGA mnufcturers. The reson is tht System Genertor uses Xilinx primitives which tke dvntges of the device chrcteristics. System Genertor cn e used for lgorithm explortion or design prototyping, for estimting the hrdwre cost nd performnce of the design. Other possiility is using

5 96 Applictions of MATLAB in Science nd Engineering System Genertor for designing portion of ig system nd joining with the rest of the design. Finlly, System Genertor cn implement complete design in hrdwre description lnguge. Designs in System Genertor re discrete time systems; the signls nd locks generte utomticlly the smple rte. However, few locks set the smple rte implicitly or explicitly. System Genertor supports multirte circuits nd some locks cn e used for chnging the smple rte. Often n executle specifiction file is creted using the stndrd Simulink Blocksets (see Fig. ). The specifiction file cn e designed using floting point numericl precision nd not hrdwre detil. Once the functionlity nd sic dtflow hve een defined, System Genertor cn e used to specify the hrdwre implementtion detils for the Xilinx devices. System Genertor uses the Xilinx DSP Blockset from Simulink nd will utomticlly invoke Xilinx Core Genertor to generte highly optimized netlists for the uilding locks. System Genertor cn execute ll the downstrem implementtion tools to get itstrem file for progrmming the FPGA device. An optionl testench cn e creted using test vectors extrcted from the Simulink environment for using with Integrted System Environment simultors. Fig.. System Genertor design flow (downlod from Every system designed with System Genertor must contin System Genertor lock (Fig. 3); this lock specifies how simultion nd code genertor cn e used. Firstly, the type of compiltion in the System Genertor lock cn e specified to otin: HDL netlist, Bitstrem for progrmming, etc. Secondly, the FPGA type cn e chosen. The trget directory defines where the compiltion writes the files of Integrted System Environment project. The synthesis tool specifies which tool is chosen for synthesizing the circuit: Synplify, Synplify Pro or Xilinx Synthesis Tool (XST). In the hrdwre description lnguge the designer cn choose etween VHDL nd Verilog. Finlly, clock options defines the period of the clock, its input pin loction, the mode of multirte implementtion nd the Simulink system period, which is the gretest common divisor of the smple periods tht pper in the system. In the lock icon disply, the type of informtion to e displyed is specified.

6 Design Methodology with System Genertor in Simulink of FHSS Trnsceiver on FPGA 97 System Genertor Fig. 3. System Genertor lock nd its dilog window 3. Integrted system environment In Xilinx Integrted System Environment it is possile to compile the hrdwre description lnguge files, nd simulte the system ehviorl or timing nlysis. Also the occupncy rte, power consumption nd operting temperture of the FPGA re otined. Afterwrds the progrm file cn e generted for the chosen device; this file cn e downloded from the computer to the ord where the FPGA is included. Finlly, the performnce of the design system must e checked with electronic mesure equipment. When the designer clicks on Generte in dilog window of System Genertor lock, the structurl description files in hrdwre description lnguge re otined, nd project is creted for Integrted System Environment. Now it is possile to check the syntx of the hrdwre description lnguge files (Fig. 4). The first step in the compiltion process is synthesizing the system. The synthesis tool used is Xilinx Synthesis Tool, it is n ppliction tht synthesizes hrdwre description lnguge designs to crete Xilinx specific netlist files clled NGC (Ntive Generic Circuit) files. The NGC file is netlist tht contins oth logicl design dt nd constrints. The NGC file tkes the plce of oth Electronic Dt Interchnge Formt (EDIF) nd Netlist Constrints File (NCF) files. In synthesis options optimiztion gol for re or speed cn e fixed; y defult, this property is set to speed optimiztion. Similrly, optimiztion effort cn e estlished s norml or high effort; in the lst cse dditionl optimiztions re performed to get est result for the trget FPGA device. Synthesis report cn e nlyzed y the designer; moreover, the designer cn view Register Trnsfer Level (RTL) schemtic or technology schemtic. After synthesizing the system, the design is implemented in four stges: trnslte, mp, plce nd route. The trnsltion process merges ll the input netlists nd design constrint informtion nd outputs Xilinx Ntive Generic Dtse (NGD) file. Then the output NGD file cn e mpped to the trgeted FPGA device fmily. The mp process tkes the NGD file, runs design rule checker nd mps the logic design to Xilinx FPGA device. The result ppers

7 98 Applictions of MATLAB in Science nd Engineering in Ntive Circuit Design (NCD) file, which is used for plcing nd routing. The plce nd route process tkes NCD file nd produces new NCD file to e used y the progrmming file genertor. The genertor progrmming file process runs the Xilinx itstrem genertion progrm BitGen to produce it file for Xilinx device configurtion. Finlly, the configurtion trget device process uses the it file to configure the FPGA trget device. Behviorl simultions re possile in the design efore synthesis with the simulte ehviorl model process. This first pss simultion is typiclly performed to verify the Register Trnsfer Level or ehviorl code nd to confirm the designed function. Otherwise, fter the design is plced nd routed on the chip, timing simultions re possile. This process uses the post plce nd route simultion model nd Stndrd Dely Formt (SDF) file. The SDF file contins true timing dely informtion of the design. Fig. 4. Overview of design flow of Integrted System Environment (downlod from 4. The trnsceiver This chpter is sed on previous FHSS trnsceiver (Fig. 5) for wireless opticl communictions. The FHSS nd nlog synchroniztion signls were emitted y two seprted Light Emitting Diodes (LED) to void dding them with discrete nlog circuits. Binry dt Trnsmitter FHSS Receiver Demodulted dt Anlog synchroniztion signl Fig. 5. Block digrm with FHSS trnsceiver designed previously

8 Design Methodology with System Genertor in Simulink of FHSS Trnsceiver on FPGA 99 The core of the trnsmitter ws discrete Direct Digitl Synthesizer (DDS) AD985 from Anlog Devices (Anlog Devices, ). The discrete DDS (Fig. 6) is digitl system excepting the finl Digitl to Anlog Converter; its output signl is sinusoidl smpled signl t 8 MHz. The emitted FHSS signl ws smoothed y the MHz ndwidth of the opticl emitter. In the DDS used, the output frequency is fixed y the expression (), where f DDS_CLK is the frequency of the DDS clock (8 MHz), N is the numer of its of the tuning word (3 its) nd Word is the deciml vlue of 3 it frequency tuning word. f out =(Word f DDS_CLK )/ N () Fig. 6. Block digrm of discrete DDS AD985 from Anlog Devices (downlod from In the demodultor of the receiver, two similr discrete DDS were used s locl oscilltors. In the new design, the full trnsceiver with the previous methodology is descried. The modultor mtches with the trnsmitter designed previously, excepting the opticl emitters nd the output Digitl to Anlog Converter of the discrete DDS. In the sme wy, the two DDS in the demodultor were integrted in the FPGA. In the previous design, discrete nlog filters were used. In the new design, these filters were integrted in the FPGA s digitl filters. The new design methodology is improved y DDS lock nd filter design cpilities in System Genertor. The Fig. 7 shows the new FHSS trnsceiver. In Fig. 8, the dt in the trnsmitter nd the demodulted dt re shown. After the synchroniztion is reched in the receiver, the demodultion is executed perfectly. FHSS TRANSCEIVER System Genertor FHSS TRANSMITTER FHSS RECEIVER doule EXTERNAL _DATA FHSS _SYNCHRONIZATION Fix_7_5 RX_IN DEMODULATED_DATA doule Constnt FB doule DATA_CONTROL DATA Termintor doule Scope Constnt Fig. 7. Frequency Hopping Spred Spectrum trnsceiver

9 3 Applictions of MATLAB in Science nd Engineering ) x -5 ) x -5 Fig. 8. Dt signls in the trnsceiver: ) trnsmitted dt, ) demodulted dt If Port Dt Type is enled in Simulink, fter the system simultion the dt types re shown in every point of the design. It cn e: (oolen); doule, Simulink floting point formt; UFix_m_n, unsigned m its two s complement fixed point formt with n frctionl its; Fix_m_n, signed m its two s complement fixed point formt with n frctionl its. Otherwise, the signls cn e nlyzed in different wys using Simulink Sinks lockset. First, the Scope lock cn e used; this ws the method used for djusting the trnsceiver, it is quick ut not convenient for cpturing signls. Secondly, signls cn e cptured with the To Workspce lock, ut these signls re only stored temporrily in Mtl. Finlly, To File lock keeps the cptured signls in mt file permnently; for this reson To File lock ws used to cpture nd present simultions of this design. 5. The trnsmitter The lock digrm of the designed trnsmitter is drwn in Fig. 9. It is composed of n internl dt genertor, pseudorndom code genertor, nd two DDS, used to generte the FHSS nd synchroniztion signls. An externl clock of 8 MHz is needed for the system. In this trnsmitter it is possile to choose etween internl or externl inry dt. FHSS_TRANNSMITTER FB FB SINC _DATA_PN DATA_PN FB SINC_DATA_PN DATA_GENERATOR DATA_PN F_CHIP DATA 3 DATA doule DATA_CONTROL doule EXTERNAL _DATA In DATA_CONTROL In EXTERNAL _DATA sel d d Mux doule DATA UFix_5_ CODE_3_STATE UFix_4_ CODE_6_STATE UFix_5_ DATA_CODE_6_STATE S_3_BEFORE UFix LENGTH F_CHIP CODE_6 _STATE S_3_BEFORE CODE_3_STATE DATA_CODE _6 _STATE CODE _GENERATOR LENGTH Fix _9_9 DATA_DDS DATA_CODE_6_STATE DATA_DDS Fix _6_5 FHSS FHSS DDS_FHSS Fix _6_5 LENGTH SYNCHRONIZATION SYNCHRONIZATION FHSS_SYNCHRONIZATION Fix_7_5 Fix_7_5 + FHSS_SYNCHRONIZATION AddSu DDS_SYNCHRONIZATION Fig. 9. Block digrm of FHSS trnsmitter designed with System Genertor

10 Design Methodology with System Genertor in Simulink of FHSS Trnsceiver on FPGA 3 5. Pseudorndom dt genertor Appliction of the internl dt genertor (Fig. ) voids using n externl dt source; it ws designed using Liner Feedck Shift Register (LFSR) lock s pseudorndom genertor of 5 its long t 5 kiloits per second. A pulse in the pseudorndom dt genertor is formed ech time the sequence egins; this provides high qulity periodic signl to synchronize the oscilloscope. The LFSR lock is configured with the dilog windows (Fig. ). The clock, the dt synchroniztion pulse nd the pseudorndom dt re shown in Fig.. DATA_GENERATOR CEProe FB_i 5 Constnt UFix_4_ Constnt 36 = z - UFix_9_ lod UFix_9_ out din Counter UFix _8_ 8 Constnt 3 >= z - Reltionl FB SINC_DATA_PN dout UFix_4_ Slice [:] Reltionl 3 DATA_PN LFSR_DATA_GENERATOR Fig.. Internl pseudorndom dt genertor Fig.. Liner Feedck Shift Register dilog windows.8.6 ) x -5.8 ) x -5 c) x -5 Fig.. Pseudorndom dt genertor signls: ) clock t it rte, ) the dt synchroniztion pulse, c) the pseudorndom inry dt

11 3 Applictions of MATLAB in Science nd Engineering 5. Pseudorndom code genertor The pseudorndom code genertor nd its Simulink simultion signls re shown in Figures 3 nd 4. The code rte is clled chip frequency; its vlue is.5 Megchips per second. Consequently, three codes re generted y ech dt it. The code genertor is sed on Liner Feedck Shift Register of 3 sttes. In the pseudorndom code genertor, pulse is generted ech time the sequence egins. A five its word is otined with the four most significnt its of the pseudorndom code genertor nd the dt it s most significnt it. CODE_GENERATOR dout LFSR_CODE _GENERATOR DATA UFix _5_ CEProe F_CHIP _i Slice [:] UFix_4_ Constnt hi lo UFix_7_ Conct lod din out Counter 6 Constnt 3 UFix_5_ 5 Constnt UFix _7_ UFix _6_ UFix_5_ >= z - Reltionl = z - Reltionl F_CHIP CODE _3 _STATE 3 CODE _6 _STATE 4 DATA_CODE_6_STATE 5 S_3_BEFORE cst Convert UFix q Accumultor UFix 6 LENGTH Fig. 3. Pseudorndom code genertor ) x -5 ) x -5 c) x -5 d) e) x -5.5 f) x x -5 Fig. 4. Pseudorndom code genertor signls: ) chip frequency, ) pseudorndom code 5 its width, c) 4 most significnt its of pseudorndom code 5 its width, d) dt joined with 4 most significnt its, e) the stge previous to, f) squre signl which mrks the code length

12 Design Methodology with System Genertor in Simulink of FHSS Trnsceiver on FPGA Frequency hopping spred spectrum signl genertion For ech group of five its (signl d in Fig. 4) smpled sinusoidl signl is generted ccording to Tle. Code Frequency (MHz) Code Frequency (MHz) Tle. Trnsmitted frequencies for the FHSS signl In Fig. 5, the DDS generting the FHSS signl is shown. The DDS clock is the system clock (8 MHz). Therefore, pure sinusoidl signl with n externl filter cn e synthesized until it less thn 9 MHz. DDS_FHSS we UFix _5_ DATA_CODE_6_STATE x.853 UFix 6 Constnt Fix _9_9 + dt sine Fix _6_5 FHSS CMult Constnt UFix_6_6 AddSu DDS Compiler. DATA_DDS Fig. 5. Direct Digitl Synthesizer generting the FHSS signl The input dt for the Xilinx DDS lock is the synthesized frequency divided y the DDS clock. The eqution () shows the mening of this reltion. Consequently, the DDS lock

13 34 Applictions of MATLAB in Science nd Engineering fixes the numer of N its ccording to the rest of the DDS prmeters: spurious free dynmic rnge, resolution, implementtion mode, etc. dt=f out /f DDS_CLK =Word/ N () Fig. 6 shows the dilog windows of the DDS lock, where the designer cn fix its prmeters. This DDS cts like frequency modultor. Fig. 6. Direct Digitl Synthesizer lock dilog windows for FHSS signl The five its input signl is trnsformed to the formt of the input DDS lock. The lst opertion is n unsigned fixed point integer to unsigned fixed point deciml conversion. In Fig. 7, five chip times of FHSS signl re shown. Three frequencies re generted y ech dt it, therefore this is Fst Frequency Hopping Spred Spectrum modultion. 3 ) x ) x -5.5 c) x -5 Fig. 7. Signls in Direct Digitl Synthesizer generting the FHSS signl: ) five its DDS input, ) input for Xilinx DDS lock, c) FHSS signl 5.4 Synchroniztion signl genertion nd finl dder In the pseudorndom code genertor, squre signl is generted with 5% duty cycle (signl f in Fig. 4). This squre signl hs semi-period with the sme durtion s the pseudorndom code length. The squre signl is the DDS input (Fig. 8), it modultes in phse to 9 MHz crrier (Fig. 9). The phse modulted signl crries informtion out the

14 Design Methodology with System Genertor in Simulink of FHSS Trnsceiver on FPGA 35 eginning of the pseudorndom code; nd out its chip frequency, ecuse its crrier is multiple of.5 MHz. DDS_SYNCHRONIZATION we UFix LENGTH x.5 CMult UFix _7_6 Constnt 3 Fix _9_9 cst Convert dt sine DDS Compiler. Fix_6_5 SYNCHRONIZATION Fig. 8. Direct Digitl Synthesizer for synchroniztion genertion ) x x -5 ) x x -5 Fig. 9. Signls in Direct Digitl Synthesizer tht genertes the synchroniztion signl: ) squre input signl, ) synchroniztion signl The Fig. shows the dilog window of the DDS lock. This Direct Digitl Synthesizer cts like phse modultor. In oth Xilinx DDS locks, the ltency configurtion is fixed to for keeping the DDS delys to the minimum sme vlue, this prmeter specifies the dely s numer of clock cycles. Fig.. Direct Digitl Synthesizer lock dilog windows for synchroniztion signl

15 36 Applictions of MATLAB in Science nd Engineering Finlly, the FHSS nd the synchroniztion signls re dded with n AddSu lock, this new signl is the trnsmitter output (Fig. )..5 ) x -5.5 ) x -5 c) x -5 Fig.. Inputs nd output of finl dder: ) FHSS signl, ) synchroniztion signl, c) the ove signls dded together 6. The receiver The receiver lock digrm is shown in Fig.. The signl received from the trnsmitter enters in the splitting filter, FHSS nd synchroniztion signls cn e seprted ecuse they re multiplexed in frequency. The filtered synchroniztion signl is the input of the synchroniztion recovery, where the code is otined in the receiver. The code recovered synchronizes the locl oscilltors. Finlly, the locl oscilltors outputs nd the FHSS filtered re introduced to the doule rnch dt demodultor. Fix_7_5 RX_IN In Fix_7_5 RX_IN RX_FHSS DEMODULATED _DATA DEMODULATED _DATA SYNCHRONIZATION RECOVERY LOCAL OSCILLATORS SF_IN SYNCHRONIZATION _FILTERED Fix 7 SR_IN CODE_RECOVERED UFix_4_ CODE_IN F_ F_ Fix_6_5 Fix_6_5 F_ FHSS _IN DEMODULATED_DATA FHSS_FILTERED Fix_8_4 F_ DOUBLE BRANCH DEMODULATOR SPLITTING FILTERS z -75 Fix_8_4 DELAY Fig.. Block digrm of FHSS receiver designed with System Genertor 6. Splitting filters The splitting filters lock digrm nd signls re drwn in Fig. 3 nd 4 respectively. A Finite Impulse Response (FIR) high pss filter recovers the FHSS signl. It ws designed using the Filter Design nd Anlysis Tool (Fig. 5), the filter s coefficients re used y Xilinx FIR Compiler lock for eing synthesized. In the sme wy, nd pss filter is designed to otin the synchroniztion signl.

16 Design Methodology with System Genertor in Simulink of FHSS Trnsceiver on FPGA 37 SF_IN Fix_7_5 dout Fix_8_4 dout Fix 7 FHSS_FILTERED SYNCHRONIZATION _FILTERED din rfd din rfd Termintor Termintor 3 rdy Termintor FIR Compiler 4._FFHSS FDATool rdy Termintor 4 FIR Compiler 4._SYNCHRONIZATION FDATool SPLITTING FILTERS Coefficients _HPF Coefficients _BPF Fig. 3. Splitting filters lock digrm ) x -5 ) x -5.5 c) x -5 Fig. 4. Splitting filters signls: ) input, ) FHSS filtered, c) synchroniztion filtered Fig. 5. Filter Design nd Anlysis Tool dilog window

17 38 Applictions of MATLAB in Science nd Engineering 6. Synchroniztion recovery The input of this system is the synchroniztion filtered, in its output gets the most significnt four its of the pseudorndom code (Fig. 6). It is formed (Fig. 7) y 9 MHz recover, synchronous demodultor, lod nd enle genertors, nd Liner Feedck Shift Register code genertor. ) x x -5 ) x x -5 Fig. 6. Synchroniztion recovery signls: ) synchroniztion filtered, ) code recovered SYNCHRONIZATION RECOVERY SR_IN LENGTH_DEMODULATED LENGTH_DEMODULATED LOAD LOAD SR_IN Fix 7 SR_IN UFix 9_MHz 9_MHz LOAD GENERATOR ENABLE CODE_RECOVERED UFix _4_ CODE _RECOVERED 9 MHz RECOVER SYNCHRONOUS DEMODULATOR 9_MHz ENABLE (.5 MHz) LFSR CODE GENERATOR ENABLE GENERATOR Fig. 7. Synchroniztion recovery lock digrm 6.. Crrier recover (9 MHz) This system recovers the crrier of the synchroniztion signl (Fig. 8). Initilly the phsemodulted signl is squred nd filtered to get doule the crrier frequency with n 8 MHz nd pss filter (Fig. 9); the smple frequency is 8 MHz. The 8 MHz signl is squred y comprtor nd pulse is generted with ech rising edge. Finlly, n ccumultor genertes 9 MHz squred signl with 5% duty cycle. 9 MHz RECOVER Reltionl SR_IN Fix 7 z - Fix_6_4 ( ) Mult din dout rfd rdy Fix_4_37 Termintor Termintor Constnt > z - UFix z - & ~ Expression reinterpret Reinterpret UFix UFix q Accumultor 9_MHz FIR Compiler 4._8 MHz Dely FDATool FDATool _BPF Fig. 8. Crrier recovery of 9 MHz lock digrm 6.. Synchronous demodultor The lock in Fig. 3 is phse demodultor of the synchroniztion signl. The output indictes the length of the code with two consecutive edges of the signl (Fig. 3). The

18 Design Methodology with System Genertor in Simulink of FHSS Trnsceiver on FPGA 39 unipolr squre 9 MHz crrier is converted to ipolr; in this wy, the multiplier output ssumes non-zero vlues in ech semicycle. The dely lock for the crrier ensures the synchronous demodultion. The output of the low pss filter is introduced to comprtor to get the length signl demodulted. ) x -5 ).5 c) d) e) x x x -5 f) x x -5 Fig. 9. Crrier recovery signls: ) synchroniztion filtered input, ) squred signl, c) 8 MHz filtered, d) 8 MHz squre wve, e) pulse with rising edge, f) 9 MHz squre wve SYNCHRONOUS DEMODULATOR SR_IN Fix 7 z -4 Fix z - Fix 7 ( ) din dout rfd Fix_36_3 Termintor > z - Reltionl LENGTH _DEMODULATED Dely Mult rdy UFix 9_MHz UFix x UFix_3_ Fix + Termintor 5 FIR Compiler 4._LOW_PASS_FILTER FDATool Constnt CMult - Fix AddSu FDATool _LPF Constnt Fig. 3. Synchronous demodultor lock digrm ) x x -5 ) c) x x x x -5 d) e) x x x x -5 Fig. 3. Synchronous demodultor signls: ) synchroniztion input, ) 9 MHz multiplier input, c) multiplier output, d) filter output, e) length demodulted

19 Applictions of MATLAB in Science nd Engineering 6..3 Lod genertor The circuit in Fig. 3 produces pulse with the rising or flling edge t the input (Fig. 33). The output signl lods the initil vlue in the Liner Feedck Shift Register of the code genertor in the receiver. LOAD GENERATOR LENGTH _DEMODULATED ( & ~) (~ & ) LOAD z - Expression Dely Fig. 3. Lod genertor ) x x -5.8 ) x x -5 c) x x -5 Fig. 33. Lod genertor signls: ) input, ) delyed input, c) output 6..4 Enle genertor The input of this system (Fig. 34) is the 9 MHz squre crrier nd genertes.5 MHz enle signl. A pulse is otined with the rising edge t the input (Fig. 35). This signl is used s enle signl in six sttes counter; comprtor checks when the counter output is zero. Finlly, pulse is generted with ech rising edge of the comprtor output. The output signl hs the chip frequency, it will e used s input in Liner Feedck Shift Register to recover the pseudorndom code. ENABLE GENERATOR Convert cst en out UFix_3_ & ~ ENABLE (.5 MHz) 9_MHz UFix & ~ UFix Counter = z - z - Dely Expression Expression Reltionl z - UFix UFix Dely Constnt 3 Fig. 34. Enle genertor lock digrm

20 Design Methodology with System Genertor in Simulink of FHSS Trnsceiver on FPGA 3.5 ) x -5.5 ) c) x x -5 d) x -5 e) x -5 Fig. 35. Enle genertor signls: ) 9 MHz input, ) internl pulse with the input rising edge, c) counter output, d) zero vlue in the counter output, e) enle genertor output 6..5 Liner feedck shift register code genertor This system is LFSR similr to the code genertor in the trnsmitter (Fig. 36); with the exceptions of the lod signl to initilize the vlue nd the enle signl to generte the.5 MHz output rte. A dely lock synchronizes the lod nd enle signl. The LFSR inputs nd the vlue of the code recovered re shown in Fig. 37. LFSR CODE GENERATOR 3 UFix _5_ din Constnt LOAD ENABLE z -5 Dely lod dout en LFSR UFix _5_ Slice [:] UFix _4_ CODE _RECOVERED Fig. 36. Liner Feedck Shift Register code genertor lock digrm ) x -5 ) x -5 c) x -5 Fig. 37. Liner Feedck Shift Register code genertor signls: ) LFSR lod input, ) LFSR enle input, c) code recovered

21 3 Applictions of MATLAB in Science nd Engineering 6.3 Locl oscilltors The code recovered is the locl oscilltors input (Fig. 38). The two oscilltors were designed using two Direct Digitl Synthesizer locks, nd the four its input code must e converted to the input formt of the DDS lock. The frequency of the oscilltor F_ output (Fig. 39) is the trnsmitted frequency if the dt in the trnsmitter is minus.7 MHz; in other words, the left side of Tle minus.7 MHz. Consequently the vlue of the intermedite frequency in the receiver is.7 MHz. Similrly, the frequency of the oscilltor F_ output is the trnsmitted frequency if the dt in the trnsmitter is minus.7 MHz; in the sme wy, the right side of Tle minus.7 MHz. LOCAL OSCILLATORS UFix _4_ In F_ OSCILLATOR _F_ Fix_6_5 F_ CODE_IN In F_ Fix_6_5 F_ OSCILLATOR _F_ Fig. 38. Locl oscilltors lock digrm OSCILLATOR _F_ we In UFix _4_ x.853 UFix 6 Constnt Fix_9_9 + dt sine Fix_6_5 F_ CMult UFix _6_6 AddSu DDS Compiler. Constnt Fig. 39. Oscilltor F_ lock digrm 5 ) x -5 ) x -5 c) Fig. 4. Locl oscilltors signls: ) locl oscilltors input, ) oscilltor F_ output, c) oscilltor F_ output x -5

22 Design Methodology with System Genertor in Simulink of FHSS Trnsceiver on FPGA Doule rnch demodultor This demodultor is formed y two similr envelope detectors (Fig. 4). The inputs re the FHSS filtered signl nd the locl oscilltors outputs. The FHSS filtered signl is delyed to keep the synchroniztion with the locl oscilltors frequencies. The top rnch gets the wveform of the dt nd the ottom rnch the inverter dt. Lstly, the two outputs re compred nd finl output is the inry demodulted dt. F_ Fix_8_4 FHSS_IN 3 F_ Fix_6_5 Fix_6_5 F_ DATA FHSS_IN DATA_DEMODULATOR F_ DATA_N FHSS_IN Fix_4_38 Fix_4_38 DOUBLE BRANCH DEMODULATOR > z - Reltionl DEMODULATED _DATA DATA_N_DEMODULATOR Fig. 4. Doule rnch demodultor lock digrm The Fig. 4 is the top rnch lock digrm. The mixer of the rnch is the first multiplier nd the intermedite frequency nd pss filter. The second multiplier nd the low pss filter is the envelope detector. The Fig. 43 shows the signls in the demodultor. DATA_DEMODULATOR F_ Fix_6_5 z - () Mult Fix_8_4 FHSS_IN Fix_37_3 z - ( ) dout Mult Fix_4_9 din rfd Termintor 3 rdy Termintor 4 FIR Compiler 4._IF_.7 MHz FDATool Fix _6_4 din dout rfd rdy FIR Compiler 4._LOW_PASS_FILTER FDATool Fix _4_38 Termintor Termintor DATA FDATool _IF FDATool _LPF Fig. 4. Top rnch demodultor lock digrm 7. Chnnel simultion Once the design of the trnsceiver hs een finished, the performnces cn e tested inserting chnnel etween the trnsmitter nd the receiver. For this purpose, n Additive White Gussin Noise (AWGN) Simulink chnnel ws chosen (Fig. 44). In this chnnel, the signl-to-noise power rtio is fixed y the designer. The Bit Error Rte (BER) ws mesured with the Error Rte Clcultion lock, where the dely etween the dt must e specified. Besides, the instnt of synchroniztion in the receiver ( microseconds) is indicted to strt the it error counter. This lock genertes three vlues: the first is the Bit Error Rte, the second is the numer of errors, nd the third is the numer of its tested. Finlly, the BER is represented versus the signl-to-noise power rtio (Fig. 45).

23 34 Applictions of MATLAB in Science nd Engineering ) ) c) d) x x x x -5 e) f) g) x x x -5 Fig. 43. Doule rnch demodultor signls: ) intermedite frequency filter output in the top rnch, ) squred signl in the top rnch, c) low pss filter output in the top rnch, d) intermedite frequency filter output in the ottom rnch, e) squred signl in the ottom rnch, f) low pss filter output in the ottom rnch, g) demodulted output System Genertor FHSS TRANSMITTER FHSS RECEIVER doule EXTERNAL_DATA FHSS _SYNCHRONIZATION doule AWGN doule RX_IN DEMODULATED _DATA doule Constnt doule DATA_CONTROL FB DATA Termintor doule AWGN Chnnel Constnt Tx Rx Error Rte Clcultion doule Error Rte Clcultion Disply Scope Fig. 44. Error rte clcultion in presence of Additive White Gussin Noise.35 Bit Error Rte Signl to noise reltion (db) Fig. 45. Bit Error Rte represented versus the signl-to-noise power rtio (deciels)

24 Design Methodology with System Genertor in Simulink of FHSS Trnsceiver on FPGA Simultion nd compiltion with ISE After the system hs een simulted with Simulink, it cn e compiled with System Genertor. The chosen device is Virtex 4 FPGA, nd the hrdwre description lnguge is Verilog. A project is then generted for Integrted System Environment, which includes the files for the structurl description of the system. The syntx of the Verilog files cn e checked, nd the synthesis nd ehviorl simultion of the system cn e executed (Fig. 46). Therefter, the implementtion of the design llows the timing simultion of the trnsceiver (Fig. 47). Lstly, the progrmming file is generted for the chosen FPGA. Fig. 46. A long ehviorl simultion of the FHSS trnsceiver using ISE (4 microseconds) Fig. 47. Timing simultion of the FHSS trnsceiver using ISE (8 nnoseconds) The Integrted System Environment softwre provides power estimtor tht indictes dissiption of.5 wtts in the FPGA, nd n estimted temperture of 3.4 degrees centigrde. The FPGA core is supplied with. volts nd the input-output pins support the Low Voltge Complementry Metl Oxide Semiconductor (LVCMOS) volts stndrd. The design uses 49 of the 5 FPGA multipliers. The occuption rte of input-output pins in the FPGA is out.3%. However, this occuption rte cn e reduced until 3.3% if internl signls re not checked. 9. Conclusions nd future work With this design methodology the typicl dvntgeous fetures of using progrmmle digitl devices re reched. Repeting design consists in reprogrmming the FPGA in the chosen ord. The design nd simultion times re decresed, consequently the time to

25 36 Applictions of MATLAB in Science nd Engineering mrket is minimizing. The used tool permits gret flexiility; in others words, the design prmeters cn e chnged nd new fetures cn e checked within severl minutes. The flexiility llows to chnge the Direct Digitl Synthesizers nd filters prmeters nd to check its performnces. The Simulink simultions re esy to run, nd the signls re shown in floting point formt which mke esier its nlysis. These simultions re possile even efore the compiltion of the System Genertor locks to otin the hrdwre description lnguge files. With the System Genertor it is possile to simulte the full trnsceiver, the trnsmitter nd the receiver cn e connected through chnnel. Moreover, it is possile to simulte the trnsmission in presence of interference, distortion, multipth nd other spred spectrum signls using different codes.. References Anlog Devices (). AD985 DDS. URL: ctive on April Huck, S. & DeHon, A. (8). Reconfigurle Computing, Elsevier, ISBN , USA MthWorks. (). Simulink. URL: ctive on April Mxfield, C. (4). The Design Wrrior's Guide to FPGAs, Elseiver, ISBN , New York, USA Plnitkr, S. (3).Verilog HDL. Prentice Hll, ISBN , USA Pedroni, V. (4). Circuit Design with VHDL, The MIT Press, ISBN , USA Pérez, S.; Rdán, J.; Delgdo, F.; Velázquez, J & Pérez, R. (3). Design of synchronous Fst Frequency Hopping Spred Spectrum trnsceiver for indoor Wireless Opticl Communictions sed on Progrmmle Logic Devices nd Direct Digitl Synthesizers, Proceedings of XVIII Conference on Design of Circuits nd Integrted Systems, pp , ISBN X, Ciudd Rel, Spin, Novemer, 3. Simon, M.; Omur, J.; Scholtz, R. & Levitt, B. (994). Spred Spectrum Communictions Hndook, McGrw-Hill Professionl, ISBN 7385, USA Xilinx (). System Genertor. URL: ctive on April

26 Applictions of MATLAB in Science nd Engineering Edited y Prof. Tdeusz Michlowski ISBN Hrd cover, 5 pges Pulisher InTech Pulished online 9, Septemer, Pulished in print edition Septemer, The ook consists of 4 chpters illustrting wide rnge of res where MATLAB tools re pplied. These res include mthemtics, physics, chemistry nd chemicl engineering, mechnicl engineering, iologicl (moleculr iology) nd medicl sciences, communiction nd control systems, digitl signl, imge nd video processing, system modeling nd simultion. Mny interesting prolems hve een included throughout the ook, nd its contents will e eneficil for students nd professionls in wide res of interest. How to reference In order to correctly reference this scholrly work, feel free to copy nd pste the following: Sntigo T. Peŕez, Crlos M. Trvieso, Jesuś B. Alonso nd Jose L. Vśquez (). Design Methodology with System Genertor in Simulink of FHSS Trnsceiver on FPGA, Applictions of MATLAB in Science nd Engineering, Prof. Tdeusz Michlowski (Ed.), ISBN: , InTech, Aville from: InTech Europe University Cmpus STeP Ri Slvk Krutzek 83/A 5 Rijek, Croti Phone: +385 (5) Fx: +385 (5) InTech Chin Unit 45, Office Block, Hotel Equtoril Shnghi No.65, Yn An Rod (West), Shnghi, 4, Chin Phone: Fx: