FPGA Based Five-Phase Sinusoidal PWM Generator

Transcription

1 22 IEEE Interntionl Conference on Power nd Energy (PECon), 25 Decemer 22, Kot Kinlu Sh, Mlysi FPGA Bsed FivePhse Sinusoidl PWM Genertor Tole Sutikno Dept. of Electricl Engineering Universits Ahmd Dhln (UAD) Yogykrt, Indonesi Nik Rumzi Nik Idris, I.M. Alsofyni Dept. of Energy Conversion Universiti Teknologi Mlysi (UTM) Johor, Mlysi Auzni Jidin, L. Logn Rj Dept. of Power Electronics & Drives Universiti Teknikl Mlysi Melk (UTeM) Melk, Mlysi Astrct Multiphse mchine hs ecme populr in mny rottionl drive pplictions due to its reliility, high efficiency nd high qulity of wveforms. Moreover, this mchine ( 5 phse induction mchine) cn provide more options for selecting the most optimum voltge vector since the numer of switching devices of the inverter increses tht cn enhnce torque cpility nd improve dynmic performnces. However, the gret dvntgeous offered cnnot e relized if the switching nd control strtegy performed t very low smpling frequency which does not gurntee for the multiphse drive to operte t optimum opertions. This pper presents the reliztion of fivephse sinusoidl PWM signl genertor t fst smpling frequency using onechip progrmmle gte rry (FPGA). It cn e shown tht the genertion of sinusoidl PWM using FPGA cn perform the switching frequency of the inverter t 4 khz switching frequency tht my rise potentil for excellent drive performnces. KeywordsFivePhse Sinusoidl PWM Genertor, FPGA, inverter, motor drives, power converter, VHDL I. INTRODUCTION In recent yers, ttention in multiphse inverter technology hs incresed due to the enefits of using more thn three phses in drive pplictions. Multiphse motor possess severl dvntges, such s reduced the mplitude nd incresed the frequency of torque pulstions, reduced rotor hrmonics currents, reduced dclink current ripple, reduced sttor current per phse without incresing the voltge per phse, incresed fult tolernce, greter efficiency, lower per phse power hndling requirements, improved noise chrcteristics, nd higher reliility s compred to threephse motor [6]. In generl, the 5phse mchines produce the output current 68% higher thn those of the 3phse nd 6phse mchines [7]. The most commonly used of multiphse system which is the smllest phse numer, is fivephse. Severl work on design nd control of fivephse c motor drives were pulished, nd lso lot of modultion techniques for fivephse pulse width modultion (PWM) inverters hve developed [82]. However, different from threephse PWM inverters, till recently, not much works hd een mde in FPGAsed multiphse PWM signl generting tht results in miniml input nd output ripple on fivephse PWM inverters. In [3], erly model of sinusoidl PWM wveform genertion for fivephse converter using FPGA technology is presented. No work hs considered s to wht is the optimum technique tht result hs een investigted nd in minimum current ripples. In this pper, fivephse crriersed sinusoidl PWM signl genertor utilizing FPGA is presented. Reltionship of the voltge vectors nd switching sttes etween threephse nd fivephse system will e reviewed in section II, nd the relevnt expressions re derived. Section III descries principle of fivephse PWM generting, tht its implementtion is showed in section IV. Results nd discussions re presented in section V, nd in section VI conclusion is drwn. II. GENERAL EXPRESSIONS Figure shows the numer of switching sttes (or voltge vectors) provided y the 3phse induction mchinedrive system. v 5 V DC + v 4 S 3phse VSI v 4 is switched v 7 v () v 3 v 6 v () 3phse IM Figure. Voltge vectors nd switching sttes in 3phse induction mchinedrive system; () power circuit configurtion nd () spce voltge vectors plne S v 2 S c where, V () V () V 2 () V 3 () V 4 () V 5 () V 6 () V 7 () /2/$3. 22 IEEE 34

2 22 IEEE Interntionl Conference on Power nd Energy (PECon), 25 Decemer 22, Kot Kinlu Sh, Mlysi The 3phse motor drives re supplied with 3phse voltge source inverter (VSI) which cn only hve 2 3 = 8 voltge vectors. Figure 2 shows the numer of switching sttes (or voltge vectors) provided y 5phse induction mchinedrive system. In comprison with 3phse induction motor drives, the 5phse motor drives re supplied with 5phse voltge source inverter (VSI) which cn hve 2 5 =32 voltge vectors (i.e. 2 n where n is the numer of phse). In prticulr, the 32 spce voltge vectors re composed of three sets of vectors hving different mplitudes nd divide the voltge vector plne into ten sectors. The reltionship mong the DC side current, switching sttes nd the AC side current of the inverter with refer to Figure 2. cn e written s is required, the formtion of decgonl flux locus cn e ccomplished y modifying the flux error sttus ccording to flux positions. For clerer picture, the trjectory of flux in Sector I to form decgonl flux shpe with modified flux error sttus is shown in Fig. 3(). In this sector, the modified flux error sttus Ψ s is equl to to increse the flux (V 3 is selected) whenever the flux lies in susector i, otherwise the Ψ s is equl to to decrese the flux (V 4 is switched) whenever the flux lies in susector ii. V 3 V 4 V 2 () where,,, nd re the switching sttes of phse, 2, 3, 4 nd 5, respectively. () V 5 V 6 V V V 7 V DC + S 5phse VSI v is switched S i d i c () S c i S d 5phse IM i i e S e () Ψ s =V s,k t IV V V 8 III II I VI X VII IX VII Su. ii V 3 Su. i Ψ s in Sec. I V 4 (Ψ s =) (Ψ s =) V 6 V 5 V 4 V 5 V 26 V6 V 4 V 25 V 24 V 7 V 7 V 3 V 3 V 23 V 32 V 22 V 2 V 2 V 3 V 3 V 2 V V 27 V 28 V 8 V 8 V 29 V 2 V V where, V () V 2 () V 3 () V 4 () V 5 () V 6 () V 7 () V 8 () () V () V () V 2 () V 3 () V 4 () V 5 () V 6 () V 7 () V 8 () () V 2 () V 2 () V 22 () V 23 () V 24 () V 25 () V 26 () V 27 () V 28 () V 29 () V 3 () V 3 () V 32 () (c).6v DC.4V DC.4V DC.6V DC Phse voltge V V V 2 V 3 π 2π ωt V 4 V 5 V 6 V 7 V 8 () Figure 3. Decgonl flux locus with ppliction of step Voltge; () voltge vector plne, () sttor flux plne, (c) phse voltge Figure 2. Voltge vectors nd switching sttes in 5phse induction mchinedrive system, () power circuit configurtion nd () spce voltge vectors plne Figure 3 illustrtes the sttor voltges, i.e. step voltge tht cn e estlished in 5phse inverter y controlling the flux vector trjectory into decgonl shpe, s Figure 3(). If it In generl, if the sector k is eqully sudivided into Susectors, i nd ii, voltge vector of two possile voltges tht uses to increse the flux (Ψ s is equl to ) will e selected throughout Susector i nd voltge vector tht uses to decrese the flux (Ψ s is equl to ) will e used throughout Susector ii. As the flux vector moves from one sector to nother sector until it completely forms decgonl flux shpe, it is possile tht the 35

3 22 IEEE Interntionl Conference on Power nd Energy (PECon), 25 Decemer 22, Kot Kinlu Sh, Mlysi sttor voltge to rech t step voltge limit. This prticulrly cn e chieved when the motor speed exceeds its se speed where the ppliction of zero voltge vectors is zero. It should e noted tht the torque demnd will e nturlly fulfilled y the controller, which will grdully drops the pplictions of zero voltge vectors s the speed increses pproching its se speed. As the speed is further incresed nd no more zero voltge vectors re ville, the selection of voltge vector will nturlly trnsform to step mode. In other words y trnsforming the sttor flux locus to the decgonl shpe, we provide the room for the sttor voltge to increse eyond the decgonl oundry nd the torque demnd will nturlly trnsform the sttor voltge from PWM to step mode. The onoff signls for the switching devices cn e otined y compring fivephse reference signls or modulted signls to highfrequency tringulr signl s crrier signl. Figure 4 shows the phse reference signls used in this pper, which cn e written s V k sin θ v V k sinθ 2π 5 v V k sinθ v (2) By using eq.(), the dc input current during one crrier period, s shown Figure 5, cn e written s, for, for, for, for, for, for (3), for, for, for, for, for T s V ref2 V ref V ref3 V ref5 V ref4 V k sinθ v sin where is n ritrry signl tht is injected into the sinusoidl reference signls. Becuse the injection signl into the phse reference signls is sme, the verge vlue of the phsetophse voltges will not e ltered y this ritrry signl. The ritrry signl ssumption is vlid s long s the frequency of crrier (tringulr) signl is much higher thn the reference signls. In this condition, the reference signls cn e ssumed s constnts during one crrier period, nd the detiled inverter wveforms cn e drwn s shown in Figure 5. The figure is vlid during the intervl A of Figure 4. c T T T 2 T 3 T 4 T 5 T 5 T 4 T 3 T 2 T T id (id+ ie) i+ i i t t t2 t3 t4 t5 t6 t7 t8 t9 t t t2 Figure 5. Inverter wveforms over one crrier period s s s c s e s d i d Figure 4. Five reference signl III. FIVEPHASE SPWM ALGORITHM IMPLEMENTATION Figure 6 shows the design of overll experimentl setup. However, the pper only focus on FPGA sed fivephse sinusoidl PWM signls generting, nd the overll system is under preprtion. Due to limittion the llocted spce, in depth design procedure of PWM signl genertor tht is esy for modifying cnnot e presented. However, the overll system is hoped provide cler enough out this reserch in future nd hve cpility to involve mny reserches in next development phse. 36

4 22 IEEE Interntionl Conference on Power nd Energy (PECon), 25 Decemer 22, Kot Kinlu Sh, Mlysi 3phse Bridge Rectifier 5phse VSI Current Trnducers 5phse I.M 3ø I.M D.C Gen. I.E From 3phse Vric trnsformer Test ed * is gte drivers FPGA (APEX2KE)sed PWM T stt (2it) Ψ s (it) Sector (4it) Oscilloscope Input commnd 4CH ADC 2it DAC 2it DS4 DSPord DSP TMS32C3 I.E interfce ADC 6it i,i,i c,i d,i e ω Host computer Figure 6. Design of overll experimentl setup Figure 7. PWM signl genertor in lower switching frequency, () Qurtus result simultion, (). FPGA implementtion result Figure 8. PWM signl genertor in higher switching frequency, () Qurtus result simultion, (). FPGA implementtion result 37

5 22 IEEE Interntionl Conference on Power nd Energy (PECon), 25 Decemer 22, Kot Kinlu Sh, Mlysi IV. RESULTS AND DISCUSIONS The fivephse sinusoidl PWM modules re descried with mix VHDL nd schemtic entry design using Qurtus II softwre. After plcement nd routing, the design is implemented in Alter APEX2KE, where 496 logic elements re used. The designed IC cn operte t 33MHz system clock, nd the switching frequency is djustle. Figure 7 shows simultion nd implementtion result of PWM signl genertor in switching frequency lower thn Figure 8. From Figure 7 () is cler tht the PWM signls shift 2π/5 rd. The phse shifting in hrdwre implementtion is shown in Figure 9 (). In Figure 9(), leg pir of PWM signls on switching frequency higher thn Figure 7() nd 8 () is presented. Therefore, the PWM signls re redy to implement for controlling fivephse inverter s. V. CONCLUSION This pper presents the reliztion of progrmmle fivephse sinusoidl PWM signl genertor sed on FPGA. Reltionship of the voltge vectors nd switching sttes etween threephse nd fivephse system hve een reviewed, nd the relevnt expressions hve een derived, nd then principle of fivephse PWM generting hve een Figure 9. PWM signl genertor sed on FPGA, () Phse shifting of PWM signls, (). Leg pir of PWM signls on highest switching descried. The proposed scheme ws implemented nd tested using n FPGA technology. Experiment results show tht the constructed design cn cquire excellent operting performnce. It is elieved tht such fivephse PWM control IC s will ecome key components in power converter nd motor drives of the future. ACKNOWLEDGMENT The uthors would like to thnk the Universiti Teknologi Mlysi (UTM) nd Ministry of Higher Eduction (MOHE) of the Mlysin government for providing the funding for this reserch. REFERENCES [] E. E. Wrd nd H. HÃ rer, "Preliminry investigtion of n invertorfed 5phse induction motor," Electricl Engineers, Proceedings of the Institution of, vol. 6, pp , 969. [2] E. A. Klingshirn, "High Phse Order Induction Motors Prt I Description nd Theoreticl Considertions," Power Apprtus nd Systems, IEEE Trnsctions on, vol. PAS2, pp. 4753, 983. [3] K. N. Pvithrn, et l., "Studies on inverterfed fivephse induction motor drive," Power Electronics, IEEE Trnsctions on, vol. 3, pp , 988. [4] S. Willimson nd S. Smith, "Pulsting torque nd losses in multiphse induction mchines," Industry Applictions, IEEE Trnsctions on, vol. 39, pp , 23. [5] E. Levi, "Multiphse Electric Mchines for VrileSpeed Applictions," Industril Electronics, IEEE Trnsctions on, vol. 55, pp , 28. [6] O. Lopez, et l., "Multilevel Multiphse Spce Vector PWM Algorithm," Industril Electronics, IEEE Trnsctions on, vol. 55, pp , 28. [7] B. Zhng, et l., "Comprison of 3, 5, nd 6phse mchines for utomotive chrging pplictions," in Electric Mchines nd Drives Conference, 23. IEMDC'3. IEEE Interntionl, 23, pp vol.3. [8] J. W. Kelly, et l., "Multiphse spce vector pulse width modultion," Energy Conversion, IEEE Trnsctions on, vol. 8, pp , 23. [9] R. HyungMin, et l., "Anlysis of multiphse spce vector pulsewidth modultion sed on multiple dq spces concept," Power Electronics, IEEE Trnsctions on, vol. 2, pp , 25. [] A. Iql, et l., "Generlised Sinusoidl PWM with Hrmonic Injection for MultiPhse VSIs," in Power Electronics Specilists Conference, 26. PESC '6. 37th IEEE, 26, pp. 7. [] P. A. Dhono, et l., "Output CurrentRipple Anlysis of FivePhse PWM Inverters," Industry Applictions, IEEE Trnsctions on, vol. 45, pp , 29. [2] D. Csdei, et l., "A new crriersed PWM strtegy with minimum output current ripple for fivephse inverters," in Power Electronics nd Applictions (EPE 2), Proceedings of the 24th Europen Conference on, 2, pp.. [3] P. Adhikri nd M. Okro, "Fivelevel fivephse PWM signl genertion using FPGA," in North Americn Power Symposium (NAPS), 2, 2, pp