Engineer-to-Engineer Note

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1 Engineer-to-Engineer Note EE-236 Technicl notes on using Anlog Devices DSPs, processors nd development tools Contct our technicl support t dsp.support@nlog.com nd t dsptools.support@nlog.com Or visit our on-line resources nd Rel-Time Solutions Using Mixed-Signl Front-End Devices with the Blckfin Processor Contributed by Prshnt Khullr Rev 1 My 18, 2004 Introduction Certin res of telecommunictions infrstructure re evolving towrds the cretion of smller, loclized wireless networks. These so-clled picocells cn extend wireless connectivity to res where terrestril networks re not present. The development of this microinfrstructure brings bout the need for compct devices tht cn perform some of the tsks trditionlly ssocited with lrger wireless bse sttions. The Blckfin fmily of processors cn be gluelessly integrted with mixed-signl frontend (MxFE) for these nd wide vriety of other rel-time pplictions. The Blckfin rchitecture s signl processing performnce, ese of progrmmbility, nd flexible prllel port mke it n idel cndidte for such roles. Additionlly, MxFE devices integrte the necessry nlog front-end functionlity onto single chip with progrmmble rchitecture. Hrdwre Architecture The AD9866 MxFE is chosen for this discussion. The 12-bit dt converters (A/D nd D/A) on the MxFE connect to the Blckfin s prllel peripherl interfce (PPI) without ny externl logic. The PPI is hlf-duplex 16-bit prllel port which runs t up to hlf the speed of the Blckfin system clock (SCLK/2). At the mximum SCLK frequency of 133 MHz, this trnsltes to PPI updte rte of 66 MHz. The MxFE seril interfce for control register configurtion connects directly to the Blckfin s seril peripherl interfce (SPI). Depending on the ppliction s bndwidth requirements, hlfduplex or full-duplex implementtion cn be used. The former cn be ccomplished using the ADSP-BF531/BF532/BF533 line of processors which hve single PPI.! Full-duplex pplictions require dul PPI device such s the ADSP-BF561 symmetric multiprocessor. Such implementtions re not discussed in this EE-Note. As shown in Figure 1, the prllel digitl interfces of the 12-bit ADC nd 12-bit DAC connect directly to the Blckfin PPI. A fixed number of smples is trnsferred directly using from the ADC to buffer in the processor s internl memory. Signl processing my then be performed on this block of dt before the PPI direction is reversed nd the dt is trnsferred out to the DAC. Generl-purpose flg pins re used to lterntely enble nd disble the ADC nd DAC in deterministic fshion. All dt trnsfers re synchronized by single clock sourced by n oscilltor running t frequencies up to 60 MHz. Copyright 2004, Anlog Devices, Inc. All rights reserved. Anlog Devices ssumes no responsibility for customer product design or the use or ppliction of customers products or for ny infringements of ptents or rights of others which my result from Anlog Devices ssistnce. All trdemrks nd logos re property of their respective holders. Informtion furnished by Anlog Devices pplictions nd development tools engineers is believed to be ccurte nd relible, however no responsibility is ssumed by Anlog Devices regrding technicl ccurcy nd topiclity of the content provided in Anlog Devices Engineer-to-Engineer Notes.

2 Figure 1. Hrdwre Interconnection The seril connection between the Blckfin nd AD9866 is used to progrm the MxFE s onbord register set. These registers control vrious spects of the device s opertion including power mngement, clocking, progrmmble gin mplifiers, nd interpoltion filters. Softwre-Controlled Dt Flow To implement such hlf-duplex communiction scheme, the PPI nd controller on the Blckfin processor need to reverse their direction of dt trnsfer t specified intervls. This cn be ccomplished in softwre using block of configurtion code plced in n interrupt service routine (ISR). In the tested implementtion, generl-purpose timer ws used to generte the interrupts tht trigger this routine t deterministic intervls. The timer period ws chosen empiriclly such tht the time between successive interrupts ws dequte to ensure tht the ongoing trnsfer is ble to complete nd tht the turnround code is lso ble to execute to completion. The ltency ssocited with the /PPI turnround code hs two components. The first is the time ssocited with switching context between the min execution flow nd the ISR. The dely involved with reconfiguring the GPIO,, nd PPI register sets constitutes the reminder of the turn-round time. The subsequent quntittive nlysis of this dtflow uses the following bbrevitions: N: Number of Smples (Dt Window Size) CCLK: SCLK: DCLK: Blckfin Core Clock Frequency Blckfin System Clock Frequency Dt Clock/PPI Clock (synchronizes MxFE converters nd PPI) RX 0, RX 1: first nd second hlves of the received dt window, respectively TX 0, TX 1: first nd second hlves of the trnsmitted dt window, respectively P0, P1: signl processing of first nd second dt window hlves, respectively The following benchmrks were obtined empiriclly: Context Switch Ltency (Using EX_InterruptHndler with the stck in L1 Dt Memory) = ISR Initiliztion Ltency + Rel-Time Solutions Using Mixed-Signl Front-End Devices with the Blckfin Processor (EE-236) Pge 2 of 5

3 ISR Termintion Ltency = 32 CCLK cycles GPIO//PPI Reconfigurtion Ltency = 25 SCLK + 73 CCLK cycles (223 CCLK cycles t 6:1 SCLK:CCLK rtio) Totl Turn-round Ltency = 25 SCLK cycles CCLK cycles (255 CCLK cycles t 6:1 SCLK:CCLK rtio) To boost processing efficiency, ping-pong scheme is implemented in softwre, whereby signl processing tsks my be performed in prllel with trnsfers. In prticulr, input nd output dt buffers re broken into hlves so tht one hlf my be processed while the other is being red or written by the controller. The following dt-flow digrm nd execution timeline illustrte this hlf-duplex ping-pong scheme. ADSP-BF533 PPI Core Processing MxFE Converters PPI_Dt [11:0] Access Bus (DAB) Core Bus (DCB) RX 0 RX 1 TX 0 TX 1 Lod Dt Store Dt DCB L1 Internl Memory Buffers Figure 2. Digitl Dtflow Figure 3. Execution Timeline Rel-Time Solutions Using Mixed-Signl Front-End Devices with the Blckfin Processor (EE-236) Pge 3 of 5

4 ! For pplictions tht require lrger nd vribly-sized smple windows, the bove dt flow cn be modified esily to plce buffers in externl SDRAM. As demonstrted bove, the turn-round ltency reduces the vilble bndwidth minimlly. The mximum throughput of this rrngement cn be quntified s follows. With CCLK = 750 MHz, SCLK = 125 MHz, DCLK = 60 MHz: Turnround Ltency = 255 CCLK cycles 20 DCLK cycles Averge bndwidth lost to turn-round ltency = [1/(20 DCLK cycles)]*2 Bytes = (DCLK/20)*2 Bytes = 6 megbytes/second Averge RX Throughput = Averge TX Throughput = [(DCLK/2) (DCLK/20)]*2 Bytes = 54 megbytes/second Signl Processing The rel-time processing worklod tht cn be ccommodted depends on the size of the dt window. The time tken by the lgorithm to complete must not exceed the deterministic time required for the prllel trnsfer to complete. Approprite selection of the window size is therefore essentil. In generl, signl processing lgorithms tht execute slower thn in liner time become unmngeble s the window size grows lrge. On the other hnd, lgorithms tht execute fster thn in liner time my be more efficient to implement with lrge window sizes. The demonstrtionl exmple used to test this system performed 512-point Fst Fourier Trnsform (FFT) followed by n inverse FFT of the sme size on ech hlf of the 1024-smple window. Both lgorithms execute slower thn in liner time (O(n log n)); therefore they cn be expected to exceed the vilble processing time if the dt window size is incresed indefinitely. Hlf-Duplex Synchroniztion Dt trnsfers between the AD9866 high-speed converters nd the Blckfin PPI re synchronized using flg pins. The Blckfin processor cts s the mster device by toggling flg pins connected to the Trnsmit Enble (TXEN) nd Receive Enble (RXEN) pins of the AD9866. The ctive-high RXEN nd TXEN signls indicte when vlid dt is being red from the ADC or written to the DAC by the Blckfin PPI, respectively. These signls re not trnsmitted over the nlog medium. Therefore, in this hlfduplex scheme, n externl device connected to the nlog medium needs to be ble to hndle the lternting bursts of dt trnsmission nd reception. One possible implementtion is for the device to hve built-in circuitry to distinguish between vlid dt nd silence. A simple ded-bnd circuit, which enbles dt smpling fter certin nlog voltge threshold is exceeded, would be pproprite. Additionlly, the device would need to be progrmmed to receive nd trnsmit dt bursts of pre-specified length. When interfcing to externl devices tht require explicit dt frming, the TXEN nd RXEN signls cn be trnsmitted longside the nlog signls. Implementtion The hrdwre components nd configurtion required to evlute this design re outlined in the redme.txt file included in the VisulDSP++ project tht ccompnies this EE-Note. A glueless 3-bord interconnection is required. The AD9866 Evlution Bord connects directly to the ADSP-BF533/BF561 EZ-Extender crd, which interfces to the ADSP-BF533 EZ-KIT Lite Evlution Bord. The VisulDSP++ softwre module tht demonstrtes the hrdwre s functionlity is written entirely in embedded C. It provides proof-of-concept with enough flexibility nd modulrity to fit wide rnge of pplictions. Rel-Time Solutions Using Mixed-Signl Front-End Devices with the Blckfin Processor (EE-236) Pge 4 of 5

5 Conclusion With bidirectionl throughput of over 50 megbytes/second, flexible progrmming model, nd mple processing hedroom, the hlfduplex interconnection of Blckfin processor nd MxFE is prticulrly well-suited to low-cost wireless infrstructure. Moreover, it is generl enough to be used for ny number of rel-time pplictions. References [1] ADSP-BF533 Blckfin Processor Hrdwre Reference. Revision 1.0, November 2003, Anlog Devices Inc. [2] AD bit Brodbnd Modem Mixed Signl Front End Dtsheet. Revision 0.0, November Anlog Devices Inc. Document History Revision Rev 1 My 18, 2004 by P. Khullr Description Initil Relese Rel-Time Solutions Using Mixed-Signl Front-End Devices with the Blckfin Processor (EE-236) Pge 5 of 5