VLSI Design of High-Throughput SISO-OFDM and MIMO-OFDM Baseband Transceivers for Wireless LAN Networks

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1 74 ECTI TRANSACTIONS ON ELECTRICAL ENG., ELECTRONICS, AND COMMUNICATIONS VOL.5, NO.2 August 2007 VLSI Design of High-Throughput SISO-OFDM nd MIMO-OFDM Bsend Trnsceivers for Wireless LAN Networks Shingo Yoshizw 1, Yoshikzu Miyng 2, Nouo Htok 3, Biko Si 4, Norihis Tkym 5, Mski Hirt 6, Hiroshi Ochi 7, nd Yoshio Itoh 8, Non-memers ABSTRACT This pper descries VLSI design of highthroughput OFDM trnsceivers trgeted to future wireless LAN systems. The optimum prmeters composing new pcket OFDM frme re discussed y expnding the IEEE stndrd. The proposed system provides mximum trnsfer rte of 600 Mps y use of n 80-MHz occupied ndwidth nd MIMO technique. The SISO-OFDM nd MIMO-OFDM trnsceivers hve een designed ccording to the proposed OFDM formt. A lowltency nd full-pipelined rchitecture enles reltime processing of OFDM modultion/demodultion nd MIMO detection. In the MIMO detection, the circuit structures of zero-forcing nd MMSE- V-BLAST lgorithm in 2 2 MIMO configurtion re presented. The SISO-OFDM nd MIMO- OFDM trnsceivers hve een implemented to 90- nm CMOS technology. It performed smll implementtion logic size nd low power consumption fter rel LSI evlution. The circuit ehvior of the OFDM trnsceivers hs een verified y using the FPGA prototyping pltform tht executes oth digitl nd nlog OFDM send trnsmissions. Keywords: Wireless, OFDM, MIMO, VLSI Design, Digitl Circuit Mnuscript received on Jnury 30, 2007 ; revised on My 7, ,2 The uthors re with Grdute School of Informtion nd Science Technology, Hokkido University, Spporo , Jpn, Emils: yosizw@csm.ist.hokudi.c.jp nd miy@ist.hokudi.c.jp 3 The uthor is with the Centrl Res. L., Hitchi Ltd., Tokyo /Tohoku Institute of Tech., Sendi , Jpn, Emil: htok@tohtech.c.jp 4 The uthor is with the LSI Product Development Hedqurters, Rohm Co.Ltd., Kouhoku-ku, Yokohm , Jpn, Emil: Biko.Si@dsn.rohm.co.jp 5 The uthor is with the SANYO Semiconductor Co.,Ltd., Oizumi-mchi, Or-gun, Gunm , Jpn, Emil: Norihis.Tkym@snyo.co.jp 6 The uthor is with the SANYO Semiconductor Co.,Ltd., Oizumi-mchi, Or-gun, Gunm , Jpn, Emil: m.hirt@necel.com 7 The uthor is with the Dept. of CSE, Kyushu Inst. of Tech., Kwzu, Iizuk, Fukuok , Jpn, Emil: ochi@cse.kyutech.c.jp 8 The uthor is with the Dept. of Electricl Electronic Eng., 1. INTRODUCTION Wireless technologies, such s digitl rod csting, wireless LAN, nd wireless PAN, hve enled high-speed dt trnsmission in home nd personl networks. The IEEE stndrd supports mximum of 54 Mps t 20-MHz frequency nd y using orthogonl frequency division multiplexing (OFDM) [1]. For the stndrdiztion of next genertion wireless LAN networks proceeded y IEEE Tsk Group n (TGn), the Enhnced Wireless Consortium (EWC) group sets gol to chieve dt rtes of more thn few hundred using multiple-input nd multiple-out (MIMO) technique [2]. The EWC proposl indictes four min modifictions from the IEEE stndrd to chieve 600-Mps dt rte, i.e., the doption of 40- MHz occupied ndwidth, 400-ns short gurd intervl, 5/6 coding rte nd 4 4 MIMO configurtion. On the other hnd, our reserch project supported y STARC 1 hs developed comprle wireless OFDM system where this project minly hs focused on estlishing high-speed wireless dt links etween informtion home pplinces, e.g., digitl dt trnsmission of dvnced high-definition digitl video grphics. The proposed system chieves the sme mximum dt rte of 600 Mps y use of n 80-MHz occupied ndwidth nd 2x2 MIMO configurtion. The proposed system occupies the doule signl ndwidth of the EWC proposl in frequency utiliztion. However, the EWC proposl hs the following technicl difficulties to trnsmit the ove 600-Mps dt: First, it ws difficult to uild up hrdwre tht performs rel time frequency-domin MIMO chnnel estimtion nd coding ecuse of the lrge hrdwre complexity nd high power consumption. Second, the use of 5/6 coding rte is not sufficient for error correcting in Viteri decoder. Low density prity check code (LDPC) nd turo decoders improve trnsmission performnce s lterntive decoding schemes, however increse complexity nd must del with their incresed power. Tottori University, Koym-minmi, Tottori , Jpn, Emil: itoh@ele.tottori-u.c.jp 1 Arevition of Semiconductor Technology Acdemic Reserch Center in Jpn.

2 VLSI Design of High-Throughput SISO-OFDM nd MIMO-OFDM Bsend Trnsceivers for Wireless LAN Networks 75 Tle 1: system. Dt rte (Mps) Principl prmeters in pcket OFDM K F F n T g N s N R DFT size Bndwidth (Hz) Gurd crrier ndwidth (Hz) Gurd intervl (s) Numer of dt sucrriers Coded its per sucrrier Coding rte K=64 K=128 K=256 K=512 K=1024 K=2048 DFT size Bndwidth (MHz) Fig.1: Dt rte estimte y function of DFT size nd ndwidth. This pper descries the totl VLSI design of the proposed OFDM system, i.e., SISO-OFDM nd MIMO-OFDM trnsceivers. Their results indicte tht our proposed system cn provide relistic instnces in trnsmission performnce nd implementing hrdwre. A new OFDM frme formt in the proposed system is discussed in Section II. Section III reports the simultion results in trnsmission performnce compring the EWC proposl with the proposed system. Section IV nd V indicte low-ltency nd full-pipelined rchitecture in order to enle reltime opertions of OFDM demodultion/modultion nd MIMO detection, respectively. The MIMO detection circuits sed on zero-forcing nd MMSE- V-BLAST techniques re descried. Section VI reports the VLSI implementtion results of the designed trnsceivers in 90-nm CMOS process, where circuit size nd power dissiption re evluted. Section VII introduces the FPGA prototyping pltform tht performs oth digitl nd nlog OFDM send trnsmissions to verify circuit ehviors of the OFDM trnsceivers. Section VIII summrizes the key points nd mentions future work. 2. PROPOSED OFDM SYSTEM The optimum prmeters composing new OFDM frme formt re discussed in this pper. In order to relize 600-Mps dt rte system, we first consider the OFDM prmeters of SISO-OFDM system Frme formt in the proposed OFDM sys- Tle 2: tem. Smpling period 12.5 ns Numer of FFT/IFFT points 512 Numer of dt sucrriers 480 Numer of pilot sucrriers 20 PLCP durtion (short & long premles) 16 µs Symol durtion 7.2 µs FFT/IFFT window durtion 6.4 µs Gurd intervl durtion 0.8 µs Sucrrier frequency spcing MHz Tle 3: Trnsmission modes nd dt rtes of the STARC-SISO nd the STARC-MIMO. Mode Modultion Coding SISO 2 2 MIMO Rte (Mps) (Mps) 1 QPSK 1/ QAM 1/ QAM 1/ QAM 3/ with 300-Mps dt rte. The 2 2 MIMO-OFDM system processes two dt strems nd doules the ove dte rte. For the SISO-OFDM system, we presented the dt rte estimte for vrile OFDM prmeters y expnding the IEEE stndrd in [3]. The finl representtion is given y D(K, F, F n, T g, N, R) = ( K 1 F ) n F N R. (1) F K + F T g Tle 1 enumertes the prmeters in the ove eqution. For the four prmeters of F n, T g, N, nd R, we dopt the sme vlues used in the IEEE stndrd: The gurd crrier ndwidth F n is (Hz). The gurd intervl T g is (s). The coded its per sucrrier is N = 6 (its). The coding rte is R = 3/4. By sustituting for ove prmeters, the estimte eqution is trnsformed into function given y DFT size nd signl ndwidth. Figure 1 shows the estimtes of dt rtes for vrile DFT points nd signl ndwidths. A 64-point DFT reches round 60 Mps in 20-MHz ndwidth. However, the 64-point DFT is not sufficient in incresing the dt rte for n 80-MHz ndwidth. A 512-point DFT chieves 300 Mps in n 80-MHz ndwidth. Therefore, the proposed OFDM system employs the 512-point FFT/IFFT used for OFDM modultion/demodultion. Tle 2 shows the proposed OFDM frme formt. The sucrrier frequency spcing is out hlf of tht in the IEEE stndrd. The principl trnsmission modes nd their dt rtes re depicted in Tle 3, where the STARC-SISO nd the STARC-MIMO modulte/demodulte one nd two dt strems, respectively.

3 76 ECTI TRANSACTIONS ON ELECTRICAL ENG., ELECTRONICS, AND COMMUNICATIONS VOL.5, NO.2 August 2007 Tle 4: Simultion prmeters of the EWC proposl nd the STARC-MIMO. Bndwidth GI Length FFT/IFFT Size Antenn Structure (Tx, Rx) Coding Coding Rte Decoding Dt Bits per Symol (DBPS) Numer of the OFDM symols Pcket Size Mximum Dt Rte EWC Proposl 40 MHz 400 ns 128 4, 4 MMSE-V- BLAST 5/6 STARC-MIMO 2, 2 MMSE-V- BLAST ytes 80 MHz 800 ns 512 Convolutionl Coding 64-Stte Viteri Algorithm 600 Mps 3/4 2, 2 Zero- Forcing Tle 5: Chnnel Environments. Modultion 64-QAM Chnnel model 18-pth Ryleigh fding Doppler frequency 20 Hz Dely profile TGn Chnnel D RMS dely spred 50 ns 3. TRANSMISSION PERFORMANCE BER performnce is compred the proposed system with the EWC proposl y send simultion. The simultion prmeters in the 600-Mps trnsmission modes listed in Tle 4. The EWC proposl uses 128-point FFT nd 5/6 coding rte. The proposed system is evluted y tking the 2 2 MIMO-OFDM systems sed on zero-forcing (ZF) nd MMSE-V- BLAST detection techniques. Dt its per symol (DBPS), the numer of OFDM symols, nd pcket size is the sme etween the EWC proposl nd the STARC-MIMO. The conditions of multipth fding environments re listed in Tle 5. The multipth dely profile is sed on the TGn Chnnel D [4]. Figure 2 shows the simultion results of BER performnce. The 2 2 STARC-MIMO systems outperform the EWC proposl y 6 to 7 db nd more thn 10 db in SNR for BER=10 2 nd BER=10 3, respectively. The use of 5/6 coding rte is considered to e insufficient to remove it errors y Viteri decoding under multipth fding chnnels, s is oserved from these results. 4. TRANSCEIVER ARCHITECTURE Since the numer of dt sucrriers is ten times lrge s tht of IEEE stndrd, new VLSI rchitecture is to e discussed to del with such n BER x4 MIMO-OFDM IEEE802.11n (BLAST-MMSE) 2x2 STARC-MIMO (V-BLAST-MMSE) 2x2 STARC-MIMO (Zero-Forcing) SNR (db) Fig.2: BER performnce in the EWC proposl nd the STARC-MIMO systems. (A) Encoding & Mpping (E) Pre-FFT SRAM (B) Frme Synchroniztion (C) FFT/IFFT & Chnnel Equliztion Trnsmitter Receiver (D) GI/PLCP Genertion (F) Post-FFT SRAM (G) Soft-Out Dempping (H) Viteri Decoding Fig.3: Block digrm in the SISO-OFDM trnsceiver. (A) Encoding & Mpping (E) Pre- Trnsform Memory (B) Timing Synchroniztion (C) FFT/IFFT Trnsmitter Receiver (D) GI/PLCP Insertion (F) Post- Trnsform Memory (G) MIMO Detection (H) De- Mpping (I) Viteri Decoding Fig.4: Block digrm in the 2 2 MIMO-OFDM trnsceiver. incresed complexity. The proposed system hs smpling rte of 80 Msps. A recursion procedure is not suitle for rel-time processing ecuse high clock rte mkes it difficult to design n ppliction specific circuit nd consumes lrge power. We pply full-pipelined rchitecture which processes one dt per cycle t the minimum frequency of 80 MHz. Figure 3 shows overll lock digrm in the SISO-OFDM trnsceiver consisting of processing locks (A) to (H). The two SRAM locks djusts dt communiction timing etween djoined processing locks. For instnce, while the lock (A) sends mpped dt to the neighor SRAM lock (E), the FFT/IFFT lock (C) reds out mpped dt in the previous symol. As long s the locks of (A) nd (C) finish their own processing within symol durtion,

4 VLSI Design of High-Throughput SISO-OFDM nd MIMO-OFDM Bsend Trnsceivers for Wireless LAN Networks 77 Short Premle Long Trining Symols Dt Symols Chnnel Estimtion (1 stge) Inverse Mtrix Clcultion (7 stges) S T 11 T 21 D 11 D 21 D K1 T11T 12 H * H = H *δ 1 G = H * δδ * T 12 T 22 D 12 D 22 D K2 T 21 H 11 H 11 G 11 from FFT Chnnel Estimtion nd Pre-processing T 1,T 2 Chnnel Estimtion H Inverse Mtrix G = Η 1 Ltency D Memory MIMO Detection Fig.5: OFDM frme structure, lock digrm nd processing timing chrt in the MIMO detection lock. G y T 22 Fig.6: H 12 H 21 H 22 H 12 H 21 H 22 δ =H δ * 11H 22 H12H 21 δδ * 1 δδ * Circuit structure in the ZF lgorithm. G 1 T T 1 2 H G 2 G 2 D G 12 G 21 G 22 Chnnel Estimtion nd Pre-processing (10 stges) Tle 6: MIMO detection complexity in the EWC proposl nd the STARC-MIMO. STARC-MIMO EWC Proposl Antenn (Tx, Rx) 2, 2 2, 2 4, 4 Algorithm Zero-Forcing MMSE-V-BLAST MMSE-V-BLAST Complexity k W y ˆα r W y ˆα r (6 stges) no dt collision occurs etween these locks. The strt timing in ech lock is given y the strt point of FFT/IFFT period nd determined y the frme synchroniztion lock (B). In the FFT/IFFT lock, pipeline FFT using hyrid Rdix-2 nd Rdix-2 2 Single-pth Dely Feedck (R2SDF nd R2 2 SDF) rchitecture [5] is implemented to the system. The Viteri lock decodes prllel dt sequences y 3 its per clock. The three Viteri decoders perform their decoding for supporting the mximum dt rte of 64-QAM demodultion, where they were designed in the previous reserch [6]. The 2 2 MIMO-OFDM trnsceiver is shown in Fig. 4. The processing locks from (A) to (I) re duplicted except the time synchroniztion lock nd the MIMO detection lock. 5. MIMO DETECTION 5. 1 Required timing constrint The OFDM frme structure, the lock digrm, nd the processing timing chrt in the MIMO detection lock re illustrted in Fig. 5. The MIMO frme consists of the short symol, the long trining symols, nd the dt symols. The long trining symols T ij with the i-th symol index nd the j-th strem re used for the estimtion of MIMO chnnel mtrix. The chnnel mtrix H is otined from n orthogonl trining where this eqution is descried ŷ ŷ y Fig.7: Modified processing procedure in MMSE-V- BLAST lgorithm. s: H 11 = (T 11 T 21 )/2 (2) H 12 = (T 11 + T 21 )/2 (3) H 21 = (T 12 T 22 )/2 (4) H 22 = (T 12 + T 22 )/2. (5) The MIMO detection lock performs the chnnel estimtion nd the inverse mtrix clcultion given y G=H 1 (clled s pre-processing ) t receiving the long trining symols. At receiving the dt symols of D, the MIMO lock decodes the trnsmitted dt y y=gd. If the MIMO decoding is immeditely pplied to the first dt symol, the chnnel estimtion nd the MIMO detection should e completed efore receiving the first dt symol. Hence, the permitted ltency durtion is within the gurd intervl (see Ltency in Fig. 5). The chllenging work is to relize rel-time MIMO detection which performs lrge complexity of inverse mtrix clcultion so tht the MIMO chnnels for ll the su-crriers cn e clculted

5 78 ECTI TRANSACTIONS ON ELECTRICAL ENG., ELECTRONICS, AND COMMUNICATIONS VOL.5, NO.2 August 2007 on time. Tle 6 shows the MIMO detection complexity per sucrrier in the EWC proposl nd the STARC-MIMO, where QR decomposition lgorithm is utilized for clculting n inverse mtrix. We hve developed the 2x2 MIMO-OFDM detection locks in zero-forcing nd MMSE-V-BLAST techniques. As well s the other processing locks, full-pipeline rchitecture is introduced. The designed circuits tend to increse circuit re; however they stisfy the ove timing constrint nd indicte prcticl instnces in developing hrdwre Zero-forcing The zero-forcing (ZF) lgorithm is simply chieved y computing n inverse mtrix G. The inverse formul is given y ( ) g11 g 12 = g 21 g 22 1 h 11 h 22 h 12 h 21 ( ) h22 h 12, (6) h 21 h 11 where h ij nd g ij re fctors of the chnnel mtrix H nd the inverse mtrix G, respectively. The QR decomposition is generlly utilized in the inverse mtrix clcultion in order to reduce complexity. However, the complexity is not lrge s for 2x2 MIMO configurtion. Figure 6 shows the circuit structure of the ZF lgorithm. This circuit opertes 8-stge pipeline including complex divide opertion. The totl ltency is 11 cycles including memory ccess. It cn stisfy the ove timing constrint for the gurd intervl of 64 cycles (12.5-ns clock period 64 cycles = 800 ns). The numers of rel nd complex multipliers re 8 nd 11, respectively MMSE-V-BLAST The originl V-BLAST is expressed s recursive procedure [7]. In our rchitecture, the procedure is modified to introduce pipeline nd concurrent processing. In the 2x2 MIMO, the modified procedure is descried s follows: G 1 = H + (7) G 2 = + (H) 2 (8) G 2 = + (H) 1 (9) w = (G 1 ) 1 (10) w = (G 1 ) 2 (11) ȳ = w T r (12) ȳ = w T r (13) ˆα = Q[ȳ ] (14) ˆα = Q[ȳ ] (15) ŕ = r ˆα (H) 1 (16) ŕ = r ˆα (H) 2 (17) ŷ = G 2 ŕ (18) ŷ = G 2 ŕ (19) k = rg min j (G 1 ) j 2 (20) Tle 7: Circuit performnce of the SISO-OFDM Trnsceiver. System Control Coder & Mpping Timing Synchroniztion FFT/IFFT & Equlizer GI PLCP Signls SRAMs for Pre-FFT SRAMs for Post-FFT Soft Dempper Viteri Decoder Totl Circuit Are (μm 2 ) No. Logic Gtes TX (mw) RX (mw) Tle 8: Circuit performnce of the zero-forcing MIMO-OFDM Trnsceiver. System Control Coder & Mpping Timing Synchroniztion FFT/IFFT GI PLCP Signls SRAMs for Pre-FFT SRAMs for Post-FFT Soft Dempper Viteri Decoder Totl y = { Circuit Are (μm 2 ) No. Logic Gtes TX (mw) RX (mw) (ȳ, ŷ ) T if k=1 (ŷ, ȳ ) T otherwise, (21) where (H) j is the j-th column of H nd + denotes n inverse mtrix opertion sed on MMSE criterion. The inverse mtrices of G 2 nd G 2 re precomputed efore the MIMO detection t Eqs. (8) nd (9). This pre-computtion converts recursive procedure into one-time procedure. It prepres oth cndidtes of (ȳ, ŷ ) nd (ŷ, ȳ ) for optiml detection ordering. Figure 7 depicts the modified procedure in MMSE-V-BLAST lgorithm, which is pplied to the MIMO detection lock. While the two cndidtes re clculted t Eqs. (10) to (19), the chnnel order informtion of k is simultneously computed t Eq. (20). The chnnel estimtion nd the pre-processing finish within 13-cycle ltency including memory ccesses. The numers of rel nd complex multipliers require 16 nd 27, respectively. 6. VLSI IMPLEMENTATION In the VLSI implementtions of the SISO-OFDM nd the 2x2 MIMO-OFDM trnsceivers, their minimum wordlengths hve een explored y using fixed point simultion [8]. The trnsceivers hve een designed y using Verilog in RTL level design nd implemented to logic gtes on 90-nm CMOS stndrd cell lirry. The operting clock frequency is 80 MHz,

6 VLSI Design of High-Throughput SISO-OFDM nd MIMO-OFDM Bsend Trnsceivers for Wireless LAN Networks 79 Tle 9: Circuit performnce of the MMSE-V- BLAST MIMO-OFDM Trnsceiver. System Control Coder & Mpping Timing Synchroniztion nd SNR Estimtion FFT/IFFT Circuit Are (μm 2 ) No. Logic Gtes TX (mw) RX (mw) To RF From RF DACs DACs ADCs Interpolte & FIR Decimte & FIR Test Dt OFDM OFDM Trnsmitter Receiver Rndom Signl PC IF IDE Cle GI PLCP Signls SRAMs for Pre-FFT Trnsmitter Dempper SRAMs for Post-FFT Soft Dempper Viteri Decoder Totl Trnsmit Receive Test Viteri Decoder Receiver Decoder Fig.9: Block digrm of the FPGA ord. Fig.8: Photogrphs of the FPGA ord nd the RF modules. clock frequency nd the other modules operte t its hlf clock speed. The current FPGA ord enles send trnsmission vi ADCs nd DACs. BER nd PER cn e otined from this send trnsmission. which is common to the trnsceivers. The power voltge is 1.1V for ll devices. Circuit re, logic gte counts, nd power dissiption re reported in Tle 7, 8 nd 9. The SISO-OFDM trnsceiver ws designed in 0.78 millions of logic gtes with 110 mw of mximum power consumption. The Viteri decoder hs een re-designed to reduce oth circuit re nd power dissiption, compred to the previous work [9]. The zero-forcing MIMO-OFDM trnsceiver hs 1.42 millions in logic gtes nd dissiptes 206 mw in the mximum. The FFT/IFFT nd Viteri locks hve impct on the overll system. The MMSE-V-BLAST MIMO-OFDM trnsceiver hs 2.60 millions in logic gtes nd increses dissipted power to 266 mw. The circuit size of the MIMO detection lock in the MMSE-V-BLAST ecomes out three times of the zero-forcing, However, it does not increse power consumption s much s circuit re ecuse the MIMO detection is executed y short period. 7. FPGA VERIFICATION Figure 8 shows the FPGA verifiction ord used to verify circuit ehvior of the OFDM trnsceivers nd RF modules. Figure 9 shows the lock digrm of the FPGA ord in the SISO-OFDM system. The FPGA ord ctivtes three chips of the trnsmitter, the receiver, nd the Viteri decoder, which is sed on Xilinx Vertex II-Pro XC2VP70. We hve dded n interpoltor, decimtor, rndom signl genertor, nd us interfces to communicte with PC. The interpoltor nd the decimtor require 100-MHz 8. CONCLUSION This pper hs descried the VLSI design of the SISO-OFDM nd the MIMO-OFDM trnsceivers chieving 600-Mps dt rte for wireless LAN networks. The proposed frme formt is sed on the use of 512-point FFT/IFFT nd n 80-MHz occupied signl ndwidth. The 2x2 MIMO configurtion doules the dt rte of the SISO-OFDM system. Compred to the 600-Mps trnsmission mode in the EWC proposl, the STARC-MIMO hs superior trnsmission performnce nd lower complexity in the MIMO detection. In the hrdwre rchitecture, the SISO-OFDM nd the MIMO-OFDM trnsceivers hve een designed y the policy of pplying full-pipeline nd concurrent processing. The zero-forcing nd MMSE-V-BLAST techniques hve een implemented to hrdwre s prcticl instnces. The OFDM trnsceivers hve een implemented to 90-nm CMOS process nd evluted on circuit re nd power dissiption. The FPGA ord hs een presented to verify circuit ehviors nd execute send trnsmission. As future work, the VLSI implementtion of 4 2 MIMO configurtion will e discussed. The 4 2 MIMO-OFDM system is given y LSTBC system [10] which comines lyered spcetime (LST) [11] nd spce-time lock coding (STBC) [12] techniques. The 4 2 MIMO hs much etter trnsmission performnce thn the 2 2 MIMO. This utiliztion is ssumed in downlink trnsmission when wireless sttion hs four trnsmission ntenns.

7 80 ECTI TRANSACTIONS ON ELECTRICAL ENG., ELECTRONICS, AND COMMUNICATIONS VOL.5, NO.2 August 2007 ACKNOWLEDGMENTS The uthors would like to thnk Reserch nd Development Hedqurters, Ymtke Corportion nd the VLSI Design Eduction nd Reserch Center (VDEC), Tokyo University for fruitful discussions. This study is supported in prts y Semiconductor Technology Acdemic Reserch Center (STARC), Project 308. References [1] IEEE Std , Wireless LAN medium ccess control (MAC) nd physicl lyer (PHY) specifictions: high-speed physicl lyer in 5 GHz nd, 1999 Edition. [2] Enhnced Wireless Consortium puliction, HT PHY specifiction v1.27, Version 1.27, Dec [3] Shingo Yoshizw, Yoshikzu Miyng et l., 300-Mps OFDM send trnsceiver for wireless LAN systems, Proc. IEEE ISCAS2006, pp , My [4] V. Erceg et l., TGn chnnel models, IEEE /940r4, My [5] Shousheng He nd Torkelson M., A new pproch to pipeline FFT processor, Prllel Processing Symposium, 1996, pp , Apr [6] Ysuyuki Htkw nd Yoshikzu Miyng, Roust LSI rchitecture nd its high speed Viteri decoder, IEEE Interntionl Midwest Symposium on Circuits nd Systems (MWS- CAS), Vol. 2, pp , July [7] P. W. Wolninsky, G. J. Foschini, G. D. Golden, R. A. Vlenzuel, V-BLAST: n rchitecture for relizing very high dt rtes over the rich-scttering wireless chnnel Proc. IEEE ISSSE98, Sep [8] K. Hn nd B. L. Evns, Wordlength optimiztion with complexity-nd-distortion mesure nd its pplictions to rodnd wireless demodultor design, Proc. IEEE ICASSP2004, Vol. 5, pp , My [9] Shingo Yoshizw nd Yoshikzu Miyng, VLSI implementtion of high-throughput SISO-OFDM nd MIMO-OFDM trnsceivers, Interntionl Symposium on Communictions nd Informtion Technologies (ISCIT), No. T2D-4, Oct [10] X. Zhungm, F. W. Vook, S. R-Leveil, K. Gosse, Trnsmit diversity nd sptil multiplexing in four-trnsmit-ntenn OFDM, Proc. IEEE ICC2003, Vol. 26, pp , My [11] G. J. Foschini, Lyered spce-time rchitecture for wireless communiction in fding environment when using multi-element ntenns, Bell Ls Tech. J., Vol. 1, pp , [12] S. M. Alomouti, A simple trnsmit diversity technique for wireless communictions, IEEE Journl on Select Ares in Communictions, Vol. 16, No.8, pp , Oct Shingo Yoshizw He received the B.E., M.E. nd Dr.Eng. degrees from Hokkido University, Jpn in 2001, 2003 nd 2005, respectively. He is n Assistnt Processor nd currently working t the Grdute School of Informtion Science nd Technology, Hokkido University. His reserch interests re speech processing, speech recognition, wireless communiction, nd VLSI rchitecture. Yoshikzu Miyng He received the B.S., M.S., nd Dr.Eng. degrees from Hokkido University, Jpn in 1979, 1981, nd 1986, respectively. From 1983 to 1987, he ws Reserch Associte t the Institute for Electronic Science, Hokkido University. From 1987 to 1988, he ws Lecturer t the Fculty of Engineering of Hokkido University. From 1988 to 1997, he ws n Associte Professor there. He is currently Professor t the Grdute School of Informtion Science nd Technology, Hokkido University. His current reserch interests re dptive signl processing, non-liner signl processing, nd prllel-pipelined VLSI systems. Nouo Htok He received the B.S.E.E. degree nd the M. Sc. degree in Electricl nd Electronics Engineering from Tohoku University, in 1976 nd 1978, respectively, nd the Ph.D in Engineering in 1992 from Tohoku University. He joined Centrl Reserch Lortory, Hitchi Ltd. in 1978, nd he spent one yer from 1988 to 1989 s Visiting Resercher t Crnegie Mellon University in U.S.A. From 1989 to 1993, he ws Lortory Mnger of Hitchi Dulin Lortory in Irelnd nd fter returning to HCRL in Jpn he took mngement responsiilities s Chief Reserch Scientist. He is currently Professor of Tohoku Institute of Technology in Sendi, Jpn. His reserch interests include medi implementtion on microprocessors, nd lgorithm development on speech recognition, speech synthesis, speech trnsltion, nd rtificil intelligence. Dr. Htok is memer of the IEEE Acoustic, Speech, nd Signl Processing Society, the Institute of Electronics, Informtion nd Communiction Engineers (IEICE), Jpn, nd the Acousticl Society of Jpn. He is presidentelect in Informtion Systems Society of IEICE. Biko Si He received the B.E. from Shnghi University in 1985, nd received M.E. from Yokohm Ntionl University in He worked for Spce nd Science Ministry of Chin in Shnghi from 1985 to He worked s system engineer in Pioneer Electronic Corportion Jpn from 1990 to 1996 nd s system design mnger in Philips Semiconductors from 1996 to

8 VLSI Design of High-Throughput SISO-OFDM nd MIMO-OFDM Bsend Trnsceivers for Wireless LAN Networks The is LSI product design mnger in Rohm Co,.Ltd. His reserch interests re signl processing, communiction, video processing nd cryptogrm. Norihis Tkym He received the B.E. nd M.E. degrees in Electricl Engineering from Mie University, Jpn in 1981 nd 1983, respectively. He joined SANYO Electric Co., Ltd., in He hs een engged in reserch nd development of VLSI design techniques for imge processing nd wireless communiction systems. From 2006, he is working t SANYO Semiconductor Co., Ltd. Mski Hirt He received the B.S., M.S. degrees in electronics engineering from the University of Electro- Communictions, Tokyo in 1972 nd 1974, nd Ph.D. degree in electronics engineering from the University of Tokyo, Tokyo in He joined NEC Corportion, Kwski, Jpn in 1974, where he hs een engged in the reserch of CMOS VLSI circuits design. He worked t STARC (Semiconductor Technology Acdemic Reserch Center) from 2000 to He is currently senior mnger in NEC Electronics Corportion. His reserch interests focus on System LSI rchitecture. Dr. Hirt is memer of the Institute of Electronics, Informtion nd Communiction Engineers of Jpn. Hiroshi Ochi He received the B.E. nd M.E. degrees from Ngok Institute of Technology, nd Ph.D. from Tokyo Metropolitn University, Jpn in 1981, 1984, nd 1992 respectively. He is Processor t the deprtment of CSE, Kyushu Institute of Technology His reserch interests re signl processing, wireless communiction, nd their VLSI implementtion. Yoshio Itoh He received the B.E. degree in electronics engineering from Osk Institute of Technology, M.E. nd D.E. degrees in electricl engineering from Osk Prefecture University in 1979,1981 nd 1991, respectively. He is now Professor in the Fculty of Engineering, Tottori University, Jpn. His reserch interests re in the re of digitl signl processing nd communiction systems. From 2000 to 2004, He ws n Associte Editor of Trns. on Fundmentls of IEICE. He is memer of the IEEE, IEICE nd Acousticl Society of Jpn.