Modeling of Conduction and Switching Losses in Three-Phase Asymmetric Multi-Level Cascaded Inverter

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1 Proceedings of the 5th WEA nt. onf. on Power ystems nd Electromgnetic omptibility, orfu, Greece, August 23-25, 2005 (pp ) Modeling of onduction nd witching Losses in Three-Phse Asymmetric Multi-Level scded nverter M. G. Hosseini Aghdm,. H. Fthi Abstrct--The designer of power converters must model the losses of converter switches to optimize the performnce of system. This pper is focused on model of three-phse symmetric multi-level cscded inverter losses using switching function concept. The suggested model is bsed on the semiconductor chrcteristics. imultion results re shown the simplicity, convergence, nd relibility of the suggested model. ndex Terms--Three-Phse Asymmetric Multi-level scded nverter, witching Function, onduction Losses witching Losses.. NTROUTON NE EERAL YEAR, there is growing demnd for high voltge conversion systems cpble of providing high output voltge signls nd hving good spectrl performnce nd esy control. Exmples of such s systems re FAT devices, H light trnsmission, A drives, nd ctive filters [1, 2]. n ll the well-known multi-level inverter topologies, the number of power devices required depends on the output voltge level needed. However, incresing the number of power semiconductor switches lso increse inverter circuit, control complexity nd cost. To provide lrge number of output levels without incresing the number of inverters, symmetric multi-level inverters cn be used [2]. The bsic elements used in symmetric multi-level inverter re GBTs nd diodes. Becuse of economicl nd technicl importnce of power dissiption, the designers must consider nd minimize the losses of these devices. The losses of switching device cn be clssified in three groups: off-stte, conduction, nd switching losses. The lekge current during the off-stte is negligibly smll therefore the power losses during this stte cn be neglected. As result, only conduction nd switching losses must be exctly modeled [1, 3, 4, 5]. There re severl methods to model these losses. n the cse of modeling with Pspice nd ber, the inverter circuits cn be schemticlly expressed by using ctul power semiconductor device models nd pssive elements [1, 6]. These models hve shown number of problems, such s complexity, slow execution times, lrge mount of generted dt, nd convergence [1, 6]. To overcome the mentioned limittions, switching function concept hs been developed [6]. n this pper, for three-phse symmetric multi-level cscded inverter system the modeling methods of conduction nd switching losses bsed on switching function concept re presented.. AYMMETRAL MULT-LEEL NERTER Asymmetric multi-level inverters hve exctly the sme circuit topology s symmetric multi-level inverters. They differ only in the used cpcitor voltges. The properties of symmetric multi-level inverters re however quite different from those of their symmetric versions. Especilly the number of output-voltge levels cn be drmticlly incresed [2]. Figure 1 shows phse circuit digrm of n symmetric nine-level cscded inverter. A number of modultion strtegies re used in multi-level power conversion pplictions. They cn generlly be clssified into three ctegorize: Multi-step, pce ector PWM (PWM), nd rrier-bsed PWM (BPWM) [1]. This pper focuses on crrier-bsed PWM (BPWM) techniques which hve been extended for use in multi-level topologies by using multiple crriers. M. G. Hosseini Aghdm, nd. H. Fthi re with the eprtment of Electricl Engineering, Amirkbir University of Technology (Tehrn Polytechnic), No 424, Hfez Ave., Tehrn, rn (e-mil: Fig. 1. Phse circuit digrm of n symmetric nine-level cscded inverter.

2 Proceedings of the 5th WEA nt. onf. on Power ystems nd Electromgnetic omptibility, orfu, Greece, August 23-25, 2005 (pp ) The phse disposition (P) PWM method s one of the. FUNTONAL MOEL BPWM methods is bsed on comprison of sinusoidl n order to define switching functions, switching control reference wveform, with verticlly shifted crrier wveforms. strtegy must be selected. n this pper, the P PWM control The P PWM method uses N-1 crrier signls to generte the strtegy is selected s control strtegy (figure 2). Bsed on N-level inverter output voltge. As it cn be seen in figure 2, the P PWM control strtegy figure 4 shows the four the crrier signls hve the sme mplitude A c nd the sme switching functions (F frequency f c nd re in phse. The sinusoidl reference wve 1, F b2, F c1, F d2 ). hs frequency f r nd n mplitude A r. At ech instnt, the Figure 5 shows the functionl model of three-phse result of the comprison is decoded in order to generte the symmetric multi-level cscded inverter. This model consists correct switching function corresponding to given output of five functionl blocks bsed on the switching functions voltge level. F 1, F b2, F c1, nd F d2. ince there re no redundnt output sttes in two-cell As it cn be seen in figure 5, the phse nd line-to-line symmetric nine-level inverter, the reltion between the output voltges re obtined from block 1. Assuming blnced R-L nd the cell sttes is unique. As n exmple, the min- nd lod, the lod currents (, b, c ) re derived s rtio of the sub-inverter output voltges re shown in figure 3, for the phse voltges nd respective impednce s sme P PWM signls s in four-cell symmetric nine-level n n inverter. n Z R + jωl Fig. 2. Reference signl nd tringulr crriers of n symmetric nine-level cscded inverter with the P PWM control strtegy. bn cn Z bn Z b cn c bn R + jωl cn R + jωl Then, the switch currents ( 1, b2, c1, d2 ) for ech phse cn be clculted of the lod current with the corresponding switching functions F 1, F b2, F c1, nd F d2, tht is,. F 1 b2 c1 d 2 1. F b2. F c1. F n order to clculte the current rting of the power semiconductor switch ( 1 ), one needs the informtion for the pure switch current nd the pure diode current. The switch current ( 1 ) cn be determined s follows (3) where 1- nd 1- re the pure switch current nd the pure diode current of the switch 1, respectively. d 2 (1) (2) Fig. 3. ell voltges m, s nd output voltge of n symmetric nine-level cscded inverter. Fig. 4. witching functions with the P PWM control strtegy for phse A.

3 Proceedings of the 5th WEA nt. onf. on Power ystems nd Electromgnetic omptibility, orfu, Greece, August 23-25, 2005 (pp ) Fig. 5. The model of three-phse symmetric multi-level cscded inverter.. ONUTON AN WTHNG LOE The conduction losses re computed by multiplying the on-stte voltge by the on-stte current. The on-stte voltge is function of switch current, gte voltge of GBT, nd etc. Figure 6 () shows the collector current versus collectoremitter voltge of GBT (KM 400 GB 124 [7]). Figure 6 (b) shows the - chrcteristic of the diode. These curves cn be pproximted by the following equtions E A < < 20 A 7 A < < 50 A > 50 A < 7 A < 75 A > 75 A (4) (5) Fig. 6. () E- chrcteristic of GBT. (b) - chrcteristic of diode. (b) The most ccurte method of switching losses clcultion is the current nd voltge wveforms determintion during trnsitions. The point by point multipliction of these curves results in the ccurte dt [3]. The re under the power wveform is the switching energy t turn-on or turnoff trnsitions. Figure 7 () nd (b) show the switching energy versus switch current for GBT nd diode, respectively (KM 400 GB 124 [7]). These curves re pproximte by 2 E (6) on switch E (7) off switch 2 E (8) rec diode ()

4 Proceedings of the 5th WEA nt. onf. on Power ystems nd Electromgnetic omptibility, orfu, Greece, August 23-25, 2005 (pp ) () Bsed on the switching function signls F 1, F b2, F c1, nd F d2, the switch currents 1, b2, c1, nd d2 cn be successfully derived from pure current genertor block s shown in figure 9. Then using the eqution of (3), the switch currents re divided into the pure switch currents ( 1-, b2-, c1-, d2- ) nd the pure diode currents ( 1-, b2-, c1-, d2- ) s shown in figures 10 nd 11 for switches of b2, nd d2. Figures present the symmetric nine-level cscded inverter losses bsed on equtions (4)-(8). Figures (12) nd (14) (), (b) show the GBT nd diode conduction losses, respectively. Figures (13) nd (15) (), (b), (c) show the GBT turn-on switching losses, GBT turn-off switching losses, nd diode turn-off switching losses, respectively. The suggested model for conduction nd switching losses is very ccurte. Therefore, in order to select the proper power semiconductor devices for symmetric multi-level inverter, the suggested model is very relible nd sfe. Also, the simultion run-time mesured of the suggested model is 100 times fster thn the ordinry method or Pspice simultion model. Also, this developed model solves the problems such s convergence nd complexity of circuit nd control.. ONLUON Bsed on switching function concept, the losses of threephse symmetric nine-level cscded inverter hve been modeled with the using of MATLAB imulink. The suggested model is bsed on GBT nd diode chrcteristics modeling. Therefore, the clcultion of conduction nd switching losses by using this model is very ccurte. Also, n order to select the proper power semiconductor devices for symmetric multi-level inverter, the suggested model is very relible nd sfe. Also, this model is simple nd hs short run-time of simultion, too. Fig. 7. () GBT turn-on/turn-off energy. (b) iode turn-off energy. (b). MULATON REULT The proposed model for symmetric nine-level cscded inverter is simulted using MATLAB imulink. The simultion prmeters re s follows: upplying voltges: d1 50 nd d2 150, Lod: R5 Ω nd L20 mh, Reference signl frequency (f r ): 50 Hz, rrier signls frequency (f c ): 1.95 khz Modultion index (M A r /A c ) 0.8 nd GBT type: KM 400 GB 124 [7]. Figure 8 shows voltge nd current wveforms. Figures (8), b, nd (c) re phse voltge ( n ), line-to-line voltge ( b ), nd blnced lod currents (, b, c ), respectively.. REFERENE [1] M. G. Hosseini Aghdm, nd G. B. Ghrehpetin, "Modeling of witching nd onduction Losses in Three-Phse PWM Using witching Function oncept", Accepted for Publiction in EEE PowerTech'2005, t.petersburg, Russi, June 27-30, [2] J.. Mnguelle,. Mriethoz, M. eenstr, nd A. Rufer, "A Generlized esign Principle of Uniform tep Asymmetricl Multilevel onverter for High Power onversion", EPE 2001, Grz, Austri. [3] T. J. Kim,. W. Kong, Y. H. Lee, nd.. Hyun, "The Anlysis of onduction nd witching Losses in Multilevel-nverter ystem", Power Electronics pecilists onference, PE EEE 32nd Annul, ol.3 pp [4] K. Berringer, J. Mrvin, nd P. Perruchoud, "emiconductor Power Losses in A nverters", in onf. Rec. EEE-A Annu. Meeting, 1995, pp [5] F. snells, "Losses in PWM nverters Using GBTs", Proc. EEE- Elect. Power Applictions, ol. 144, No. 5, ept. 1994, pp [6] B. K. Lee, nd M. Ehsni, "A implified Functionl imultion Model for Three-Phse oltge-ource nverter Using witching Function oncept", EEE Trns. ndustril Electronics, ol. 48, No. 2, April 2001, pp [7] KM 400 GB 124.

5 Proceedings of the 5th WEA nt. onf. on Power ystems nd Electromgnetic omptibility, orfu, Greece, August 23-25, 2005 (pp ) Fig. 8. oltge nd current wveforms of symmetric nine-level cscded inverter with the P PWM control strtegy. () Phse voltge ( n). (b) Line-to-Line voltge ( b). (c) Lod currents (, b, c). Fig. 10. urrent of switch b2 ( b2), pure switch current of switch b2 ( b2), nd pure diode current of switch b2 ( b2). Fig. 9. urrent wveforms of switches 1, b2, c1, nd d2. Fig. 11. urrent of switch d2 ( d2), pure switch current of switch d2 ( d2), nd pure diode current of switch b2 ( d2).

6 Proceedings of the 5th WEA nt. onf. on Power ystems nd Electromgnetic omptibility, orfu, Greece, August 23-25, 2005 (pp ) Fig. 12. onduction losses of switch b2. () GBT conduction losses [mj]. (b) iode conduction losses [mj]. Fig. 14. onduction losses of switch d2. () GBT conduction losses [mj]. (b) iode conduction losses [mj]. Fig. 13. witching losses of switch b2. () GBT turn-on switching losses [mj]. (b) GBT turn-off switching losses [mj]. (c) iode turn-off switching losses [mj]. Fig. 15. witching losses of switch d2. () GBT turn-on switching losses [mj]. (b) GBT turn-off switching losses [mj]. (c) iode turn-off switching losses [mj].

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