DSP-based PLL-controlled khz 20 kw highfrequency induction heating system for surface hardening and welding applications

Transcription

1 DSP-sed PLL-controlled 5 1 khz 2 kw highfrequency induction heting system for surfce hrdening nd welding pplictions N.S. Byındır, O. K.ukrer nd M. Ykup Astrct: A digitl signl processor (DSP)-sed phselocked loop (PLL)-controlled highfrequency induction heting system is descried. The rectifier nd insulted gte ipolr trnsistor (IGBT) inverter re controlled y TMS32F24 DSP system, which hs the hrdwre feture of providing ded-nd dely independent of the frequency of opertion. This feture, together with the high speed of the DSP, llows the use of zero current resonnt switching t high power fctor for frequencies up to 1 khz. Resonnt opertion of the inverter is mintined y simple digitl PLL scheme implemented on the DSP. The frequency converter enles sfe opertion t ll lod conditions with digitl overcurrent, overvoltge nd overtemperture protection fetures. The costeffective system descried is operted successfully t outputs up to 19.8 kw t 72 khz nd 5 V. 1 Introduction High-frequency induction heting furnces re widely used in pplictions such s surfce hrdening, welding, metl to plstic or metl to glss onding nd curing. The higher efficiency, very short heting times nd locl heting cpilities of induction heters hve mde them superior to other heting devices. With the ltest dvnces in power semiconductor switching devices nd microprocessors, high-frequency induction heting power supplies re now more relile nd cost-effective nd hve higher performnces [1 4]. In [4] pulse mplitude modulted voltge source, series lod resonnt inverter hs een developed using high-power sttic induction trnsistors (SITs), which opertes t lod-dptive tuned operting frequency tht is slightly higher thn the series resonnt frequency in order to chieve zero-voltge soft-switching commuttion. A phselocked loop integrted circuit (PLL-IC) is used to provide lod resonnt opertion sed on the phselocked loop principle. Due to the difference etween the switching frequency nd the lod resonnt frequency, the power fctor hs een degrded y 5% nd oscilltions re oserved t the switching instnts. Moreover with this method the dely etween the inverter output voltge nd current wveforms cnnot e mintined t the sme level t ll frequencies due to the chnge in component chrcteristics with frequency. In [1], hlf-ridge inverter circuit with series prllel resonnce is descried which does not use n impednce mtching trnsformer. Series nd prllel compensting cpcitors re used to reduce the rective r IEE, 23 IEE Proceedings online no doi:1.149/ip-ep:2396 Pper first received 29th April 22 nd in revised form 25th Septemer 22 N.S. Byındır nd O. K.ukrer re with the Deprtment of Electricl nd Electronic Engineering, Estern Mediterrnen University, G. Mgos, Mersin 1, Turkey M. Ykup is with the Technology Development Centre, Estern Mediterrnen University, G. Mgos, Mersin 1, Turkey loding of the workpiece nd lso to increse the lod current with respect to the inverter current. However, the method is vlid for coil inductnce vlues less thn twice the totl series stry inductnce in the circuit. Another disdvntge is the use of n extr cpcitor, which is expensive t the frequencies in question. A comprison of series nd prllel inverter systems [5] hs reveled tht the voltge source series resonnt inverter offers etter overll performnce thn the prllel resonnt counterprt with respect to converter utilistion. Considering the results of this comprison, the series resonnt inverter topology hs een dopted in this project. In this pper digitl signl processor (DSP)-sed PLL control scheme is presented in which the phse difference etween the inverter voltge nd current is minimised nd mde independent of the operting frequency. The hrdwre ded-nd feture of the DSP is used, in conjunction with softwre-sed PLL control, to chieve precise zerocurrent switching opertion so tht the di/dt stresses on the insulted gte ipolr trnsistors (IGBTs) re minimised nd switching occurs with negligile oscilltions. The DSPsed digitl control pproch enles esy implementtion of vrious monitoring nd protection functions, in ddition to the uilt-in ded-nd feture. Furthermore, digitl implementtion of the PLL scheme is more relile thn n nlogue implementtion, where chnging component chrcteristics my degrde performnce in time. Moreover, in nlogue implementtions of PLL control the ded-nd time my vry with operting frequency, which then degrdes the power fctor. The design nd constructionl fetures of the whole system re presented in this pper. Experimentl work hs een crried out on the induction heting system to mesure the opertionl performnce under vrious loding conditions. Experimentl results indicte tht the system opertes successfully with power fctor very close to unity. A simultion model hs een developed using Simulink, which hs een used to nlyse nd design the PLL control system. A mthemticl model of the system hs lso een developed in discrete time, with which the stility of the system cn e ssessed. IEE Proc.-Electr. Power Appl. 1

2 2 System description The generl lyout of the frequency converter is shown in Fig. 1, where it my e seen tht the output power is controlled y three-phse controlled rectifier nd tht the inverter is of the voltge-fed lod resonnt type. High-speed IGBTs with fst nti-prllel diodes re used in the inverter. RC snuers re used to reduce the dv/dt stresses on the IGBTs. A high-frequency impednce mtching trnsformer with turns rtio of 5/1 hs een designed nd constructed with n morphous core on which the primry nd secondry coils re wound using Litz wire, nd this is used to isolte nd mtch the impednces of the converter nd the induction heting coil. The induction heting coil nd the impednce mtching trnsformer re wter cooled. A high-frequency compensting cpcitor of vlue C s ¼ 1 mf (5 khz, 6 V) is connected in series with the coil (L s ). The inverter output voltge nd the cpcitor voltge re mesured y mens of high-frequency voltge trnsducers to provide the necessry inputs to the DSP for PLL control. The inverter nd coil currents re lso mesured to trck the lod resonnt opertion nd lso to mesure the efficiency of the converter nd of the impednce mtching trnsformer. L F + X f Fig. 2 Fig. 3 DSP TMS32F24 phse detection circuit inverter impednce mtching trnsformer optoisoltor optoisoltor zerocrossing circuits Block digrm of PLL-sed control system XOR Phse detection circuit initite ded-nd routine R f resonnt lod (cpcitor+ inductor) C f Xf T 1 T 3 C s strt A/D converter 3-ph supply C F V dc L s (R l ) T 4 T 2 wit for end of conversion 3-ph controlled rectifier - DSP sed PLL control system voltge trnsducer voltge trnsducer cquire phse error [e D (k)] Fig. 1 Generl lyout of high frequency induction heting system clculte new inverter period T c (k+1) = T c (k)+k cd.e D (k+1) 3 DSP-sed PLL control system 3.1 Control system description A simple DSP-sed PLL control lgorithm hs een developed in which the ded-nd dely is provided y the specil hrdwre feture of the TMS32F24 DSP system. The digitl implementtion of PLL mintins resonnt opertion over wide rnge of frequencies from 5 to 1 khz. A lock digrm of the PLL system is shown in Fig. 2. The cpcitor voltge nd the inverter output voltge re mesured with high-frequency voltge trnsducers with negligile dely nd the zero crossings of these voltges re detected nd compred in n XOR gte, s shown in Fig 3. The output of the XOR gte is filtered to yield DC voltge (x f ) proportionl to the phse difference etween the inverter nd cpcitor voltges. This voltge is isolted opticlly nd pplied to the nlogue input of the DSP, where digitl implementtion of the PLL scheme is then relised. The flowchrt of the PLL control lgorithm is shown in Fig. 4. The voltge input to the DSP, which is proportionl to the phse difference etween the inverter output nd the cpcitor voltges, is compred with vlue corresponding to 9 degrees nd the switching frequency is djusted so tht this difference is mde zero. When this condition is chieved, the cpcitor nd the inverter voltges Fig. 4 T c (k+1) < T min no T c (k+1) > T mx no updte counter period in ded-nd PLL control lgorithm T c (k+1) = Tmin T c (k+1) = T mx re in qudrture, which ensures tht the inverter voltge nd current re in phse. The pulse width modulted (PWM) outputs of the DSP re used to generte switching pulses for the inverter IGBTs. The PWM periods determined y the PLL lgorithm re loded into the timer control register T1CON, which then strts genertion of the PWM yes yes 2 IEE Proc.-Electr. Power Appl.

3 switching pulses. The ded-nd dely etween the switching instnts of the IGBTs on the sme leg of the inverter is provided y the ded-nd control register DBTCON, which is set t.8 ms. This dely is djusted y the specil hrdwre feture of the DSP, nd is independent of the processing delys. This feture of the DSP mintins constnt dely t ll frequencies, which is not possile in nlogue circuit implementtions of PLL control due to the vrition of component chrcteristics with frequency (prticulrly in the high-frequency rnge). The DSP opertes t speed of 2 MIPS, which mkes it possile to control the system up to 1 khz. During experimenttion, lower frequency limit of 5 khz nd n upper frequency limit of 1 khz were set on the control system so tht the operting frequency could never exceed these limits ccidentlly. The switching signls re isolted nd mplified efore they re pplied to the gtes of the IGBTs using signl conditioning circuit. 3.2 Mthemticl model An pproximte discrete-time model of the system ws found to e useful in designing the control system. Referring to Fig. 4, the PLL control is implemented in discrete-time y the following eqution: T ðk þ 1Þ¼TðkÞþK c eðk þ 1Þ ð1þ which corresponds to integrl ction. In (1) T is the inverter voltge period (represented y T c in digitl form in Fig. 4), K c is the integrl gin (represented y K cd )nde is the error in phse difference (represented y e D )defineds eðkþ¼x f ðkþ 1 2 ð2þ where x f is the verge vlue of the normlised LP filter output (Fig. 5). 1 XOR output Fig. 5 Wveforms for PLL opertion u f = x fss Normlistion here refers to scling such tht the mximum is unity (corresponding to 1% duty rtio of the XOR output). Note tht the period of the VCO output (T) is updted insted of its frequency. This is found to e more convenient since the inverter control progrm (ded nd) requires period informtion directly. Now, it is cler tht x f cn e expressed in the stedy stte in terms of the phse difference f s However, in trnsient opertion x f should e relted to u f y the differentil eqution dx f dt ¼ 1 t f x f þ 1 t f u f u f ¼ f p ð4þ where t f ¼ R f C f is the time constnt of the filter. Note tht in (4) u f is function of the frequency of the inverter voltge (or its period) through the phse difference f. Considering the stedy stte opertion of the resonnt lod of the inverter, the following reltionship cn e otined etween f nd T: ( fðt Þ¼tn 1 2p T R ) lc s ð5þ 1 ð 2p o T Þ2 p where o ¼ 1= ffiffiffiffiffiffiffiffiffi L s C s ; L s is the inductnce of the heting coil nd R l is its equivlent resistnce. It is ssumed tht the reltionship (5) is pproximtely vlid during trnsient opertion in which the period T chnges slowly. Furthermore, (5) is otined y ssuming tht the inverter output voltge is purely sinusoidl. Eqution (4) cn e discretised s follows: f½t ðkþš x f ðk þ 1Þ¼x f ðkþþ ð6þ p where ¼ e T s=t f, ¼ (1 ), nd T s is the control smpling time. Using (1), (2) nd (6) the closed-loop system eqution is otined s T ðk þ 1Þ¼TðkÞþK c x f ðkþþ f½t ðkþš 1 p 2 ð7þ Equtions (6) nd (7) re non-liner, since f is non-liner function of T(k). These equtions cn e linerised esily y linerising (5) round the operting point, where the inverter frequency is equl to the resonnt frequency of the lod, to give (see Appendix, Section 7) fðt Þ p 2 1 ðt T Þ ð8þ pr l C s where T is the inverter period t the operting point. With the following definitions of perturtion vriles: Dx f ¼x f 1 2 ð9þ DT ¼T T the linerised closed-loop equtions of the system ecome (see Appendix, Section 7) yðk þ 1Þ¼A c yðkþ ð1þ In (1) y is the column vector y ¼ [Dx f DT] T nd 2 3 A c ¼ 4 1 p 2 t r 5 K c 1 ð1 ÞK c p 2 t r where t r ¼ R l C s. Applying Jury s stility test [6] to (1), the following rnge of gin for stility is otined: ok c o 1 þ 2p 2 R l C s ð11þ 1 4 System modelling nd simultion x f ;ss ¼ f p ¼ u f where u f is the verge vlue of the LP filter input. ð3þ At the design stge of the induction heting system, simultion model of the converter nd the lod ws developed using the SIMULINK pckge to estimte the turns rtio of the impednce mtching trnsformer, the IEE Proc.-Electr. Power Appl. 3

4 compensting cpcitor vlue nd the IGBT rtings, s well s the controller gin. The simultion model is shown in Fig. 6. The system prmeters re L sp ¼ 122 mh, C sp ¼.4 mf, R lp ¼ 11.1 O (referred to the primry side of the impednce mtching trnsformer), T s ¼ 2 ms, nd t f ¼ 68 ms. Note tht this model does not simulte the PLL control lgorithm s in the ctul prcticl implementtion, with the period T s the output of the VCO (softwre version). Insted, the frequency of the VCO output in this model is controlled y the VCO input. However, the ehviours resulting from the two pproches re expected to e similr for sufficiently smll devitions round the operting point. An equivlent gin of K c ¼ 5. ms hs een used in the simultions, which is the vlue tht corresponds to the gin used in the experimentl system. Note tht the theoreticl limit for the gin from (11) is K c o9.8 ms. 1 Vi. int. gin Ls hold T z-1 discrete-time integrtor e =xf-1/ constnt clock in1 out1 LPF 15 s sum prod1 int1 prod2 rte lim1 tt time rte limiter VCO+INV rely2 XOR (ZCD) XOR xf norm. filter volt. 1/Cs rte lim2 v_inv inv.voltge Vi Vc lod rely1(zcd) cp. voltge trnsf. rtio v_cp 1/5 int2 R 1 1 s -K- s i_inv inv. current Fig. 6 SIMULINK model for PLL-controlled induction heting system Complete system Resonnt lod model 1 Vc Referring to Fig. 6 the cpcitor nd inverter voltges re pssed through relys, which represent zero-crossing detectors (ZCD), the outputs of which re pplied to the inputs of the XOR. The lowpss filter (LPF) output is compred with the reference vlue of.5 nd the error is smpled y first-order smple-nd-hold, which represents the nlogue-to-digitl conversion opertion. The discrete-time integrtor implements the integrl controller. The VCO output in this simultion is the squre wve inverter output voltge, which is pplied to the resonnt lod model. The rte limiter djusts the rte of chnge of the inverter voltge during switches to prcticl vlues. Fig. 7 shows smple simultion results for stedy-stte nd trnsient opertion of the system. In the trnsient test cse, it is ssumed tht there re rmp chnges in the inductnce nd the resistnce of the coil from 9 mh to x f vi, V;, V, V; i c, A mh, nd from 1 O to 8 O, respectively (Section 4). This emultes trnsient test on the ctul system in which the workpiece is pulled out y lmost 2%. In Fig. 7c it cn e oserved tht the PLL control strtegy keeps the coil current in phse with the inverter voltge under ll operting conditions. 5 Experimentl results time, s c strt of trnsient Fig. 7 Simultion results for induction heting system Inverter voltge ( ) nd current ( ) Inverter voltge ( ) nd cpcitor voltge ( ) (referred to inverter side) c Trnsient response of filter output (x f ) for 2% sudden reduction in the lod L nd R An experimentl prototype of the proposed system hs een set up using Fuji IPM inverter module (7MBP 1RA- 12), with short-circuit, overcurrent, overtemperture nd undervoltge protection logic. The system hs een operted t n output power of 19.8 kw, n operting frequency of 72 khz nd n input voltge of 5 V. The inverter output voltge nd current, nd the cpcitor voltge re presented in Figs 8 nd 9. In Fig. 8c IGBT collector emitter voltges hve een mesured t 4 V, which is the mximum rnge of the oscilloscope. The output voltges of the PLL circuit (XOR nd LP filter outputs) were lso mesured nd re presented in Fig. 1. A trnsient test hs een performed t lower power of IEE Proc.-Electr. Power Appl.

5 voltge: 2 V/div, current: 2 A/div, time: 2.5 µs/div (i) voltge: 2 V/div, current: 2 A/div, time: 1 µs/div (ii) voltge: 2 V/div, time: 2.5 µs/div Fig. 8 Experimentl results for 19.8 kw output (i) Inverter voltge ( )ndcurrent( ). (ii) Inverter voltge nd current, reduced timescle (1 ms/div) Inverter voltge ( ) nd cpcitor voltge ( ) c Collector emitter voltges of IGBTs on the sme inverter leg voltge: 5 V/div; time: 5 ns/div c 3.3 kw with different coil, where the workpiece ws suddenly prtilly pulled out of the coil (y out 2%). The trnsient chnge in the filtered output shows tht the PLL control system rings the system ck to unity power fctor opertion in out 5 ms. It is difficult to mke comprison with the simultion result under similr conditions, since the exct conditions in the test cnnot e modelled in the simultion. However, the response time in the simultion is round 3 ms, which roughly grees with the prcticl result. Note tht in the simultion result the trnsient strts t t ¼ 25ms nd comes to n end t t ¼ 28 ms. Comprison of stedy-stte experimentl nd IEE Proc.-Electr. Power Appl. 5

6 ZCD output XOR output voltge: 2 V/div, time: 2.5 µs/div voltge: 2 V/div, current: 2 A/div, time: 2.5 µs/div Fig. 9 Inverter voltge nd current for ded-nd time of 1.2 ms simultion results revels tht the system design sed on the simultion model closely follows the predicted ehviour. Referring to Fig. 8, (i), it cn e oserved tht the inverter switches t exctly zero current which ensures unity power fctor. This lso mens tht switching losses re minimised s result of zero current switching. Hence, in efficiency clcultions the switching losses cn e neglected nd n estimte of the overll efficiency of the inverter sed on conduction losses only cn e otined, using Z ¼ 1 2V CE;st 1% V dc ð12þ s 98.9%. In (12) V CE,st represents the sturtion voltge of the IGBTs. Fig. 8, (ii) displys the inverter current nd voltge on much smller time scle nd shows tht the current nd voltge wveforms re exctly in phse. It my lso e noted tht the inverter switches in 1.2 ms. Furthermore, the inverter voltge exhiits no oscilltions during switching intervls. This is the result of zero-current switching nd the very smll lekge inductnce of the impednce mtching trnsformer. The IGBT collector emitter voltges (for IGBTs on the sme inverter leg) on nrrow time sclereshowninfig.8c, where it is lso cler tht the IGBTs switch in out.8 ms, which is consistent with Fig. 8. Note tht the IGBTs on the sme leg switch lmost simultneously without giving rise to shoot-through, which is gin result of zero-current switching. Fig. 8 shows tht the inverter nd cpcitor voltges re phseshifted y 91, which demonstrtes tht the PLL scheme opertes successfully. The effect of incresing the ded-nd durtion on the inverter output voltge is illustrted in Fig. 9, where the ded-nd is djusted to 1.2 ms. The oscilltions in the voltge during the switching intervls re the result of the feedck diodes trying to turn on s the lod current reverses direction when the outgoing trnsistors re turned off. During this trnsition period, the incoming trnsistors remin off due to the incresed ded-nd. It is evident tht such oscilltions give rise to extr losses. Therefore, it cn e concluded tht the dednd durtion is very criticl in zero-current switching pplictions. 6 Conclusions voltge: 1 mv/div, time: 2.5 µs/div voltge: 1 mv/div, time: 5 ms/div c Fig. 1 XOR output (lower trce) Lowpss filter output in stedy-stte c Lowpss filter output for trnsient cse strt of trnsient A DSP-sed PLL-controlled induction heting system hs een descried in which zero-current switching of the IGBTs nd opertion t unity power fctor with negligile oscilltions on the inverter voltge re chieved through softwre-sed PLL control scheme using DSP which hs hrdwre ded-nd feture. The proposed DSP-sed 6 IEE Proc.-Electr. Power Appl.

7 PLL controller is more flexile nd precise thn conventionl nlogue PLL controllers, llowing esy modifiction of control prmeters (such s ded-nd time nd controller gin) vi softwre, wheres in nlogue implementtions, which require hrdwre chnges, these modifictions would e fr more difficult. The ded-nd dely cn e kept constnt t ny predefined vlue, independent of the operting frequency, using the uilt-in ded-nd circuitry. Experimentl results revel tht the PLL control scheme opertes precisely s designed nd no phse dely ws oserved etween the inverter output voltge nd current. Trnsient tests on the system hve shown tht fter disturnce the PLL control system rings the system ck to unity power fctor opertion within time of 5 ms. System prmeters such s the turns rtio of the impednce mtching trnsformer, compensting cpcitor vlue nd IGBT rtings, s well s controller gin were otined from simultion model. Agreement etween predicted simultion results nd experimentl results hve vlidted the design. The use of DSP-sed control system hs the dded dvntge tht different control schemes requiring different heting periods nd different dpttions of the induction heting system cn e implemented with modifictions to the softwre lone nd no chnges to the hrdwre. 7 Acknowledgments The uthors wish to thnk the Estern Mediterrnen University Technology Development Centre (DAU-TEK- MER) for their finncil support. 8 References 1 KAMLI, M., YAMAMOTO, S., nd ABE, M.: A 5-15 khz hlfridge inverter for induction heting pplictions, IEEE Trns. Ind. Electron., 1996, 43, (1), pp WANG, S., IZAKI, K., HIROTA, I., YAMASHITA, H., OMORI, H., nd NAKAOKA, M.: Induction-heted cooking pplince using new qusi-resonnt ZVS-PWM inverter with power fctor correction, IEEE Trns. Ind. Appl., 1998, 34, (4), pp CALLEJA, H., nd ORDONEZ, R.: Improved induction-heting inverter with power fctor correction. 3th Annul IEEE Power electronics specilists Conference, PESC 99 4 OKUNO, A., KAWANO, H., SUN, J., KUROKAWA, M., KOJINA, A., nd NAKAOKA., M.: Fesile development of softswitched SIT inverter with lod-dptive frequency-trcking control scheme for induction heting, IEEE Trns. Ind. Appl., 1998, 34,(4), pp DAWSON, F.P., nd JAIN, P.: A comprison of lod commutted inverter systems for induction heting nd melting pplictions, IEEE Trns. Power Electron., 1991, 6, (3), pp KUO, B.C.: Digitl Control Systems, 1st Edn. (Holt-Sunders Interntionl Editions, Tokyo, 1981) 9 Appendix The phse difference f cn e linerised y mens of the following truncted Tylor series: fðt Þ fðt Þþ df ðt T Þ ð13þ dt T ¼T where T ¼ 2p/o. The derivtive cn e evluted from (5) s df dt ¼ ðt 2 þ T 2Þ ðt 2 T 2 ð14þ Þþ2 T 2 where ¼ 2pR l C s. When evluted t T ¼ T,thisderivtive gives df ¼ 2 dt T ¼T ¼ 1 ð15þ pr l C s By lso noting tht f(t ) ¼ p/2, (8) is otined. Sustituting (8) nd (9) into (6) gives: Dx f ðk þ 1Þþ 1 2 ¼ Dx f ðkþþ 1 2 þ p p 2 1 DT ðkþ pr l C s Simplifiction using the fct tht ¼ 1 then yields ð1 Þ Dx f ðk þ 1Þ ¼Dx f ðkþ p 2 DT ðkþ ð16þ R l C s Similrly, sustituting (8) nd (9) into (7) gives DT ðk þ 1Þ¼DTðkÞþK c Dx f ðkþþ 1 2 ð1 Þ p þ p 2 1 DT ðkþ 1 pr l C s 2 which simplifies to DT ðk þ 1Þ¼ðK c ÞDx f ðkþ þ 1 ð1 ÞK c p 2 R l C s DT ðkþ ð17þ Equtions (16) nd (17) cn then e written in mtrix form s in (1). IEE Proc.-Electr. Power Appl. 7