Timing Macro-modeling of IP Blocks with Crosstalk

Transcription

1 Timing Mcro-modeling of IP Blocks with Crosstlk Ruiming Chen nd Hi Zhou Electricl nd Computer Engineering Northwestern Universit Evnston, IL Astrct With the increse of design compleities nd the decrese of miniml feture sizes, IP reuse is ecoming common prctice while crosstlk is ecoming criticl issue tht must e considered. This pper presents two mcro-models for specifing the timing ehviors of comintionl hrd IP locks with crosstlk effects. The gr-o model keeps coupling grph nd lists the conditions on reltive input rrivl time comintions for couplings not to tke effect. The lck-o model stores the output response windows for sic set of reltive input rrivl time comintions, nd computes the output rrivl time for n given input rrivl time comintion through the union of some comintions in the sic set. Both mcro-models re conservtive, nd cn gretl reduce the pessimism eisting in the conventionl pin-to-pin model. This is the first work to del with timing mcromodeling of comintionl hrd IP locks with the considertion of crosstlk effects. 1 Introduction With the progress of deep su-micron technologies, shrinking geometries hve led to reduction in self-cpcitnce of wires. Menwhile coupling cpcitnces hve incresed s wires hve lrger spect rtio nd re rought closer together. For present d processes, the coupling cpcitnce cn e s lrge s the sum of the re cpcitnce nd the fringing cpcitnce, nd the trends indicte tht the role of coupling cpcitnce will e even more dominnt in the future s feture sizes shrink. This mkes crosstlk mjor prolem in IC design. Crosstlk introduces noise etween djcent wires, nd even lters the functions of circuits. If n ggressor nd victim switch simultneousl on the sme direction, the victim will speed up. Likewise, if n ggressor nd victim switch on the opposite directions, the victim will slow down. With the growing compleit of VLSI sstems, the intellectul propert (IP) reuse is ecoming common prctice. There re previous reserches deling with the timing mcromodeling of IP locks, nd ll of them re sed on the concept of pth del [1, 2, 3, 4, 5, 6]. The simplest of such models is the pin-to-pin del model used to chrcterize stndrd cells nd other comple comintionl circuits. For emple, given simple comintionl circuit shown in Figure 1(), its pin-to-pin del model is shown in Figure 1(). The numers shown on ech rc give the miniml nd miml dels from one pin to nother. In this cse, if () nd A() re used to represent the erliest nd ltest rrivl time of signl, respectivel, we hve () = () + 3; A() = A() + 5; () = min(()+2, (c)+3); A() = m(a()+4, A(c)+4). To model sequentil circuit with memor elements, the pinto-pin model is etended to include timing constrints from clock pin to n input pin (to model setup nd hold conditions) nd del rcs from clock pin to n output pin (to model the ltch output to circuit output del) [1]. Functionlit m lso e used to reduce the pessimism in these models [5, 6]. This work ws supported NSF under CCR c (3,5) (2,4) c (3,4) c () () (c) Figure 1: () A simple circuit; () Its pin-to-pin mcromodel; (c) Coupling destros pth del concept. Unfortuntel, coupling totll destros the pth del concept. For emple, s shown in Figure 1(c), if the wires nd re coupled to ech other, the rrivl time on nd cnnot e decided through pths from the inputs. Insted, the reltive switching time of,, c is importnt in deciding the rrivl time on nd. Suppose when () = A() = 0, () = A() = 1, (c) = A(c) = 0, we hve the miml del vrition on the coupled signls nd such tht ((), A()) = (2, 10), ((), A()) = (1, 11). Then for n t such tht () = A() = t, () = A() = t + 1, (c) = A(c) = t, the del vrition will lso e miml nd we hve ((), A()) = (t + 2, t + 10), ((), A()) = (t + 1, t + 11). This mens tht the dels etween pins re influenced the reltive rrivl time of inputs. So the conventionl pinto-pin mcro-model for IP locks is pessimistic. Mn reserches hve een done on timing nlsis or modeling considering crosstlk [7, 8, 9, 10, 11, 12, 13, 14, 15, 16]. Most of them consider how to compute the dels of set of coupled nets given their input time, so the resulting dels re ccurte onl for specific input rrivl time comintion. Sski et l. [17, 18] proposed reltive window methods, nd Agrwl et l. [19] proposed n nlticl method, to depict the del chnge curves for noise-wre sttic timing nlsis (STA). However, the cn onl hndle the simple cses with one victim nd multiple ggressors. So when considering crosstlk effects, ll the current mcromodeling methods cnnot generte n ccurte model for comple IP lock. We propose two input-dependent models for specifing the timing ehviors of comple IP locks. To the est of our knowledge, it is the first work deling with timing chrcteriztion of IP locks with crosstlk effects. The rest of the pper is orgnized s follows. Section 2 shows the requirements of vile mcro-model. Section 3 presents the etrction nd ppliction of SIMPMODEL. This fst gr-o mcro-model computes nd utilizes the conditions on the reltive input rrivl time comintions for couplings not to tke effect. Section 4 present the etrction nd ppliction of UNIONMODEL. This ccurte lck-o model stores the output response windows for sic set of reltive input rrivl time comintions, nd computes the

2 output rrivl time for n given input rrivl time comintion through the union of some stored output response comintions. Section 5 reports the eperimentl results on the proposed mcro-models nd their comprison with pinto-pin model nd STA results. Finll, the conclusion nd future work re discussed in Section 6. 2 Mcro-model requirements A vile timing mcro-model of comintionl hrd IP lock should stisf the following requirements: Hiding of implementtion detils. It is requirement for protecting intellectul propert. Model ccurc. Given n input rrivl time comintion, the rrivl time window of n primr output generted the timing mcro-model should e s close s possile to the corresponding ctul output rrivl time window. Conservtive modeling. Given n input rrivl time comintion, the ctul time window of n primr output should e in the rnge of the corresponding output time window generted the timing mcro-model. When crosstlk effects re considered, the del etween pins depends not onl on the structurl detil of IP locks, ut lso on the reltive rrivl time of primr inputs, or input ptterns. Definition 1 (input/output pttern) An input/output pttern of n IP lock is n rrivl time window vector where ech element is n rrivl time window on one primr input/output of the IP lock. So n input-dependent model m gretl improve the ccurc. As is sid efore, when considering crosstlk effects, ll the current mcro-modeling methods cnnot generte n ccurte model for comple IP lock. We introduce two input-dependent mcro-models tht stisf ll the requirements. 3 SIMPMODEL 3.1 Del model The conventionl pin-to-pin model ssumed tht the coupling effects were lws ctive, which led to ver pessimistic estimtion. In order to get more ccurte model, we compute nd utilize the conditions under which the couplings do not tke effect. Hssoun [20] presented dnmicll ounded del model to represent the del of net. We use modified dnmicll ounded del model. A directed grph G = (V, E, C) represents the IP lock. Ech verte in V represents primr input, primr output, gte, or net. A connection connecting inputs, outputs, gtes or nets is represented one edge in E. Let set C v e the set of ggressor nodes connected vi coupling cpcitor to victim node v, W v e the timing window of node v, nd C = v V {C v} Ech node v hs dnmicll ounded del model consisting of fied del rnge [δ v, v], nd, for ech coupling cpcitor ttched to v from n ggressor node, predicte γ v, indicting whether the coupling tkes effect. If the coupling does not tke effect, the miniml del should e incresed δ v,, nd the miml del should e decresed v,. So the miniml del of node v is δ v + C v γ v,δ v,, nd the miml del of node v is v C v γ v, v,, where γ v, is defined s { 0 if Wv overlps with W γ v, =, 1 otherwise. 3.2 SIMPMODEL detils First, the SIMPMODEL reduces the originl comple directed cclic grph (DAG) G to DAG clled coupling grph tht contins onl the input pins, the output pins, nd the nodes with coupling. Ech edge in this coupling grph represents tht the end node is rechle from the strt node through pth without etr coupling nodes, nd the weights of ech edge represent the miniml nd the miml dels from the strt node to the end node. This tsk cn e ccurtel done n conventionl STA. The remining tsk is to determine the vlue of γ v,. When considering crosstlk effects, the determintion of γ v, ecomes chicken-nd-egg prolem, nd the conventionl w is to use itertion methods. With the coupling grph, the mcro-model users cn use STA tools to get the output pttern directl. Since the coupling reltions re often comple, this kind of mcro-model leves much work to users. Insted, we design fst conservtive pproimtion method to determine the vlue of γ v,. It is ovious tht the vlue of γ v, is determined the reltions mong the time windows of primr inputs tht cn rech v or. Let set I v e the set of primr inputs tht cn rech node v, v i e the ith input tht cn rech node v, vi nd w vi e the miniml nd miml dels from input v i to v respectivel, [ vi, vi ] is the rrivl time window of input v i. Then we hve these two rules: nd min v i I v ( vi + vi ) > m j I ( j + w j ) γ v, = 1, m ( vi + w vi ) < min ( j + j ) γ v, = 1. v i I v j I After getting the coupling grph, SIMPMODEL ssumes tht γ v, = 0 for ll the coupling nodes. Then do PERT trversl on the coupling grph to clculte the miniml nd miml dels from ech primr input to ech node, nd put the results into list L. Till now, model composed coupling grph nd result list is etrcted successfull. Then during the model ppliction, once the input pttern is given, we cn check the two rules to determine the vlue of ech γ v, ccording to the informtion in the list L. Once the del of ech node is determined, we trverse the coupling grph to get the desired output pttern. We ssume tht γ v, = 0 for ll the coupling nodes, so fter checking these two rules, if γ v, = 0 for pir of coupling nodes v nd, it me equl to 1 in relit, ut if γ v, = 1 for pir of coupling nodes v nd, it must e 1 in relit, so SIMPMODEL lws chieves conservtive output pttern for given input pttern. 4 UNIONMODEL SIMPMODEL shows method to fst estimte the output pttern, while its ccurc is scrificed to get high speed, nd SIMPMODEL is gr-o model, tht is, it unveils prt of the implementtion detils of IP locks. However, the ccurc of the model nd the hiding of implementtion

3 detils re strongl required in mn situtions. The following UNIONMODEL stisfies these two requirements, tht is, UNIONMODEL is n ccurte lck-o timing mcromodel. Let A i represent the time window of pttern A corresponding to pin i. First, we introduce some definitions. Definition 2 (djcent windows) If two windows nd overlp with ech other t onl one common point, then nd re djcent, denoted s. Definition 3 (cominle input ptterns) If the windows corresponding to the sme pin in two ptterns A nd B re djcent, nd the other pirs of windows corresponding to the sme pins re the sme respectivel, then A nd B re cominle, denoted s A B Definition 4 (suwindow) If window is contined in window, then is suwindow of, denoted s. Definition 5 (supttern) Let A nd B e two ptterns. If for n i, A i B i, then A is supttern of B, denoted s A B. Definition 6 (overlpped ptterns) If ech window in pttern A overlps with the corresponding window in pttern B, then A nd B re overlpped ptterns, denoted s A B φ. Definition 7 (union of ptterns) The union of two overlpped ptterns A nd B, denoted s A B, is pttern where ech window is the union of the two corresponding windows in A nd B. For emple, in Figure 2, time windows,, c, d re [0, 10], [10, 20], [0, 10] nd [10, 20], respectivel. Input ptterns A{, c} nd B{, c} re cominle input ptterns tht cn e united into n input pttern {[0, 20], c}. But input pttern {, c} nd {, d} re not cominle, ecuse nd re djcent, nd c nd d re djcent ut not the sme. Input 1: Input 2: 0 c d Figure 2: An emple of input ptterns. It is ovious tht cominle input ptterns re lso overlpped ptterns. Cominle input ptterns hve nother importnt propert: Lemm 1 Suppose A nd B re input ptterns for n IP lock, if A B, let input pttern X = A B, then the output pttern for X is the union of the output ptterns for A or B. For emple, in Figure 2, the output window for input pttern {[0,20],[0,10]} is the sme with the union of output ptterns for input ptterns {[0,10],[0,10]} nd {[10,20],[0,10]}. UNIONMODEL uses this propert to model the timing ehvior of comintionl IP locks. 4.1 Model etrction First, wide rnge input pttern P is generted. Since sequentil circuits dominte the relit, nd comintionl prts re emedded in sequentil circuits, the rrivl time of primr inputs of comintionl circuit is etween 0 nd T, where T is the clock period of the sequentil circuit. We cn mke resonle ssumption tht T is upper-ounded vlue denoted s T m, then we choose the rrivl time window [0, T m] s P i, i = 1,..., n, where n is the numer of primr inputs. Then, ech window in P is evenl prtitioned into k prts, where k is positive integer. For ech primr input, we pick one prt from the corresponding k prts s n input window in the resulting smll rnge input pttern, then we cn construct k n distinct input ptterns, clled sic ptterns. Performing STA or simultions on the IP lock, we cn get the output pttern for ech sic pttern. The results re put into tle T : ech entr corresponds to one sic pttern nd its output pttern. This tle T provides ll the required informtion for UNIONMODEL ppliction. 4.2 Model ppliction Given n input pttern I, the windows in I re shifted the sme distnce to mke I supttern of P. If filed, then this cse cnnot use UNIONMODEL, nd the pin-to-pin model will e used. If succeeded, the output pttern cn e esil clculted union opertions on output ptterns in the tle. First, sed on Lemm 1, if we cn construct n input pttern P stisfing I P union opertions on sic ptterns in the tle T, then the output pttern constructed uniting ll the output ptterns of these sic ptterns is conservtive pproimtion of the output pttern of I. We designed procedure clled Pttern-Construction tht cn complete this construction successfull, which is shown in Figure 3. The suroutine Etr-CmPttern(S, i, A, B) serches for pir of cominle ptterns A nd B stisfing A i B i in pttern set S. If this serch succeeds, A nd B re removed from S nd true is returned. Procedure Pttern-Construction serches nd puts ll the sic ptterns overlpping with I into pttern set S, then for ech primr input i, it unites ll the cominle ptterns found Etr-CmPttern. After the ith outer loop, the following condition is stisfied: P S : I i P i. Thus, t the end of this procedure, S contins onl one pttern, nd I is the supttern of this pttern. Algorithm Pttern-Construction Nottions: T : tle storing ll the sic ptterns I: given input pttern n: the numer of windows in I Procedure: S = {P : (P T ) (P I Φ)} for i = 1 to n while(etr-cmpttern(s, i, A, B)=true) put X = A B into S; return S Figure 3: Input pttern construction. For emple, in Figure 2, suppose the input pttern is I{[2, 19], [3, 18]}. Initill, S contins ptterns A{, c}, B{, d}, C{, c} nd D{, d}, then in the first outer itertion, i = 1, we first unite A nd C to get pttern E{[0, 20], [0, 10]}, then unite B nd D to get pttern F {[0, 20], [10, 20]}, so efore the second outer itertion, S contins E nd F, nd I 1 is suwindow of E 1 nd F 1. Then in the second outer itertion, i = 2, we unite E nd F to get pttern X{[0, 20], [0, 20]}. Oviousl I is

4 supttern of X. From this procedure, we cn see tht the resulting input pttern is the sme with the union of ll the sic ptterns overlpping with I. So sed on Lemm 1, we hve the following theorem: Theorem 1 The output pttern for n input pttern I cn e conservtivel clculted uniting the output ptterns for sic ptterns tht overlp with I. Thus, it is not required to do the epensive input pttern unions. Insted, we serch for ll the sic ptterns overlpping with I, then look up the tle T to find nd unite ll the output ptterns corresponding to these sic ptterns to get the desired output pttern directl. And during this union step, we do not need to serch for the cominle ptterns nd unite them pir pir. Insted, for ech primr output, we cn simpl select window composed the erliest nd the ltest rrivl time mong the corresponding windows of these output ptterns s the corresponding output window of the desired output pttern. Bsed on this union procedure, we know tht UNIONMODEL chieves the conservtive output pttern for n given input pttern. Becuse of the lrge numer of tle entries, the most epensive step is to serch for the sic ptterns tht overlp with I in the tle. We need to design method to find them efficientl. We lel the primr inputs 1... n, nd lel the k prts in ech window of P 1... k in the incresing order of the erliest rrivl time. Then ech sic pttern cn e represented distinct ke with rdi k: ( n... 1) k, where 0 i k 1 for i = 1... n, nd the ith window of this pttern is the ( i+1)th prt in P i. Then we put the input ptterns nd their corresponding output ptterns in tle in the incresing order of kes. For given input pttern I, we cn find the rnge of prts [i p, i q] in P i overlpping with I i for i = 1... n, then the kes of the sic ptterns tht overlp with I re ll the distinct kes stisfing i p i i q for i = 1... n. Oviousl this method cn esil find the sic ptterns tht overlp with I in the tle. An importnt contriution of UNIONMODEL is tht it provides frmework for timing mcro-modeling of comintionl hrd IP locks with the considertion of crosstlk effects, tht is, the otinment of output ptterns for sic ptterns is not restricted to STA. Insted, other timing nlsis or simultion methods to clculte the output ptterns cn e emedded into this mcro-model. Also we cn esil incorporte functionl informtion into this mcro-model. 4.3 Speed-up techniques The ottleneck of UNIONMODEL is the lrge numer of sic ptterns. However, from Section 1 we hve known tht if input pttern A cn e constructed shifting input pttern B, the output pttern of A cn lso e constructed shifting the output pttern for B. We cll tht A nd B re reltivel the sme. Oviousl mn sic ptterns re reltivel the sme. For emple, in Figure 2, the corresponding windows in input ptterns {,c} nd {,d} re shifted 10 unit time respectivel, so these two ptterns re reltivel the sme. So it is not necessr to perform timing nlsis on ll the sic ptterns respectivel. We onl perform timing nlsis on the sic ptterns tht re not reltivel the sme with ech other. Our eperiments show tht this technique cn reduce the totl numer of sic ptterns nerl hlf. The numer of sic ptterns in UNIONMODEL is k n, where k is the numer of prts of n input window in P, nd n is the numer of inputs. So it is ver efficient to speedup the etrction of UNIONMODEL if we cn reduce the numer of inputs. In relit, it is possile to prtition the input set into severl disjoint sets such tht the reltive rrivl time of n two inputs in different sets hs no influence on the sme coupling nodes. Then the numer of sic ptterns in UNIONMODEL is 1 i u kn i, where u is the numer of disjoint sets, nd n i is the numer of inputs in the ith disjoint set. This correlted input set prtitioning technique will divide lrge size prolem to mn smll size prolems, which will speed-up the overll running much. Our eperiments show tht this method cn reduce the numer of sic ptterns gretl for some cses. When the rnge of input windows in P is lrge, we need to prtition ech input window in P into mn prts to gurntee the ccurc, so the numer of sic ptterns increses gretl. In order to void this prolem, we rndoml select some input ptterns, do STA or simultion to get the output ptterns, then we cn find the rnge of input ptterns where del chnges frequentl, so we cn shrink the rnge of input windows in P to this rnge, nd for the input ptterns tht cnnot e shifted into P, we use conventionl pin-topin model. This rnge shrinking step cn gretl reduce the numer of sic ptterns, nd enefit the model etrction nd ppliction speed. 5 Eperimentl results SIMPMODEL nd UNIONMODEL hve een implemented in C++ nd tested on ISCAS85 enchmrk circuits. For ech circuit, we rndoml designted the coupling etween wires, nd input ptterns re lso rndoml generted. All eperiments were run on Linu PC with 2.4G Hz Xeon CPU nd 2.0 GB memor. To verif the results of our methods, we designed STA tool sed on n itertive switch fctor method tht works s follows. First, it uses the modified dnmicll ounded del model to model the del of coupling nodes, then itertivel does PERT-trversl on the grph representing circuit, nd fter ech itertion updtes ll the γ v,. It does not stop until there is no chnge on ll γ v,, nd the output pttern in lst PERT-trversl is the desired. We lso implemented pin-to-pin model for comprison, which ssumed tht ll couplings tke effect. For ech cse, we compre the results from our model pplictions with the results from the pinto-pin model. Suppose for the sme primr input, {[d 1, d 2]} is the output pttern from our models, {[ 1, 2]} is the output pttern from STA, then the error of our models for this primr output is defined s [(d 2 d 1) ( 2 1)]/( 2 1). The verge error is the summtion of the errors for ll the primr outputs divided the numer of primr outputs. The miml error is the mimum of the errors for the primr outputs. A comprison of results mong STA, SIMPMODEL nd pin-to-pin model is shown in Tle 1, where ETime is the time of model etrction, ATime is the time of model ppliction, ME is the miml error, nd AveE is the verge error. We cn see tht the results of SIMPMODEL re much more ccurte thn the pin-to-pin model, nd the running time of the ppliction of SIMPMODEL is lws less thn 1 second, much fster thn STA in lrge cses. The errors re lws non-negtive, which confirms tht SIMPMODEL is conservtive. Since UNIONMODEL cn onl del with cses with smll numer of correlted primr inputs, for the cses with lrge numer of correlted primr inputs, we designted the rrivl time windows of most primr inputs to e invlid windows [, ] nd modeled onl the timing ehvior of the circuit stimulted the remining primr inputs tht re denoted RPI in our test. We clculted the output

5 Tle 1: Comprison results of STA, SIMPMODEL nd pin-to-pin model circuit STA SIMPMODEL pin-to-pin model nme #inputs #outputs #gtes time(s) ETime(s) ATime(s) ME(%) AveE(%) ME(%) AveE(%) c c c c c c c c c c Tle 2: Comprison results of STA nd UNIONMODEL circuit STA UNIONMODEL nme RPI time # sic ETime ATime ME # (s) ptterns (s) (s) (%) c , c ,200, c ,048, c , c pttern for ech sic pttern STA. A comprison of the results from UNIONMODEL with STA is shown in Tle 2. We cn see tht the results of UNIONMODEL re lmost the sme with the results of STA, tht is, UNIONMODEL is n ccurte model. From Tle 2 we cn lso see tht lthough the numers of RPI in c499 nd c5315 re the sme, the numer of sic ptterns in c5315 is much less thn in c499, which is the effect of less numer of correlted inputs in c5315 thn in c499. This confirms tht our correlted input set prtition improves the model etrction nd ppliction speed. 6 Conclusion nd future work We present two mcro-models to chrcterize the timing ehvior of comintionl hrd IP lock with the considertion of crosstlk effects. The first model, SIMPMODEL, keeps coupling grph nd lists the conditions on input ptterns for couplings not to tke effect. It cn fst estimte the output pttern for given input pttern with the scrifice of ccurc. The second model, UNIONMODEL, performs STA or simultions on sic input ptterns, nd sed on these results constructs the output pttern for given input pttern ccurtel. Both mcro-models re conservtive, nd cn gretl reduce the pessimism eisting in the trditionl pinto-pin model. Since the numer of sic ptterns is lrge when the size of correlted input set is lrge, the etrction nd ppliction of UNIONMODEL ecome prohiitive. So n importnt future tsk is to find etter w to reduce the numer of sic ptterns. To the est of our knowledge, this is the first work to del with timing mcro-modeling prolem with the considertion of crosstlk effects. References [1] A. J. Dg, L. Mize, S. Sripd, C. Wolff, nd Q. Wu. Automted timing model genertion. In DAC, pges , [2] C. W. Moon, H. Kriplni, nd K. P. Belkhle. Timing model etrction of hierrchicl locks grph reduction. In DAC, pges , [3] M. Foltin, B. Foutz, nd S. Tler. Efficient stimulus independent timing strction model sed on new concept of circuit lock trnsprenc. In DAC, pges , [4] S. V. Venktesh, R. Plermo, M. Mortzvi, nd K. Skllh. Timing strction of intellectul propert locks. In CICC, pges , [5] H. Ylcin, M. Mortzvi, R. Plermo, C. Bmji, nd K. Skllh. Functionl timing nlsis for IP chrcteriztion. In DAC, pges , [6] H. Ylcin, R. Plermo, M. Mortzvi, C. Bmji, nd K. Skllh. An dvnced timing chrcteriztion method using mode dependenc. In DAC, pges , [7] P. D. Gross, R. Arunchlm, K. Rjgopl, nd L. T. Pileggi. Determintion of worst-cse ggressor lighment for del clcultion. In ICCAD, pges , Sn Jose, CA, Novemer [8] R. Arunchlm, K. Rjgopl, nd L. T. Pilleggi. Tco: Timing nlsis with coupling. In DAC, pges , Los Angeles, CA, June [9] S. S. Sptnekr. A timing model incorporting the effect of crosstlk on del nd its ppliction to optiml chnnel routing. IEEE TCAD, [10] P. Chen, D. A. Kirkptrick, nd K. Keutzer. Switching window computtion for sttic timing nlsis in presence of crosstlk noise. In ICCAD, Sn Jose, CA, Novemer [11] T. Xio, C.-W. Chng, nd M. Mrek-Sdowsk. Efficient sttic timing nlsis in presence of crosstlk. In Proceedings of 13th Annul IEEE Interntionl ASIC/SOC Conference, pges , [12] P. F. Tehrni, S. W. Chou, nd U. Ekmrm. Deep sumicron sttic timing nlsis in presence of crosstlk. In Interntionl Smposium on Qulit Electronic Design, pges , [13] T. Xio nd M. Mrek-Sdowsk. Functionl correltion nlsis in crosstlk induced criticl pths identifiction. In DAC, pges , [14] H. Zhou, N. Sheno, nd W. Nicholls. Timing nlsis with crosstlk s fipoints on complete lttice. In DAC, pges , [15] P. Chen, Y. Kukimoto, C.-C. Teng, nd K. Keutzer. On covergence of switching windows computtion in presence of crosstlk noise. In ISPD, pges 84 89, [16] B. Thudi nd D. Bluw. Non-itertive switching window computtion for del noise. In DAC, pges , [17] Y. Sski nd G. De Micheli. Crosstlk del nlsis using reltive window method. In ASIC/SoC Conference, [18] Y. Sski nd K. Yno. Multi-ggressor reltive window method for timing nlsis including crosstlk del degrdtion. In Custom Integrted Circuit Conference, pges , [19] K. Agrwl, Y. Co, T. Sto, D. Slvester, nd C. Hu. Efficient genertion of del chnge curves for noise-wre sttic timing nlsis. In Proceedings of 15th Interntionl Conference on VLSI Design, pges 77 84, [20] S. Hssoun. Criticl pth nlsis uing dnmicll ounded del model. In DAC, pges , Los Angeles, CA, June 2000.