LOW-POWER CIRCUIT TECHNIQUES FOR BATTERY-POWERED DSP APPLICATIONS. Joong-Seok Moon

Transcription

1 OW-POWER CIRCUIT TECHNIQUES FOR BATTERY-POWERED DSP APPICATIONS by Joong-Seo Moon A Diertation Preented to the FACUTY OF THE GRADUATE SCHOO UNIVERISITY OF SOUTHERN CAIFORNIA In Partial Fulfillment of the Requirement for the Degree DOCTOR OF PHIOSOPHY (EECTRICA ENGINEERING Augut 3 Copyright 3 Joong-Seo Moon

2 Dedication Thi diertation i dedicated to all of my family member for their love, encouragement and upport. ii

3 Acnowledgement I alway wondered when I would write the acnowledgement of the diertation. It ha been o long ince I tarted my tudy thu I got lot in depair on many occaion. So many people helped, encouraged and advied me during thi once eemingly endle battle. Putting my enormou gratitude toward them into word eem to be the mot difficult ta, but let me try. Firt, there i Prof. Peter Beerel. He graciouly accepted me into hi group in the middle of my Ph.D. wor and continuouly encouraged me to finih my diertation. Hi amazing ability to turn thing from mey to crytal clear alway mae me wonder. Without hi help, mot of wor if not all in thi diertation wouldn t exit. Second, Dr. Jeff Draper deerve my utmot gratitude for hi upport, encouragement, generoity and advice. During my lat two year in ISI, I got all the upport from him every graduate tudent would wih for: great reearch project, trong trut and invaluable technical advice. Third, I would lie to appreciate Dr. Pedro Diniz for being a member of my Ph.D. committee and giving me many preciou feedbac. In addition, I would lie to appreciate Prof. Maoud Pedram and Prof. Sandeep Gupta for their invaluable feedbac during my Ph.D. qualifying exam. Fourth, it i hard to imagine my reearch without the guidance from Dr. Bill Atha. Every ingle circuit preented in thi diertation originate from dicuion with him. I really wihed I would pend more time with him when he left ISI, o I am going to tart to wor with him again. It i going to be an enjoyable challenge. Fifth, I would lie to than Prof. Alvin iii

4 Depain and Prof. Deog-Kyoon Jeong who introduced the field of computer architecture and VSI to me. There are many friend at USC with whom I enjoyed a trong friendhip. Firt, there are three guy I and my family enjoyed pending time together: Sangyun Kim, Ihn Kim and Kiup Chong. We hare grief and delight together all the time. I certainly hope to continue our friendhip in the ame way. Second, USC Aynchronou CAD/VSI group member have been great to mingle with: Recep Ozdag, Marco Ferretti, Sunan Tuginaviut, Haan Durmu and Hohi Kim. We never pronounced each other lat name correctly, but it didn t bother u at all to enjoy getting together. Third, I am lucy to have a lot of good friend at ISI. In particular, I would lie to than Jooneo Par, Tae-Jun Kwon, Chang-Woo Kang and Dongho Kim for wating their time to liten to my grumbling. I am going to mi them a lot. Other friend outide USC need to be mentioned here for their perennial upport and friendhip. Epecially, Clar Jooneo Kim and Yong-Seo Choi have been my bet friend and will be forever. at but not the leat, there are my whole family member. Mom, than you and I love you. I wih Dad would watch hi on to graduate, but I am ure he will be very proud of u. My parent-in-law, I am o glad to have you. Than you for all of your upport and encouragement. Siter, brother, brother-in-law and iter-in-law, than you for being with me. My on, Jaon, than you for being in thi world. You are the iv

5 mot preciou gift I ever got. I promie I will be a good father from now on. Hyun- Jung, my dear wife, it i not my degree but our degree. I dedicate my pot-graduate life to you a well a thi diertation. v

6 Table of Content Dedication...ii Acnowledgement...iii Table of Content...vi it of Figure...viii it of Table...xii Abtract...xiii Chapter.... Bacground of low-power CMOS digital deign..... Technology Circuit and logic Architecture Algorithm and ytem...7. Contribution Organization...9 Chapter.... Motivation.... Architecture....3 Read timing baed on the handhaing protocol Circuit Static memory cell Sene amplifier and latch Decoder cell Write driver Flip-flop for addre input Read controller: rdec_en ignal generator Read controller: a_en ignal generator Read controller: precharge ignal generator Read timing Performance and power imulation reult Implementation: DC- 3-bit general-purpoe microproceor...3 Chapter Motivation...3 vi

7 3. Architecture Circuit Sequencer cell Ban equencer Sequencer cell Overall read operation ummary Tet chip and meaurement reult...43 Chapter Motivation Current-fed voltage pule-forming networ Theoretical analyi of current-fed voltage pule-forming networ Voltage-pule driven pule-forming networ Voltage-pule driven networ for DC current ource elimination A tan capacitor for a poitive-wing waveform Meaurement...7 Chapter Motivation Architecture Timing and circuit ocal cloc generation Controller Read operation Write operation Overall timing for FIR filtering Iue with the cloc ditribution networ Global and hierarchical cloc tree Reonant and conventional cloc driver Implementation Kaier-window low-pa FIR filter Simulation reult...6 Chapter 6... Reference...5 Appendix... vii

8 it of Figure Figure : A bloc diagram of an N x M Regiter File...3 Figure : Micro-operation dependency flowchart...4 Figure 3: A Timing diagram of the regiter file read operation...5 Figure 4: A bloc diagram of the read controller...6 Figure 5: A chematic of a three-port SRAM cell...7 Figure 6: Write operation for two different value on the SRAM cell...7 Figure 7: A chematic of a ene amplifier and a latch...8 Figure 8: A timing diagram of the ene amplifier and latch...8 Figure 9: A chematic of a 4-to-6 addre decoder cell... Figure : A chematic of a write driver... Figure : An original ene-amplifier baed flip-flop... Figure : A modified flip-flop that reet output to zero at the negative edge of a cloc ignal... Figure 3: A chematic of the read controller: a rdec_en ignal generator...3 Figure 4: A chematic of the read controller: a a_en ignal generator...3 Figure 5: A chematic of the read controller: a precharge ignal generator...4 Figure 6: Signal tranition of a read operation...5 Figure 7: Wort-cae delay of the regiter file...6 Figure 8: Relative power diipation of the read operation...9 Figure 9: A microphotograph of the DC- microproceor...3 Figure : A bloc diagram of an N x M SAM...34 Figure : A bloc diagram of a 64x6-b SAM compoed of four 6x6-b SAM ban...35 viii

9 Figure : A chematic of the equencer cell...37 Figure 3: A timing diagram of the equencer cell...37 Figure 4: A chematic of the ban equencer...38 Figure 5: A timing diagram of the ban equencer...39 Figure 6: A chematic of the read controller...4 Figure 7: A timing diagram of read controller...4 Figure 8: Signal tranition of the read operation...4 Figure 9: A microphotograph of the tet chip...43 Figure 3: Meaured power diipation of the wort-cae read operation...45 Figure 3: Meaured power diipation of the wort-cae write operation...45 Figure 3: A ingle-rail reonant cloc driver (Flybac circuit...48 Figure 33: All-reonant blip driver...48 Figure 34: A harmonic reonant rail driver containing three harmonic term...49 Figure 35: A trapezoidal-wave voltage ignal with lope V O /(*T...5 Figure 36: Current-fed voltage pule-forming networ (CFVPN Figure 37: An equivalent networ of Figure 36 containing a capacitance C that can repreent an on-chip cloc load...55 Figure 38: An Equivalent networ of Figure 37 driven by a voltage pule...63 Figure 39: Practical approximation of the networ hown in Figure Figure 4: Frequency repone of the networ hown in Figure 39 (Vo(/Vi(...66 Figure 4: The propoed networ with the paraitic reitance of inductor...66 Figure 4: Frequency repone of the networ hown in Figure 4 for the firt two harmonic frequencie (a magnitude (b phae Figure 43: DC teady-tate for the networ (a without C T (b with C T Figure 44: A voltage-pule driven harmonic reonant rail driver...7 ix

10 Figure 45: Normalized power diipation (P/fCV and tranition time veru reitance R. fcv i the theoretical conventional power diipation to drive load capacitance C Figure 46: A cope trace of output waveform for the nd -order driver at MHz...75 Figure 47: A cope trace of output waveform for the 3 rd -order driver at MHz Figure 48: A FFT-enabled cope trace of waveform for the 4 th -order driver at MHz Figure 49: A cope trace of output waveform for the nd -order driver at MHz...76 Figure 5: Normalized power diipation veru load capacitance (C. All component except C are ept ame a deigned for pf C...77 Figure 5: Cloc jitter veru load capacitance (C Figure 5: Normalized power diipation veru cloc cycle variation Figure 53: A tapped delay line implementation of N-tap FIR filter....8 Figure 54: A generic DSP architecture for FIR filter...8 Figure 55: A bloc diagram of a N-tap FIR filter...85 Figure 56: A timing diagram of the read operation of SAM with a newly added complete ignal...87 Figure 57: A bloc diagram of the 64-tap FIR filter controller Figure 58: A timing diagram of the 64-tap FIR filter controller...88 Figure 59: A tarting location of the data memory for each ample...89 Figure 6: A timing diagram of read accee for the 64-tap FIR filter....9 Figure 6: A modified read controller of the SAM to enable an initial read acce by pphi...9 Figure 6: A bloc diagram of the data memory to generate the local cloc ignal lphi...9 Figure 63: A timing diagram of Figure 6. Each ban i aumed to have only two row to implify the diagram...9 x

11 Figure 64: A modified read controller of the multi-ban SAM to enable an initial read acce by pphi...93 Figure 65: A timing diagram of write operation...94 Figure 66: An overall timing diagram of FIR filtering...95 Figure 67: Hierarchical cloc tree generation for FIR filter ban...97 Figure 68: Conventional cloc tree generation with global cloc ditribution...98 Figure 69: Two cloc tree driving cheme: (a Single driver cheme (b ditributed buffer cheme...99 Figure 7: Serpentine cloc ditribution networ... Figure 7: Balanced H-tree cloc ditribution networ... Figure 7: A layout plot of the 6-tap FIR filter...3 Figure 73: A layout plot of the 64-tap FIR filter...4 Figure 74: Frequency repone of two low-pa FIR filter....5 Figure 75: FFT plot of the peech ampled at 6KHz...6 Figure 76: Average cycle time of two FIR filter....7 Figure 77: Energy/ample plot for two FIR filter...8 Figure 78: Power breadown of two FIR filter....9 Figure 79: Waveform plot for v x (t in Eq xi

12 it of Table Table : Wort-cae power diipation of the regiter file at the maximum cloc frequencie for a give upply voltage...8 Table : Summary of the proce technology and the tet chip...44 Table 3: Component Value for Networ of Figure Table 4: Meaured data of econd, third, and fourth quare-wave harmonic reonant rail driver for variou cloc frequencie and load capacitance. The firt three row are data for driving 97.8pF load capacitance at different cloc frequencie and the lat row how data for different load capacitance at MHz. Theoretical and meaured value of each component are alo hown for comparion....7 Table 5: Summary of the proce technology and the tet chip... Table 6: Cloc cycle time variation (T max/min T avg / T avg...8 Table 7: Effective cloc capacitance of the conventional cloc tree for filter ban... Table 8: Effective cloc capacitance of the balanced H-tree... xii

13 Abtract One of the mot crucial factor that fuel the need for low-power VSI chip i the increaed maret demand for portable conumer electronic powered by batterie. The craving for maller, lighter and more durable electronic product indirectly tranlate to low-power requirement. Thi diertation propoe variou circuit technique for the memory and the cloc networ, which are among the major power conuming component in many portable DSP application. Firt, a general-purpoe high-performance low-power regiter file deign i preented. Baed on elf-reetting potcharge logic, the deign provide wide voltage calability and avoid hort-circuit current. Second, we preent a equential acce memory deign to further optimize power diipation and performance by replacing decoder with novel equencer. The equential acce pattern for memory i ubiquitou in many DSP application uch a FIR filtering and FIFO. Power diipation required for addre equencing logic, decoder and driver for addre line are eliminated by exploiting thi characteritic. Third, we preent an energy-efficient cloc generator baed on the harmonic reonant circuit technique. Significant power diipation for a cloc networ i reduced becaue mot of the charge i recovered by driving the networ reonantly. Experimental reult are preented for a comparion with conventional cloc driver and variou characteritic of the propoed circuit are quantified. Finally, a novel FIR filter deign i preented a a cae tudy to how the feaibility of the propoed circuit xiii

14 technique for a real DSP application. The high-frequency cloc ignal needed for FIR filter operation i locally generated from a elf-reetting memory control ignal. In thi way, the ytem cloc frequency i reduced to the ample rate. The datapath i deigned in the tandard ASIC deign methodology without any pecial interfacing logic. xiv

15 Chapter INTRODUCTION The increaing demand for low power diipation ha been driven by a growing cla of portable, battery-powered application that demand ever-increaing functionality and battery life. Power diipation play the mot important role in the deign and implementation of many, if not all, of thee application due to the contingent requirement on battery dimenion and weight. Traditionally, Nicel-Cadmium batterie had been ued in mot application that require rechargeable batterie. Nicel-Metal Hybrid (Ni-MH and ithium-ion batterie recently became more popular batterie for portable application for their improved energy denity and reduced toxic heavy metal [5]. The energy capacity of batterie ha been improving over the lat two decade, but at a very low pace []. Moreover, the energy tored in a battery cannot be extracted to the full extent due to the trong dependence of the energy capacity on the mean value of the dicharge current a well a the portion of energy that i wated by the DC/DC converter [5]. With a projection of thi low pace and limitation of battery technology, unle low-power approache are adopted in variou apect of ytem, current and future portable device will uffer ignificantly from either very hort battery life or unreaonably heavy battery pac.

16 Many of thee battery-powered device perform digital ignal proceing (DSP function [5], including FIR/IIR (finite/infinite impule repone filtering [4][44][45], CODEC (coding and decoding [58][], DCT/IDCT (dicrete coine tranform [][7], and FFT (fat Fourier tranform [][3]. In thee device, maintaining a given level of computation or throughput i a common concept, in which there i no advantage in performing the computation fater than a given rate ince the hardware will imply have to wait until further computation i required. Thi i in harp contrat to general-purpoe proceing, where the goal i often to provide the fatet poible computation without bound [8]. Thi enable a variety of technique that lower power diipation while maintaining a contant throughput. Baed on thee contraint, the motivation for thi reearch i to invetigate practical low-power circuit olution for battery-powered DSP device to increae the battery life at a given throughput.. Bacground of low-power CMOS digital deign The ource of power diipation in CMOS circuit can be claified a dynamic, hort circuit and leaage power [7][57]. For mot CMOS deign, the dynamic power diipation i the main ource of power diipation and i given by P f C V DD α Eq. where i the witching activity of the ignal involved, C i the load capacitance, V DD i the upply voltage level of the ytem and f i the average data

17 rate, which i uually the cloc frequency in a ynchronou ytem [7]. Thi equation ugget that there are three degree of freedom in the low-power deign pace: voltage, phyical capacitance, and witching activity [5]. To reduce thee fundamental element of power diipation, all level of the deign hierarchy can be approached. The following ection briefly ummarize the power diipation optimization at each level of the deign hierarchy... Technology A hown in Eq., dynamic power diipation i quadratically proportional to the upply voltage. Therefore, reducing the upply voltage i the mot effective mean of minimizing the power diipation. However, lowering V DD for a given technology lead to lower performance. In particular, a V DD approache the tranitor threhold voltage, the performance of the ytem decreae exponentially. The mot popular technology optimization for low power diipation i to reduce the threhold voltage of the device [64]. Reducing the threhold voltage allow the upply voltage to be caled down without lo of performance. There i a limit for the threhold voltage caling due to the increae in the ubthrehold current a the threhold voltage cale down. Moreover, the reduced noie margin may adverely affect the ytem tability. Therefore, the optimal threhold voltage mut compromie between improvement of current drive at low upply voltage operation and control of the ubthrehold current and noie margin. 3

18 .. Circuit and logic Contrary to the technology optimization where reducing the upply voltage level i a major goal, at the circuit and logic level, all three element (voltage, phyical capacitance and witching activity are conidered to reduce power diipation. A myriad of low-power approache ha been propoed at thi level and ome repreentative wor are ummarized a follow. A. ow voltage wing circuit deign At a given upply voltage, the output of full-wing CMOS gate mae rail-to-rail tranition. In low voltage wing circuit deign, power diipation i reduced by limiting the voltage wing on the output node [74][3]. However, care mut be taen to enure reduced wing node do not lead to increaed tatic power diipation. In particular, interface with conventional gate require pecial receiver to convert low wing input to full wing output, which may incur large circuit overhead. To limit thi overhead, low voltage wing technique target only high-capacitance node uch a data bue. B. Gated clocing for logic level power-down In ynchronou deign, the logic between regiter i continuouly computing every cloc cycle baed on it new input. To reduce the power in ynchronou deign, it i very effective to minimize witching activity by powering down logic bloc when 4

19 they are not performing ueful operation. Self-timed or aynchronou circuit have an inherent power-down feature for unued bloc, ince tranition occur only when requeted [4]. However, generation of completion ignal indicating the output of the logic bloc are valid generally require additional circuit overhead. In ynchronou deign, thi can be done uing gated clocing technique that enable regiter only when neceary [48][4][7]. C. Energy-recovery and adiabatic circuit deign In energy-recovery circuit deign [57][], circuit energy that would otherwie be diipated a heat i intead conerved for later reue. Thi i a completely different approach from other conventional technique where the goal i to minimize the energy delivery that will be completely diipated a heat. The DC power upply i replaced with an AC power ource to enable bidirectional energy delivery. Cloc ignal generated by reonant circuit have been widely adopted a the cheapet ource of AC power for thee application [7]. In adiabatic circuit deign [7][6], on the other hand, lowing down the charge tranfer between node reduce the power diipation due to the reitance of the witche uually implemented a tranitor. Thee two technique are commonly combined to maximize energy efficiency [9][8]. 5

20 D. Other method Other circuit and logic minimization technique include High-efficiency DC/DC converion circuit deign [5][6] ogic minimization and technology mapping [33][65][7] Tranitor izing and logic manipulation [8][7]..3 Architecture A we cale down the upply voltage for low power diipation, the performance of a device decreae due to the reduced conduction current of tranitor. One way to maintain throughput while reducing the upply voltage i to utilize a parallel architecture, either uing hardware duplication or pipelining [8][7]. The amount of parallelim needed to achieve a given throughput depend on the level of the reduced upply voltage. However, a the upply voltage approache the threhold voltage, the degradation in performance increae dramatically and the overhead aociated with parallel architecture increae overall power. The optimum voltage can be found where further reduction in the upply voltage mae the power diipation increae. The area overhead of pipelining can be much maller than the hardware duplication approach, ince only tage regiter have to be added intead of complete hardware duplication. However, partitioning into everal pipeline tage for ome hardware require more pipeline regiter to accommodate the intermediate ignal. Clearly 6

21 thee two approache can be ued imultaneouly. Other architecture driven lowpower technique are Choice of number repreentation to minimize witching activity [63] Reordering input ignal [8][7] ogic depth balancing to reduce glitching activity [][]..4 Algorithm and ytem The choice of algorithm can mae a huge impact on the total power diipation of the ytem, uch a reduction of arithmetic operation and memory accee by tranforming a given algorithm [49]. Other example at thi level include operator reduction [9] and contant propagation [54] [54]. In ytem-level power optimization, battery deign, intelligent power management and OS upport for leep level are found in many deign example.. Contribution A pointed out in the previou ection, the algorithm and ytem level have the mot ignificant effect on the total power diipation of the ytem. However, for a given algorithm and ytem pecification, we mut approach other level of the deign hierarchy for further reduction of the power diipation. In particular, circuit technique for low power diipation can have a major impact becaue ome circuit are repeated thouand of time on a chip and many high-capacitance node are 7

22 witching regularly. Thi diertation propoe variou circuit technique for memory bloc and a cloc networ, which are among the major power conuming component in many portable DSP application. It then preent a cae tudy to how the feaibility of the propoed circuit technique in a real DSP application and quantifie the improvement compared to traditional deign. The following paragraph ummarize the contribution of thi diertation. A. Regiter file deign Firt, we preent a high-peed and low-power regiter file deign. A novel read controller uing elf-reetting potcharge logic i preented to minimize tatic power diipation and to increae voltage calability for read operation. Thi circuit technique can be extended to a large SRAM deign with a mall modification. In addition, the propoed regiter file deign can be eaily converted for a elf-timed computation environment. B. Sequential acce memory deign Second, we preent a equential acce memory deign to further optimize power diipation and performance by replacing decoder with novel equencer. The equential acce pattern for memory i ubiquitou in many DSP function lie FIR filter and FIFO. The power diipation required for addre equencing logic, decoder and driver for addre line are eliminated by exploiting thi characteritic. 8

23 C. Harmonic reonant cloc generator deign Third, we preent an energy efficient cloc generator baed on the harmonic reonant circuit technique. Significant power diipation for a cloc networ can be aved becaue mot of the charge can be recovered by driving the networ reonantly. Experimental reult are preented to compare with a conventional cloc driver, and variou characteritic of the propoed circuit are quantified. The circuit perform well in the low to mid cloc frequency range with a ignificant aving in power diipation. D. FIR filter implementation Fourth, a novel FIR filter deign i preented a a cae tudy to how the feaibility of the propoed circuit technique in a real DSP application. A elf-reetting data memory i configured uch that it generate a toppable cloc that i ynchronouly tarted and aynchronouly topped. In thi way, the ytem cloc frequency i reduced to the ample rate. The circuit overhead i minimal by utilizing mot of exiting ignal. The datapath i deigned in the tandard ASIC deign methodology without any pecial interfacing logic..3 Organization The remainder of thi diertation i organized a follow. Chapter preent the regiter file deign which i the foundation of our memory deign technique 9

24 throughout thi diertation. Our equential acce memory deign i preented in Chapter 3. Chapter 4 then decribe the harmonic reonant cloc generator deign. The memory-triggered elf-timed FIR filter i preented in Chapter 5 a a cae tudy utilizing our propoed circuit technique in a real DSP application. Chapter 6 preent concluion and ome iue for future reearch.

25 Chapter OW-POWER REGISTER-FIE DESIGN. Motivation Regiter file ued in the deign of microproceor or digital ignal proceor are often implemented a multi-port on-chip SRAM. For microproceor, a low-power high-peed regiter file i important becaue almot every intruction in all intruction et require read and/or write accee to the regiter file. In digital ignal proceor, mot of the application require treaming data operation, which require accee to a mall window of a data tream repeatedly. Therefore, the puruit of low-power high-peed regiter file deign ha lead to numerou deign technique and implementation [36][3][37][46][4]. One properou avenue for regiter file deign i to ue elf-reetting potcharge logic [3][3][4][47]. Selfreetting potcharge logic exploit aynchronou and elf-timed circuit concept without incurring the typical circuitry overhead of aynchronou circuitry. In particular, thi technique i highly effective for memory deign becaue dummy memory cell [47][4] and reet inverter chain [3][4] that effectively imulate the actual timing can implify the completion detection ignal generation with a mall overhead. However, enuring deign robutne i relatively difficult for thi technique becaue unexpected timing margin error from proce variation can caue failure in functionality, which cannot be overcome by changing the cloc

26 frequency or the upply voltage. A a reult, an increaed uceptibility to proce variation require ignificant deign effort and ophiticated CAD tool. We preent a novel regiter file deign uing elf-reetting potcharge logic. Reet inverter chain are replaced with the read controller that implement a hand-haing protocol. Several benefit arie from uing a hand-haing protocol rather than reet inverter-chain. Firt, uceptibility to proce variation i minimized, and thu deign effort can be ignificantly reduced. Second, tatic power diipation i minimized by defining a equence of control ignal uch that tatic current that typically arie due to overlap between bitline precharging and wordline driving are motly eliminated. In addition, dynamic power diipation incurred by the reet inverter chain can be removed. The propoed read controller i triggered by a ingle cloc edge o that it can generate control ignal for a regiter file that ue inglephae or multi-phae cloc. The propoed regiter file wa implemented in.5m CMOS technology for a general-purpoe microproceor [43][9] [6].. Architecture Figure how a bloc diagram of our propoed three-port N x M-bit regiter file allowing two read and one write accee imultaneouly. A regiter array, three decoder (two for read and one for write, write driver, two ene amplifier array with latche, flip-flop for addre input, precharge logic and read/write controller are hown.

27 Figure : A bloc diagram of an N x M Regiter File To enable a read operation, the read enable ignal (RdEn mut be aerted. Then, upon the riing edge of the cloc ignal, the read decoder enable ignal (rdec_en i raied to enable the decoder to aert the wordline ignal (rwl[] correponding to the current input read addree (raddra[log N-:], raddrb[log N-:]. Thi activate the aociated memory cell and dummy cell, driving the read bitline (rbita[m-:],rbitb[m-:] and the dummy bitline (dumbit, repectively. The write operation i imilar except the write bitline (wbit[m-:] are not precharged. The propoed handhaing protocol, which will be explained in the next ection, i integrated in the read controller. 3

28 .3 Read timing baed on the handhaing protocol The read controller of the regiter file ha even micro-operation that contitute a read acce of the regiter file. Thee are:. Wait for detect read requet,. Enable addre decode and diable bitline precharge, 3. Enable wordline, 4. Start memory read and enable ene amplifier, 5. Detect completion of memory read, 6. Diable wordline and ene amplifier then latch read output, 7. Enable bitline precharge. The flowchart of Figure how the dependencie between thee micro-operation. Figure : Micro-operation dependency flowchart Maintaining thee dependencie enure the functionality and minimize tatic power diipation mainly caued by the overlap between bitline precharge and memory acce. A dummy bitline and dummy memory cell are ued to trac the latency of 4

29 reading bitline and detect the completion of a memory acce. The regiter file i triggered by the riing edge of the cloc. However, it can be eaily adapted to be triggered by a falling edge of the cloc. A timing diagram of the regiter file i preented in Figure 3 with annotation to pecify the correponding micro-operation in Figure. Figure 3: A Timing diagram of the regiter file read operation All ignal interaction of read operation are directed by three control ignal rdec_en, a_en, precharge with dumbit ignal and cloc. Figure 4 how the bloc diagram of the read controller, which i compoed of three bloc: decoder enable ignal, ene amplifier enable ignal, and precharge ignal generator. By following the equence hown in Figure, interconnection between thee bloc can be eaily undertood. The rdec_en ignal i triggered by the cloc ignal, while the dumbit ignal trigger the a_en ignal. The rdec_en ignal trigger the precharge ignal. Notice that the precharge ignal and the rwln[n-:] ignal are completely nonoverlapping, uggeting that the tatic current between memory cell and precharge 5

30 tranitor can be eliminated. A detailed circuit implementation will be decribed in the next ection. Figure 4: A bloc diagram of the read controller.4 Circuit.4. Static memory cell Figure 5 how the three-port SRAM circuit chematic. A ingle-ended cheme i ued both for write and read operation to reduce power diipation. Write operation for two different value are depicted in Figure 6. A differential mode i ued for writing high value on node q while a ingle-ended mode i ued for writing low value. Therefore, the latency for write operation i dependent upon the write data value. However, thi latency variation doe not contrain the performance becaue write operation are inherently much fater than read operation in the SRAM deign. 6

31 Figure 5: A chematic of a three-port SRAM cell Figure 6: Write operation for two different value on the SRAM cell 7

32 .4. Sene amplifier and latch A mentioned in the previou ection, we ued a ingle-ended bitline for both read and write operation to reduce power diipation. The chematic of the ene amplifier and latch i hown in Figure 7. Figure 7: A chematic of a ene amplifier and a latch Figure 8: A timing diagram of the ene amplifier and latch A tri-tate buffer followed by cro-coupled inverter convert and latche dynamic read data. The rdbit ignal ha a low tranition from high to low when the value tored in memory ha a high value, a the mall NMOS tranitor dicharge the relatively large bitline capacitance. When the tored value i zero, the precharged 8

33 high value on the rdbit node i retained. Therefore, intead of connecting thi low ignal to the conventional buffer/inverter to convert into the fat full-wing ignal, only a PMOS tranitor (P i connected to the rdbit ignal. A rdbit ha only negative going tranition, the propoed circuit can eliminate tatic current from the low input lew rate. The NMOS tranitor (N connected to the areet ignal i turned off during read operation. When a read operation i completed, thi ignal reet the internal node (drdout to zero. The areet ignal i generated imply a the inverted form of the precharge ignal. A timing diagram of the ene amplifier and latch i preented in Figure Decoder cell Since the number of addre input i modet (3-6 in the regiter file deign, a pure ingle-level dynamic NAND gate i ued for decoder cell of the regiter file. Figure 9 how a chematic of a four input addre decoder cell. To prevent the charge haring problem reulting from a long NMOS chain, two wea PMOS (P, P tranitor are added..4.4 Write driver A imple tri-tate buffer i ued for the ingle-ended write driver circuit a hown in Figure. 9

34 Figure 9: A chematic of a 4-to-6 addre decoder cell Figure : A chematic of a write driver.4.5 Flip-flop for addre input A normal flip-flop output cannot be ued for the dynamic gate ince a negative tranition of the output during the evaluation phae of the dynamic gate can accidentally dicharge the precharged value. A latch wor well with the dynamic gate, but more than one cloc phae i required. To avoid a multi-phae clocing

35 deign and to combine dynamic logic with an edge-triggered input, the flip-flop i deigned uch that the output of the flip-flop alway ha a poitive-going ignal. Thi can be done by reetting the output of the flip-flop to low at the negative edge of the cloc ignal. Figure : An original ene-amplifier baed flip-flop Figure : A modified flip-flop that reet output to zero at the negative edge of a cloc ignal

36 Figure how the original flip-flop deign baed on the ene-amplifier tructure ued in StrongARM microproceor [4]. Cro-coupled NAND gate at the output tage hold the latched value during the low phae of the cloc ignal. By replacing thee NAND gate with the cro-coupled NOR gate, we can eaily convert thi flip-flop to reet the output at the negative edge of the cloc ignal. The modified flip-flop circuit i preented in Figure..4.6 Read controller: rdec_en ignal generator Read operation are initiated by enabling the read decoder. The rdec_en ignal generated by the circuit hown in Figure 3 tart the evaluation of addre decoding. During the low phae of the cloc ignal, node A i precharged. At the riing edge of the cloc, node B i pulled down and the rdec_en ignal i aerted to high. After the read operation i completed, the a_en ignal i aerted by the ene amplifier enable ignal generator. At the riing edge of the a_en ignal, the rdec_en ignal reet to low value. The a_en ignal can arrive either during high phae or low phae of the cloc ignal depending on the upply voltage and operating frequency. The propoed circuit i deigned uch that branch A i turned on only for the poitive tranition of the rdec_en ignal and branch B for the negative tranition regardle of the cloc phae.

37 .4.7 Read controller: a_en ignal generator The a_en ignal generator ue the ame topology a the ene amplifier circuit hown in Figure 7 except the tri-tate buffer in the ene amplifier i replaced by an n-latch circuit a hown in Figure 4. The dumbit ignal i ued to imulate and detect the actual memory acce latency. When the a_en ignal i aerted by the dumbit ignal, it i aumed that all other memory accee are completed. Figure 3: A chematic of the read controller: a rdec_en ignal generator Figure 4: A chematic of the read controller: a a_en ignal generator 3

38 .4.8 Read controller: precharge ignal generator Figure 5 how the chematic of the precharge ignal generator. To eliminate tatic power diipation, we mut diable the bitline precharging before the read operation and enable again right after the read operation i completed. The rdec_en ignal i ued to diable the bitline precharging ince the riing edge of thi ignal i the firt tranaction of the read operation. A uggeted in Figure 3, the completion of the read operation can be defined by the falling edge of the a_en ignal. Therefore, the a_en ignal i connected to one of the PMOS tranitor to retart the bitline precharging. Figure 5: A chematic of the read controller: a precharge ignal generator 4

39 .4.9 Read timing Figure 6 ummarize the ignal tranition for a read operation. Each tranition i identified and numbered in the increaing order of operation equence. Tranition with the ame number are concurrent. Figure 6: Signal tranition of a read operation 5

40 .5 Performance and power imulation reult The propoed regiter file wa deigned and implemented in a.5-µm technology for a general-purpoe microproceor and a hearing-aid feedbac cancellation proceor. Extenive PowerMill and HSPICE imulation were performed to meaure the wort-cae power diipation and acce time of the regiter file. Three different configuration - 8 x 3b, 6 x 3b, 3 x 3b - were deigned. Figure 7 how the wort-cae delay of three regiter file at variou upply voltage x 3 6 x 3 3 x 3 4 Tcl (n Vdd Figure 7: Wort-cae delay of the regiter file A hown in Figure 7, the wort-cae delay of the 8 x 3b regiter file ha the mallet delay for all upply voltage. The difference of the wort-cae delay increae a the upply voltage decreae. The imulated maximum frequency for the 6

41 three regiter file configuration wa meaured a 3MHz (8 x 3b, 4MHz (6 x 3b and 9MHz (3 x 3b at.v upply voltage repectively. At 3.3V upply voltage, the maximum frequency wa meaured a 3MHz, 5MHz and MHz, repectively. Contrary to a conventional regiter file deign where bitline precharging i controlled by the cloc uch that half of the cloc cycle i wated for the precharging operation, HSPICE imulation how that only -5% of the cloc cycle i conumed for bitline precharging in the preented regiter file deign. Thi in turn give better voltage calability for high-performance application. We meaured the wort-cae power diipation at each upply voltage and maximum frequency by uing the following input pattern. Read Addree: Write Addree: Write data: Read data: Power diipation for the wort-cae pattern wa meaured from PowerMill imulation. Table ummarize the power diipation reult at the maximum frequency. 7

42 Table : Wort-cae power diipation of the regiter file at the maximum cloc frequencie for a give upply voltage 8

43 The effective capacitance in the table i calculated by the following equation. P I V C eff DD P /( f CK f CK V C DD eff V DD Eq. Simulation reult how that thi value i relatively independent of the cloc frequency and the upply voltage, uggeting that the tatic power diipation i virtually eliminated. A mall increae in the effective capacitance wa oberved a the upply voltage increae due to the increaed voltage region where both PMOS and NMOS tranitor are turned on imultaneouly. Another HSPICE imulation reult how that the tandby current wa le than.ua for all operating condition. Figure 8 how the relative read power diipation for each functional bloc of three regiter file configuration. Relative read power diipation % 9% 8% 7% 6% 5% 4% 3% % 5.95% 3.79% 4.% 4.93%.36% 3.74% 6.8% 8.94% 36.6% 9.% 47.94% 5.34% Read Decoder Sene Amplifier Read Controller Precharging Read Addre Driver % 4.75% 7.9%.8% % 8 x 3 6 x 3 3 x 3 Regiter file ize Figure 8: Relative power diipation of the read operation 9

44 One thing to notice in the above graph i that the relative power diipation for precharging bitline and driving addre line increae a the ize of the regiter file increae. The relative power diipation for the controller decreae becaue mot of the control ignal drive the ame bit width. In the next chapter, we will explore a equential acce memory deign where the power diipation for driving the addre line can be eliminated..6 Implementation: DC- 3-bit general-purpoe microproceor The propoed 3 x 3-b regiter file wa integrated in the DC- 3-bit generalpurpoe microproceor and fabricated in.5-m CMOS technology. Due to the contingent pin requirement, eparate power and peed meaurement of the regiter file were not performed. ab meaurement how the chip i functional acro a voltage range between.v and 3.6V. The chip microphotograph i preented in Figure 9. 3

45 Figure 9: A microphotograph of the DC- microproceor 3

46 Chapter 3 OW-POWER SEQUENTIA ACCESS MEMORY DESIGN 3. Motivation In many DSP application a large fraction of the power i conumed in memory accee [59]. Numerou general-purpoe low power and high performance SRAM have been propoed, motly for high-peed deign [37][3]. Self-reetting circuit triggered with matched delay line implemented with dummy memory cell [3][4][47] often yield relatively low-power and high-peed by limiting the power diipation in the bitline and reducing precharge time a hown in the previou chapter. A few deign have been propoed for low-power memorie with pecial emphai on reduction of leaage current for low-threhold voltage device [35][4]. In many DSP application SRAM deign do not require random acce and often have trictly equential read and/or write acce pattern. In particular, programmable FIR filter read/write coefficient and data in a firt-in firt-out pattern [4]. The naïve implementation of uch tructure involve the movement of data ample each cloc cycle uing hift regiter. However, for low-power implementation, the memory can be configured a a circular buffer (with a equential acce pattern in which pointer rather than data are moved [68]. In addition, for many digital communication channel decoder, interleaver that are ued to tore and re-organize large bloc of data ample can be deigned with 3

47 memorie that upport random write and equential read (or vice vera. Moreover, equential acce of intermediate data within many channel decoder, including Fano decoder [6] and turbo decoder [39], i alo typical. In all thee cae, the naïve implementation involve uing SRAM depite the fact that the architecture often accee data equentially. Thi motivate the deign of equential acce memorie to eliminate the power diipation for addre decoding. Thi chapter preent a novel equential acce memory (SAM deign where addre equencing logic and decoder are replaced with row equencer to achieve high peed and low power. Mot of the control ignal are generated uing efficient equencer cell that communicate primarily with neighboring row only, minimizing the power diipation of wordline election. When combined with typical ban tructure that limit the amount of witched bit-line capacitance of large memorie and efficient elf-reetting potcharge logic, power diipation i largely independent of memory ize. Thi i in harp contrat to conventional SRAM deign. A tet chip wa fabricated in.5-m CMOS technology to evaluate thi deign. The chip contain two different dual-port (one read port and one write port SAM configuration: one 6x6-b and one 64x6-b, coniting of four 6x6-b ban. The chip ha been teted and i fully functional at operating voltage of.67v to.5v. The power diipation of both SAM wa meaured at different voltage and operating frequencie and found to be within 5% of each other, demontrating that power diipation i largely independent of memory ize. With a cloc frequency of 33

48 4MHz at.v, the meaured wort-cae read power diipation for the 6x6-b SAM i 344W and for the 64x6-b SAM i 358W. 3. Architecture Figure how a bloc diagram of our propoed dual-port NxM-bit SAM allowing imultaneou read and write accee. Two equencer, one for read accee and one for write accee, are hown a well a controller and I/O circuitry. Two reet equencer ignal (RdRt, WrRt are aerted to independently initialize the read and write equencer to point to the firt row. Figure : A bloc diagram of an N x M SAM 34

49 To enable the read operation, the read enable ignal (RdEn mut be aerted. Then, upon the riing edge of the cloc ignal, the read equencer enable ignal (req_en i raied which trigger the equencer cell aociated with the current pointer location to aert it aociated wordline ignal (rwl[]. Thi activate the aociated memory cell and dummy cell, driving the read bitline (rbit[m-:] and the dummy bitline (dumbit, repectively. The equencer cell alo aert a trigger ignal (rtrig[] which i combined with the req_en ignal to activate the next equencer, moving the current pointer location to the next row. The reet of the current equencer i triggered by the aertion of the next wordline. The write operation i imilar except the write bitline (wbit[m-:] are not precharged. Figure : A bloc diagram of a 64x6-b SAM compoed of four 6x6-b SAM ban 35

50 For large N, driving long bitline lead to increaed power diipation and latency. A memory ban tructure can be eaily applied to thi SAM tructure becaue mot of the control ignal are locally generated. Figure how a bloc diagram of a 64x6-b SAM compoed of four 6x6-b SAM ban. The ban are daiy-chained o that the current ban generate a trigger ignal to enable the next ban when a equencer pointer ha reached the lat row in the current ban. In the ubequent cycle, the firt wordline of the next ban i fed bac to reet the trigger ignal aerted in the previou cycle. Tri-tate buffer are ued for I/O circuitry of each ban o that only one of the ban i connected to the common input/output bue. 3.3 Circuit 3.3. Sequencer cell Figure and Figure 3 how a chematic of the equencer cell and it timing diagram. Initially, for the current equencer cell trig[] i high while all other trigger ignal are low. In addition, both triggen and wl[] are low. Upon the aertion of the equencer enable (eq_en, the wordline ignal (wl[] i aerted via a dynamic AND gate. When eq_en i de-aerted, wl[] i de-aerted and a hort pule (triggen i generated by a NOR gate to aert the ubequent trigger ignal (trig[], uing a jam-latch (pule-to-level converter. Notice that trig[] i aerted approximately three gate delay after eq_en goe low to avoid two wordline ignal being activated imultaneouly. The trig[] ignal i reet by the aertion of the wordline ignal wl[] at the next read cycle. 36

51 Figure : A chematic of the equencer cell Figure 3: A timing diagram of the equencer cell To reet the SAM, the trig[] ignal hould be the only aerted trigger ignal. Thu, all equencer cell except the lat equencer cell, hould have a reet NMOS tranitor controlled by the Rt ignal attached to the jam-latch a hown in Figure. In contrat, the lat equencer hould have the reet tranitor attached to the ame ide of the jam-latch a trigen to aert trig[]. 37

52 3.3. Ban equencer In conventional baned memory deign, the current memory ban i enabled directly by the addre decoder. For the propoed SAM deign, however, the active memory ban hould notify the next memory ban a oon a read and/or write operation are completed in the current ban. A pecial ban equencer, hown in Figure 4, i attached to the read/write controller to achieve thi goal. Figure 4: A chematic of the ban equencer It i triggered by the lat trigger ignal (trig_tart of the previou ban and reet by the firt wordline ignal (trig_end of the next ban. The ban trigger ignal (ban_trig i combined with the global read or write enable ignal (RdEn/WrEn to generate the ban enable ignal (ban_en. The timing diagram of the ban 38

53 equencing circuit i depicted in Figure 5. Note that, the firt ban equencer doen t have the reet tranitor o that it i enabled by trig[] from the lat ban while all other ban are diabled by the reet ignal (RdRt/WrRt. Figure 5: A timing diagram of the ban equencer Sequencer cell Three control ignal - precharge, a_en, req_en - are generated by the read controller. Self-reetting potcharge bit-line [3][4] are ued to limit the power diipation and reduce precharge time. Thi, in turn, improve voltage calability by enabling the ue lower upply voltage while till meeting deired acce time. Notice that the controller ha no dependency on the falling edge of the cloc ignal o that read operation can be completed any time within the cloc cycle. In particular, a larger portion of the cloc cycle time can be ued for the read operation plu a ignificant amount of ubequent combinational logic. Notice that lie ome other deign [3][4][47] we ued dummy memory cell to imulate the bit-line 39

54 dicharge timing to implify the control ignal generation. Figure 6 and Figure 7 how the circuit and it correponding timing diagram. Figure 6: A chematic of the read controller 4

55 Figure 7: A timing diagram of read controller Write operation are proceed during the high phae of the cloc and are enabled by the aertion of weq_en when the aociated ban enable ignal (wban_en i aerted. To implement thi, the write controller ue a tandard dynamic flip-flop with input wban_en and large output buffer that drive weq_en. 4

56 3.3.4 Overall read operation ummary Figure 8 ummarize the ignal tranition for a read operation. Each tranition i identified and numbered in increaing order of operation. Tranition with the ame number are concurrent. Figure 8: Signal tranition of the read operation 4

57 3.4 Tet chip and meaurement reult A tet chip wa fabricated in the TSMC.5-m n-well CMOS proce offered through MOSIS. A microphotograph of the tet chip i hown in Figure 9. Three metal layer are ued for the memory core while all five metal layer are ued for I/O pad. The 6x6-b and 64x6-b SAM occupy an area of 97.3m x 3.9m and 366.m x 65.4m, repectively. Table ummarize the characteritic of the proce technology and tet chip. Figure 9: A microphotograph of the tet chip 43

58 Table : Summary of the proce technology and the tet chip The minimum operating core upply voltage wa meaured to be.67v with a correponding maximum frequency of 34MHz. Figure 3 and Figure 3 how the meaured wort-cae power diipation of two SAM (6x6-b and 64x6-b for read and write operation for a variety of upply voltage and frequencie. Note that due to the limitation of available tet equipment, teting at frequencie higher than 4MHz wa not poible. The meaured power diipation for the 64x6-b SAM read operation i 358W (8.95pJ*4MHz at 4MHz and.v and 344W (8.59pJ*4MHz for the 6x6-b SAM. Power diipation for write operation i higher than read operation (46W for the 64x6-b SAM, 396W for the 6x6-b SAM. The average power diipation wa alo meaured uing random vector with imultaneou read and write operation. The meaured average power diipation for the 64x6-b SAM i 57W at 4MHz and.v and 496W for the 6x6-b SAM. The difference in power diipation between thee two SAM are le than 5% for all condition. The independence of energy per operation with repect to frequency in the above graph ugget that there i negligible tatic current in the propoed deign. 44

59 Figure 3: Meaured power diipation of the wort-cae read operation Figure 3: Meaured power diipation of the wort-cae write operation 45

60 For both operation, additional meaurement ugget that approximately one third of the power diipation i conumed by the input and output flip-flop connected to I/O pad. In addition, the meaured tandby current wa negligible (le than.a. 46

61 Chapter 4 OW-POWER COCK GENERATION CIRCUIT USING HARMONIC RESONANCE 4. Motivation ow power ha become a critical feature of many CMOS VSI ytem becaue of the increaing demand for a longer battery life and the high cot of heat removal. Becaue clocing circuitry i typically a ignificant ource of power diipation [], reducing the power conumed by cloc driver and cloc net ha become an important focu. Becaue cloc net are motly capacitive, reonant charging technique that recycle mot of the energy tored in cloc net are increaingly promiing. The implet reonant charging technique ue the flybac circuit hown in Figure 3 to generate a inuoidal cloc ignal []. Although imple, if the NMOS tranitor i driven non-reonantly, which ha generally been the cae, the energy efficiency of thi cloc driver i poor. The blip circuit [3], illutrated in Figure 33, ha much higher efficiency becaue it i all-reonant, i.e., the energy ued to drive every tranitor i recycled. Thi circuit uccefully ha been ued a an efficient power ource for driver of large on-chip ignal line of microproceor [], [4] but can alo be ued to generate two-phae almot-non-overlapping inuoidal cloc. 47

62 Figure 3: A ingle-rail reonant cloc driver (Flybac circuit Figure 33: All-reonant blip driver A common diadvantage of both thee cloc driver i that the output ignal frequency and magnitude depend heavily on the load capacitance Cϕ. Becaue the value of Cϕ may be data-dependent and can thu vary from cycle to cycle, the cloc frequency may alo fluctuate, thereby decreaing performance and increaing deign effort [5]. Of the two driver, the frequency fluctuation in the blip driver i more pronounced becaue of the poitive-feedbac nature of the two output. Another diadvantage of both of thee driver i the need for a ditinct DC power upply V dc whoe value i determined by the load capacitance and the target frequency. atly, while inuoidal cloc ignal are well-uited for pecial adiabatic circuit [6], [7], the low lew rate caue two problem for conventional cloc net. In particular, while adiabatic circuit have pecial circuitry that prevent the low lew 48

63 rate from cauing high hort-circuit current, conventional cloc buffer, flip-flop, and latche do not have thee feature and thu have relatively fat cloc lew rate requirement. Secondly, low lew rate caue increaed variation on effective cloc ew and cloc-output delay which may coniderably affect potential performance and ytem tability. Youni and Knight [8] developed an incremental deign approach for a cla of efficient harmonic rail driver that olve thee problem. Their driver approximate a deired quare wave (with 5% duty cycle by uperpoitioning it firt n harmonic, a illutrated by the 3 rd -order driver in Figure 34. Thee driver, however, require n ditinct DC power upplie, which i prohibitive for mot practical implementation. Figure 34: A harmonic reonant rail driver containing three harmonic term. 49

64 In thi paper, we preent a new ytematic deign approach for n th -order harmonic reonant rail driver that do not require additional DC power upplie. inear networ theory i normally applied to predict the waveform generated by a networ of paive component. Our deign approach applie it for the invere problem. That i, we ue linear networ theory to ytematically derive a networ of paive component that generate n th -order approximation of any given deired cloc waveform with 5% duty cycle that can be expreed a a periodic trapezoid. In thi way, we can achieve approximation of both ideal quare wave and more practical waveform with finite rie and fall time. In particular, we ue linear networ theory to develop a non-iterative method for calculating the component value given the deired waveform hape and the nominal value of the load capacitance. The topology of our propoed driver i baed on a modified current-fed voltage pule-forming networ [9]. Thi networ i traditionally connected to a contant current ource, which internally conume ignificant power. In contrat, we propoe uing a conventional pule generator that conume much le internal power and i readily available in mot ytem. Moreover, it require no additional ditinct DC voltage/current upply and reduce the impact of variation in load capacitance on fluctuation in output magnitude and frequency. Self-ocillating reonant circuit uch a flybac and blip circuit cannot be trivially ynchronized to an external cloc ignal connected to other bloc in the ytem. However, thi can be eaily achieved in our deign becaue it i driven by an external pule generator. 5

65 Our propoed deign approach ha been implemented and teted for frequencie up to 5MHz with variou load capacitance. The wort-cae overall power diipation of the nd -order driver i 9% of fc V at 5MHz with a 97.8pF load. Magnitude and frequency fluctuation due to a broad range of load capacitance variation are oberved to be minimal. In addition, the power efficiency a a function of load capacitance and input pule frequency variation i quantified. The remainder of thi chapter i organized a follow. In Section, we briefly review the theory of waveform ynthei uing current-fed voltage pule-forming networ. Section 3 decribe our ytematic approach to identify the value of all driver component. Then, Section 4 dicue practical implementation, Section 5 preent laboratory meaurement reult, and Section 6 conclude with a dicuion of potential application and future wor. 5

66 5 4. Current-fed voltage pule-forming networ Thi ection review tandard implementation of Fourier erie approximation of periodic trapezoidal waveform uing current-fed voltage pule-forming networ. A trapezoidal-wave v(t, hown in Figure 35, can be defined by the following timedomain equation. Figure 35: A trapezoidal-wave voltage ignal with lope V O /(*T. i integer where ( ( ( ( / /, / /,, ( t v T t v t v t v T t T T T t T V T T t T V T t T t V t v δ δ δ δ δ δ Eq. 3 Becaue the trapezoidal waveform v(t i an odd function, the Fourier erie for v(t contain only ine term a follow:,3, in ( T t b t v π Eq. 4 where

67 b T 4 πt v( tin dt T T V in πδ, where,3, π πδ Eq. 5 In practice, only the firt few term are needed to yield a waveform that cloely approximate an ideal trapezoidal-wave. Notice that the model approximate a quare-wave a become zero. Figure 36: Current-fed voltage pule-forming networ (CFVPN. A current-fed voltage pule-forming networ (CFVPN that can generate an output voltage v(t coniting of the uperpoition of n harmonic i hown in Figure 36 [9]. To analyze v(t, firt aume that witch S open at t and there i no energy initially tored in the networ. The voltage acro the -th C-ection i hown in Eq. 6. ' t v ( t I DC in ' Eq. 6 C C Cacading n uch C-ection in erie yield the following equation for v(t. ' ' v( t n,3, I DC C ' ' in t ' C ' Eq. 7 53

68 With thi analyi, it i traightforward to determine the value of all networ component to approximate a trapezoidal waveform defined by Eq. 4 and Eq. 5. In particular, by comparing Eq. 7 with Eq. 4, the value of b,, C for both quare and trapezoidal waveform can be eaily determined, a ummarized in Table 3. A i, however, thi networ cannot be directly ued a a cloc rail driver becaue none of the capacitance in the networ repreent a load capacitance that reide between the output node and ground. To meet thi requirement, an equivalent networ can be derived through mathematical tranformation of impedance and admittance function of the output, a hown in the following equation. Table 3: Component Value for Networ of Figure 36 Y Z( n ' ' ',3, C n ' ' ( C,3, ( n n Z( ' ' ( i,3, i,3, i C ' i Eq. 8 Eq. 9 Notice that the impedance function Z( ha zeroe at and, which in turn appear a pole in the admittance function Y(. We therefore can rewrite Eq. 9 a follow. 54

69 v( t,3, b πt in T Eq. where A, A C, A C, B C n Eq. and the value for C and are determined a follow: C A A n lim Y lim Z( lim ( Y lim Z( ( n ',3, n,3, C ' Eq. Thi tranformation enable Y( to be generated uing the alternative circuit topology illutrated in Figure 37, which i now uitable a a cloc rail driver becaue it ha an explicit cloc load capacitance C that lie between the output and ground. Figure 37: An equivalent networ of Figure 36 containing a capacitance C that can repreent an on-chip cloc load. To find the value of other component of Figure 37, we can ue a partial fraction expanion of the admittance function Y( [], which i an iterative numerical procedure that provide little inight into the operation of the networ. In the following ection, we preent a characteritic equation that contrain component value o that only deired frequency component are produced in the networ and 55

70 together with a et of linear equation provide a more inightful cloed-form expreion for component value. 4.3 Theoretical analyi of current-fed voltage pule-forming networ There are three tep in our theoretical and algorithmic analyi of the CFVPN and it deired component value. Firt, we convert all of node voltage and branch current equation from time-domain to frequency-domain uing the aplace tranform. Secondly, the branch current equation are implified to find a characteritic equation whoe root are the product of and C of each branch uch that all unwanted frequency component are uppreed. Uing thee root, the third tep i to etablih a et of linear equation that can be found by applying KC on the output node to identify all of the inductor value in the networ. Thee value are combined with the root of the characteritic equation to identify all of the capacitor value. 56

71 57 A. Step : Convert voltage and current equation to frequency domain repreentation To eae the tedium and complexity of olving the integral and differential equation, we ue the aplace tranform to convert voltage and current equation into the frequency-domain. Since two networ hown in Figure 36 and Figure 37 are equivalent, we write the aplace tranform of the output voltage v(t of Figure 37 by approximating Eq. 4 to the n th -order, i.e., T n n b b V n,where ( ( ( Eq. 3 By noting that voltage acro all of the branche in Figure 37 equal v(t, it i traightforward to derive the aplace tranform for each branch current a follow. ( ( ( n n b b C I n C Eq. 4 ( ( ( ( ( ( ( j j b n n b b I n j j n Eq. 5 Ω ( ( ( ( n n b b V C I n Eq. 6 where,for / Ω n C Eq. 7

72 B. Step : Simplify branch current equation and etablih the characteritic equation A hown in Eq. 6, each branch introduce a new free ocillation frequency component at Ω. Thi frequency component i unwanted becaue the output of the networ hould have only n deired harmonic at to (n-. By implifying the branch current equation and finding a condition to uppre the frequency component at Ω, we can etablih the characteritic equation whoe root are n- ditinct Ω value and thu the product of and C. To implify the branch current equation, we can rewrite Eq. 6 a follow. I ( An Ω Ω A Ω B b B n (n bn (n (n Eq. 8 By comparing j th -term, two condition for A j and B j can be found b ( b j Ω ( Aj Ω ( j ( j 3 j ( j ( Aj Bj ( Aj ( j BjΩ B j ( j Aj Bj A ( j B Ω b j j j ( j Eq. 9 Eq. 58

73 59 Eq. 8 can now be implified by replacing B j with -A j and collecting the Ω -term together. Ω Ω Ω ( ( ( ( n A A A A A n A A A A I n n n n Eq. By applying KC on the output node of the networ, the relationhip of branch current can be defined by the equation ( ( ( I I I I C DC n Eq. Becaue no Ω -term exit in the right ide of thi equation, the Ω -term in each branch current mut evaluate to zero, implying the following additional contraint. n j j A Eq. 3 Eq. and Eq. 3 are combined to produce the characteritic equation hown in Eq. 5, ( (( Ω j b j A j j ( ( ( in ( ( j j j j j V j j b A Ω Ω δ π δ π π Eq. 4

74 n j A j n V in π ( j δ π π ( j δ ( j, where j Ω x x Eq. 5 Notice that the numerator of the characteritic equation i an order-(n- polynomial of variable x. The root of thi numerator polynomial, to n-, are the root of the entire characteritic equation, which can be repreented a follow. α Ω Ω, α,, Ω α n Eq. 6 n C. Step 3: Setup linear equation to find a et of and combine with the root of the characteritic equation to find a et of C. Uing Eq. 6, we can ubtitute Ω with the product and in Eq. 4 and ue the reult to implify Eq. a follow. 6

75 6 3 3 (( ( ( ( (3 ( ( ( ( 3 ( ( ( ( ( n n n n n n n n n DC n C DC n n n b n b b n b b b n n b b C I I I I I α α α α α Eq. 7 Comparing both ide of Eq. 7, the linear equation hown in Eq. 8 determine the inductor value,, n-. Note that thee value can be combined with Eq. 6 to calculate the capacitance value C,,C n-. ( ( ( α α α α α α n n n n C n n n Eq. 8

76 A an example, conider the ta of finding the value of all component of the nd - order quare-wave driver for a MHz cloc and a pf load. From Eq. 5, we have x 9 x Eq. 9 x α 5 Uing thi value, we can rewrite Eq. 8 a follow π 6 Eq. 3 By olving thee equation, we find inductor value, 4.7uH and 79.6uH. atly, ince Ω 5 / C, it follow that C 64pF. 4.4 Voltage-pule driven pule-forming networ Even though the CFVPN hown in Figure 37 ha an appropriate configuration for our target application, two problem preclude the networ from being directly applied a a cloc rail driver. Firt, a DC current ource i required to drive the networ that in practice conume large amount of power internally, canceling out the benefit of the CFVPN cloc rail driver. Second, the waveform wing between V / and V / a oppoed to and V required for driving CMOS cloc net. We propoe a unique olution that overcome thee impediment. 6

77 4.4. Voltage-pule driven networ for DC current ource elimination In theory, to eliminate the DC current ource of the CFVPN we can ue the equivalent networ hown in Figure 38, which i triggered by a voltage ource generating a waveform identical to the deired output that provide no current and thu conume no power. However, it i impractical to build a voltage ource that generate a waveform matching the deired n th -order harmonic voltage waveform. Thu, we propoe a olution that ue a more practical voltage pule whoe undeired harmonic are effectively aborbed uing a erie reitor. Figure 38: An Equivalent networ of Figure 37 driven by a voltage pule. Figure 39: Practical approximation of the networ hown in Figure

78 64 The cheapet ource of the voltage pule i a conventional cloc ocillator that, given finite rie and fall time, approximate a trapezoidal wave. The firt n harmonic of the trapezoidal waveform hould match that of the networ. However, the trapezoidal-wave cloc ignal will alo contain higher order harmonic than thoe generated by the networ. Thi will caue ignificant current draw from the voltage ource, reducing the power efficiency of the propoed rail driver. We propoe to reject thee higher order harmonic from the input pule generator by placing a reitor between the input and output of the networ a depicted in Figure 39. To undertand the benefit of adding thi reitor we firt write the impedance function of the original networ a follow. ' ' 3 ' /( 3 / / ( n j j j j Z n o Eq. 3 Note that Eq. 3 i the impedance function of the networ hown in Figure 36 that i the equivalent networ of Figure 37. Then, by adding the reitance R, the overall impedance een by the input pule generator i, ' ' 3 ' /( 3 / / ( ( n j j j R j Z R j Z n o i Eq. 3 The tranfer function A(j of the networ, repreented a the ratio of impedance Z i (j and Z o (j, i a follow:

79 65 real i where, /( / /( / ( ( ( ( ( ' ' ' ' z jz R jz n j j R n j j j Z j Z j A j V j V n n i o i o Eq. 33 where Z o (j jz (. The magnitude and phae hift of thi tranfer function can then be expreed a follow. ( ( ( jz R jz j A z R z j A Eq. 34 Thu, for all frequencie other than the harmonic frequencie (where z i finite, the magnitude approache and the phae hift approache 9º a the value of R increae. Moreover, the magnitude and phae of the tranfer function at each of the n harmonic frequencie can be calculated a follow: / / ( ( lim ( lim ( π π j R j j A z R z j A jz R jz j A z z Eq. 35 where (- for,,,n. Thu, the value of R doe not affect the phae or magnitude of any of the generated harmonic. A more detailed analytical proof of Eq. 35 for the nd -order driver example i preented in the Appendix.

80 Figure 4: Frequency repone of the networ hown in Figure 39 (Vo(/Vi(. Figure 4: The propoed networ with the paraitic reitance of inductor. Figure 4 depict the frequency repone of the nd -order driver for a MHz cloc ignal with different reitance value. It clearly how that no ditortion i incurred at two reonant frequencie (MHz and 3MHz for all reitance value. From thi graph, it eem beneficial to increae the reitance to reject higher harmonic. 66

81 However, the paraitic reitance of the component and wire unfortunately reduce the voltage level of the output ignal a R become larger becaue of the inherent voltage divider preent between the paraitic reitance and R. To undertand thi more clearly, the driver i redrawn in Figure 4 with a paraitic DC reitor of each inductor for the nd -order. Other paraitic component whoe value are negligible compared with component ued are not conidered to implify the analyi. If we apply KC on the output node, we can write the following equation. V ( V i R C By arranging for V o, o ( R C C R C V o ( Eq. 36 Vo ( RC R V ( i RC R C RC Eq. 37 Figure 4 how the magnitude and phae of Vi/Vo at the firt two harmonic frequencie. R 3Ω and R 5Ω are ued for the inductor paraitic reitance, a pecified by the data heet for the inductor ued in our implementation []. Though there i negligible change in the phae, the magnitude decreae from.96 to.69 when R increae from Ω to Ω. Thi i in harp contrat to the ideal networ whoe frequency repone at the harmonic frequencie i not affected by the reitance value a demontrated in Figure 4. Conequently, it i important to ue an adequate reitance value R while maintaining proper voltage level of the output ignal for low power diipation. For driving 97.8pF load capacitance at MHz, our 67

82 tet meaurement demontrate that only 5% of fc V i diipated with a Ω reitance with negligible degradation in output voltage. (a (b Figure 4: Frequency repone of the networ hown in Figure 4 for the firt two harmonic frequencie (a magnitude (b phae. 68

83 4.4. A tan capacitor for a poitive-wing waveform The output of the networ in Figure 39 wing between V / and V / becaue one branch between the output and ground contain a ingle inductor. To redeign the networ to wing from to V we mut introduce a DC offet to the output. We propoe accomplihing thi by introducing a DC offet at the pule generator input and adding a tan capacitance C T in erie with. (a (b Figure 43: DC teady-tate for the networ (a without C T (b with C T. To undertand how a DC offet from the input pule generator affect the networ, two circuit that differ only in an exitence of C T at the DC teady-tate condition are hown in Figure 43. Without C T, the induced output DC voltage i zero becaue the 69

84 7 output and ground node are horted by the branch a hown in Figure 43 (a. A a reult, the DC current V offet /R flow into the networ, creating ignificant unwanted DC power. For the networ hown in Figure 43 (b, the tan capacitance C T connected to in erie induce a matching DC offet voltage at the output node, eliminating the DC current into the networ. Moreover, the introduction of the tan capacitor ha a negligible impact on the overall frequency repone of the rail driver. To ee thi, notice that the impedance function for the branche in Figure 43 that contain can be written a follow. T T T C C j C j j j Z j j Z ( ( Eq. 38 Auming C T i very large, the impedance of Z (j i negligibly affected by C T a follow. T T T T T C j Z j Z j C C j C C j j Z when, ( ( ( >> Eq. 39 In our lab tet, a nf off-the-helf capacitor wa ufficient to achieve the deired DC offet voltage within a.8mhz to 5MHz frequency range. The final propoed voltage-pule driven poitive-wing driver i hown in Figure 44.

85 Figure 44: A voltage-pule driven harmonic reonant rail driver. 4.5 Meaurement The propoed harmonic reonant quare-wave rail driver containing up to four term (i.e. 4 th -order were deigned and teted on a wire-wrap board that included tunable inductor and capacitor. We varied the frequency from.8mhz to 5MHz by etting thee component to theoretical value we calculated uing Eq. 5 and Eq. 8. We then tuned each component to achieve minimum meaured power diipation and compared them with their theoretical value. Teting at higher frequencie wa limited by the tet etup and equipment that are available to the author. Table 4 ummarize the lab meaurement reult for variou configuration. In mot cae, the meaured value of the component are within 7% of the theoretical value. Deviation between the theoretical and tuned capacitance value i larger than for the inductor preumably becaue of the large paraitic capacitance in our wirewrapped board. A reported in Table 4, approximately 9% of the calculated conventional power diipation fc V wa diipated for the nd -order driver at 5MHz to drive 97.8pF load capacitance. 7

86 Table 4: Meaured data of econd, third, and fourth quare-wave harmonic reonant rail driver for variou cloc frequencie and load capacitance. The firt three row are data for driving 97.8pF load capacitance at different cloc frequencie and the lat row how data for different load capacitance at MHz. Theoretical and meaured value of each component are alo hown for comparion. 7

87 Power diipation increae a the order of the driver increae. Thi effect appear to be due to more paraitic component in the tet board. In addition, tuning the circuit for minimum meaured power diipation i increaingly error prone ince more deign variable are involved. Note that a we increae the order of the driver, we mut include additional capacitance uch a C and C for the nd -order driver. However, thi doen t increae the power diipation ignificantly becaue only a mall fraction of the current i drawn from the input pule generator. In particular, the pule generator need to provide only a very mall current ufficient to compenate the energy lo due to the paraitic of the component. Figure 45: Normalized power diipation (P/fCV and tranition time veru reitance R. fcv i the theoretical conventional power diipation to drive load capacitance C. The lat row in Table 4 how the meaurement data of the nd -order driver for different load capacitance at MHz. Reitance value are reduced to achieve % 73

88 riing and falling time of the total cycle time. Power diipation i increaed by approximately 7% for thi cae while riing and falling time are hortened by 3% from the minimal power diipation mode. Thi reult ugget that by changing reitance value, we can control the riing and falling time at the expene of power diipation. Figure 45 illutrate the meaured power diipation a we changed the reitance value R for MHz and pf. The tranition time with Ω reitance wa meaured a n which i % of the total cycle time. Notice that tranition time in Figure 45 are normalized to thi value. At 85Ω, the tranition time drop to 5n (45% while the power diipation increae from 5% to 57.9% of fc V. Figure 46 and Figure 47 how ocillocope trace of the output ignal of the driver for the nd - and 3 rd -order harmonic. To ee how the output ignal i ynchronized, the input pule i alo hown. A FFT-enabled ocillocope trace for the 4 th -order driver output i preented in Figure 48. The figure how that only four harmonic frequencie are preent in the output ignal. Figure 49 preent the trace of the output ignal of the nd -order harmonic driver for MHz frequency. 74

89 Figure 46: A cope trace of output waveform for the nd -order driver at MHz. Figure 47: A cope trace of output waveform for the 3 rd -order driver at MHz. 75

90 Figure 48: A FFT-enabled cope trace of waveform for the 4 th -order driver at MHz. Figure 49: A cope trace of output waveform for the nd -order driver at MHz. 76

91 When the driver i directly connected to the cloc networ, the non-linear characteritic of the tranitor can caue load capacitance variation. To meaure power diipation a a function of the load capacitance variation, we varied C from 3% to 3% of the nominal value while eeping all other component the ame. The power wa then meaured. The reult for a MHz cloc and a pf load capacitance are plotted in Figure 5. Figure 5: Normalized power diipation veru load capacitance (C. All component except C are ept ame a deigned for pf C. Normalized power diipation in the graph i the ratio between the meaured power diipation and fc V. Power diipation at pf i minimum becaue the circuit i deigned to harmonically reonate at thi value. No frequency variation wa noticed for thi range of capacitance a i expected for any externally-driven driver. Unlie the elf-ocillating rail driver whoe frequency varie proportional to the quare root 77

92 of variation in capacitance [5], thi beneficial characteritic of our driver ignificantly increae ytem tability. For capacitance greater than 3%, however, ignificant voltage-level degradation i oberved. On the other hand, if we reduce the load capacitance below 7% of nominal, the power diipation increae rapidly becaue current from the input pule generator motly charge the load capacitance intead of it being charged reonantly. In addition to the increaed power diipation by the load capacitance variation, the phae hift between the input pule and the generated output caue a cloc jitter. To quantify thi effect, we meaured the delay time of the output with repect to the input pule at the Vdd/ voltage level while varying the load capacitance C from - 3% to 3% of the nominal value. The meaurement reult i hown in Figure 5. Figure 5: Cloc jitter veru load capacitance (C. 78

93 We oberved cloc jitter ranging from -47n to 43n for MHz cloc frequency. Thi relatively high cloc jitter can be compenated by an increaed cloc cycle time. Therefore, 5% to % performance lo i expected for application with high load capacitance variation. Figure 5: Normalized power diipation veru cloc cycle variation. Another experiment wa carried out to meaure power diipation a a function of frequency change of the input pule generator. We varied the frequency of the input pule generator (f cl from -% to % from it nominal value then the power wa meaured. Figure 5 how the meaurement reult of the power diipation. At the nominal frequency (MHz, the normalized power diipation i 4% of fc V. When f cl i reduced by % from it nominal value, the power diipation i increaed to 39% of fc V. 36% of fc V wa meaured when f cl i increaed by 79

94 %. For % frequency fluctuation, the power diipation i increaed to 5% of fc V. 8

95 Chapter 5 CASE STUDY: OW-POWER FIR FITER Now that the low power circuit technique have been propoed for two major power conumption component cloc networ and memory bloc - of portable DSP application, a low-power FIR filter deign i preented in thi chapter a one way to combine thee technique in real DSP application. 5. Motivation FIR (Finite Impule Repone filtering i one of the mot commonly ued function in DSP and communication ytem [4][44]. Some example include pectral haping, matched filtering, noie rejection, channel equalization, and wavelet decompoition/recontruction [44]. It operation i achieved by convolving input data ample with the deired impule repone of the filter. The output y[n] of an N- tap FIR filter (Figure 53 i given by the weighted um of the latet N input data ample. N y [ n] h[ ] x[ n ] Eq. 4 The weight h[] in the above expreion are the filter coefficient. The number of tap (N and the coefficient value are derived o a to atify the deired filter repone in term of paband ripple and topband attenuation. The mot ubiquitou hardware implementation for FIR filter i to ue a generic DSP architecture a 8

96 hown in Figure 54 where two memory bloc (coefficient and data and a multiplyaccumulate (MAC unit are ynchronouly reued to mimic a tapped delay line implementation a hown in Figure 53. Two memory bloc can be acceed imultaneouly. Thi i imilar to the Harvard architecture employed in mot programmable DSP [38][68]. Figure 53: A tapped delay line implementation of N-tap FIR filter. Figure 54: A generic DSP architecture for FIR filter. 8

97 For an N-tap FIR filter, the latet N data ample are required. Therefore, the latet N ample need to be tored in the data memory. After every output computation, a new data ample i read and tored in the data memory, and the oldet data ample i removed. Data ample x[] for the current computation become data ample x[-] for the next computation. The exiting data ample thu need to be hifted by one poition for every output. The power diipated due to thi data movement can be minimized by uing a circular buffer [68] where the pointer to the data i moved intead of moving the data. For programmable FIR filter, the coefficient memory can be configured a a circular buffer a well. It i traightforward to deign a circular buffer by combining a conventional SRAM array with an addre equencing logic, which i often implemented by up/down counter. Thi approach i quite wateful both in power and peed apect if the accee to the memorie in the target application, uch a FIR filtering, are all equential a demontrated in Chapter 3. In particular, a N become large, the power diipated by the driver of the addre line and decoder grow ignificantly. A cloc networ i another major power conumption ource of FIR filter deign. In particular, the number of tap required increae ignificantly in modern DSP ytem to achieve high overall reolution with relatively imple analog component. Thi lead to a high-frequency ytem cloc even if the ampling rate of input and output data i low. For example, the ampling rate of typical CD audio ignal i 44.KHz. To deign a low-pa filter with the pecification of 4.KHz (-4.KHz tranition band and 8dB topband attenuation, approximately tap are required 83

98 [6] thu the ytem cloc frequency ha to be increaed to 5.9MHz. Becaue the ytem cloc i ditributed throughout the ytem (on-chip and off-chip, total power diipation of the ytem ignificantly grow by the increae of the cloc frequency. An on-chip P can be ued to multiply the ytem cloc to generate a fater on-chip cloc. However, typical multiplication factor of P range from two to five []. In addition, the power diipation of a P can eaily eclipe the power aving from reducing the ytem cloc frequency. Thi chapter preent a novel FIR filter deign where the on-chip cloc ignal i locally generated from the elf-reetting memory o that the ytem cloc can be ept at the ample rate. The local cloc ignal automatically top a oon a filter operation are completed. Moreover, by utilizing an exiting elf-reetting control ignal of a memory bloc for a local cloc ignal, there i virtually no circuit overhead. Thi i in harp contrat to conventional technique uch a cloc gating and toppable cloc. The equential acce memory preented in Chapter 3 i ued for coefficient and data memory bloc to further reduce power diipation of memory accee. Cloc ditribution networ cheme are alo dicued to maximize the power aving benefit of the reonant cloc rail driver preented in Chapter 4. 84

99 5. Architecture Figure 55 how a bloc diagram of our propoed FIR filter. A low ample cloc (phi i connected only to I/O regiter. Figure 55: A bloc diagram of a N-tap FIR filter A fater operation cloc (lphi i locally generated from the data memory completion ignal and connected to datapath pipeline regiter and memorie. A typical implementation include a cloc ditribution networ on the local cloc to reduce ew and lew rate. The cloc frequency of lphi i determined by the latency of the read accee. Therefore, the datapath hould be deigned uch that the critical path 85

100 latency of the datapath i le than the read acce latency of the data memory. However, thi contraint can be relaxed by inerting delay line on the local cloc net to increae the cloc cycle arbitrarily. To minimize the power diipation of decoding and driving addre line, equential acce memorie are ued both for data memory and coefficient memory. To eep trac of the number of operation to be performed, a controller i integrated into the datapath. All other datapath bloc including I/O regiter, a controller and a MAC (multiply-accumulate are deigned uing a tandard ASIC deign flow under timing contraint taen from the memory deign imulation. 5.3 Timing and circuit 5.3. ocal cloc generation The mot unique feature of the propoed FIR filter i to ue the elf-reetting ignal from a equential acce memory a a cloc ignal for datapath bloc. Figure 7 i redrawn in Figure 56 with the new ignal complete. For a ynchronou deign where the memory i triggered by the ytem cloc, elf-reetting circuit technique are mainly ued to mae a equence of micro-operation in line o that there i no wate in power diipation. Therefore, completion detection i not required a long a a cloc cycle time i longer than the read acce latency. 86

101 Figure 56: A timing diagram of the read operation of SAM with a newly added complete ignal. To enable the memory to trigger read accee without an external cloc, the complete ignal i fed bac to the memory cloc input port. Both edge of the complete ignal are aerted by the elf-reetting circuit operation dicued in Chapter. The local cloc ignal lphi i imply a delayed ignal of complete. Typically, the phae difference between complete and lphi include cloc tree inertion delay. All micro-operation of each read acce are triggered by the riing edge of lphi Controller A defined in Eq. 4, every tep of FIR filtering tart with read accee to the data and coefficient tored in memorie and finihe with a MAC operation. The initial read acce can be triggered eaily by utilizing a riing edge of the ytem cloc. However, determining the lat acce, and thu the completion of operation, 87

102 require additional logic. For a 64-tap FIR filter, one 6-bit counter and imple tate machine can implement thi function a preented in Figure 57. A timing diagram of the controller i hown in Figure 58. Figure 57: A bloc diagram of the 64-tap FIR filter controller. Figure 58: A timing diagram of the 64-tap FIR filter controller. lrenc and lrend are read enable ignal for the coefficient memory and data memory repectively. The pphi ignal which i generated at the riing edge of the ytem cloc phi, reet the counter and aert lrenc and lrend. The up-counter eep incrementing the counter value at each riing edge of lphi. When the counter value 88

103 cnt reache 6 and 63, lrenc and lrend are reet to zero repectively. When thee ignal are low at the riing edge of lphi, no read acce i performed, and lphi top toggling thereafter. For each output of FIR filtering, one redundant read acce to the data memory i performed becaue the tarting location of the data memory ha to be incremented by one a hown in Figure 59. Data from thi additional acce i dicarded and not forwarded to the datapath bloc. Figure 59: A tarting location of the data memory for each ample Read operation We have hown how to generate the local cloc ignal (lphi and read enable ignal (lrenc, lrend in previou ubection. To ee how thee ignal are ued for read operation, a timing diagram for read operation i preented in Figure 6. The initial read acce (x[i-63] i triggered by the pphi ignal when the global read enable (ren ignal i high. Thi initial read acce then create the firt riing edge of lphi. A dicued in the previou ubection, the lphi ignal repeat toggling until the lrend ignal goe to low. The read controller for the ingle ban equential acce memory hown in Figure 6 i lightly modified to trigger the initial read acce at the riing 89

104 edge of pphi. Figure 6 how the modified circuit diagram for the req_en ignal. Other read control ignal are not affected by the new timing. Figure 6: A timing diagram of read accee for the 64-tap FIR filter. Figure 6: A modified read controller of the SAM to enable an initial read acce by pphi 9

105 For a multi-ban equential acce memory, only one of the ban i active for a given cycle. Conequently the complete ignal from the active ban toggle while other are held high. Therefore, all of thee ignal are combined by an AND gate to get the local cloc ignal that repeat toggling during the whole operation. A bloc diagram of the four-ban example and it timing diagram are depicted in Figure 6 and Figure 63. To implify the timing diagram, each ban i aumed to have two row. Figure 6: A bloc diagram of the data memory to generate the local cloc ignal lphi. 9

106 Figure 63: A timing diagram of Figure 6. Each ban i aumed to have only two row to implify the diagram. The tart addre of read accee can reide in any of the ban for a given ample. The read controller for a ingle ban equential acce memory hown in Figure 6 mut be modified becaue all of the ban will be triggered by the pphi ignal otherwie. Note that the ban location of the tart addre at the beginning of the operation i tored in the ban_enq ignal of Figure 4. By adding one NMOS tranitor with a gate connected to ban_enq in the newly added NMOS tac of Figure 6, the initial triggering of read accee can be eaily achieved. Figure 64 how the modified circuit diagram of the read controller for the multi-ban equential acce memory. 9

107 Figure 64: A modified read controller of the multi-ban SAM to enable an initial read acce by pphi Write operation Regardle of the tap ize of a FIR filter, only one write operation for the data memory i required per ample. A equential acce memory for FIR filtering i baically the ame a a FIFO configuration. Therefore, the oldet ample tored in the data memory during the previou period i replaced with the new ample at the 93

108 beginning of the current period. Concurrent read and write to/from the ame location uually require additional bypaing logic or a prolonged latency. To avoid thi overhead, read accee tart from the oldet ample to the new ample wherea the new data i written into the data memory at the beginning of the current period. The pphi ignal i ued to trigger the write operation a hown in Figure 65. Figure 65: A timing diagram of write operation Overall timing for FIR filtering An overall timing diagram of FIR filtering i hown in Figure 66. Multiplier input (m/m and the accumulator output (acc are pipeline regiter output triggered by the lphi ignal. The FIR filter output (FIRout i latched by the I/O regiter at the ubequent riing edge of phi. coef and data are output of the coefficient memory and the data memory, repectively. Note that the final value of the accumulator i available at the lat riing edge of lphi. 94

109 Figure 66: An overall timing diagram of FIR filtering 95

110 5.4 Iue with the cloc ditribution networ The cloc networ i one of the major ource of power diipation in DSP application. In particular, capacitance aociated with the cloc networ at the ytem level are typically higher than on-chip cloc networ. Therefore, by reducing the ytem cloc frequency from the operating rate to the ample rate, a ignificant amount of energy can be aved. The reonant cloc rail driver preented in Chapter 4 can ave energy even further by driving the cloc networ reonantly. In addition, it ha been demontrated that energy efficiency of the reonant cloc rail driver increae a cloc frequency decreae. In thi ection, we will preent iue related with the cloc ditribution networ to minimize cloc power diipation Global and hierarchical cloc tree Since the cloc ignal to trigger operation for each FIR filter i locally generated from the memory, it i inherent to ue hierarchical cloc tree generation. For each FIR filter, a mall cloc tree whoe root i the complete ignal of the data memory i generated to meet timing requirement uch a cloc ew and tranition time. At a chip level, another cloc tree i inerted to minimize cloc ew from the ytem cloc node to each leaf node, which i the ytem cloc input of the FIR filter. A hierarchical cloc tree cheme i depicted in Figure

111 Figure 67: Hierarchical cloc tree generation for FIR filter ban. One of the advantage of thi configuration i the mall leaf node capacitance of the ytem cloc. Cloc tree of high-peed cloc are localized in each bloc o that cloc tree overhead i maller a compared with a global cloc tree generation. (Figure 68 Contrary to conventional approache in which a high-peed cloc i ditributed acro a whole chip, there i no timing relationhip between thee local cloc ignal. Therefore, the cloc tree overhead to minimize cloc ew and cloc lew rate can be ignificantly reduced. 97

112 Figure 68: Conventional cloc tree generation with global cloc ditribution Reonant and conventional cloc driver To enure fat cloc tranition in conventional ytem, buffer are inerted to drive large load capacitance of a cloc net [3][]. There are two common cloc driving cheme: ingle driver and ditributed buffer [57]. In the ingle driver cheme a hown in Figure 69 (a, a chain of cacaded buffer with a very large buffer at the end i ued at the cloc ource, and no buffer are ued elewhere; in the ditributed buffer cheme a hown in Figure 69 (b, intermediate buffer are inerted in variou part of the cloc tree. The ingle driver cheme ha the advantage of avoiding adjutment of intermediate buffer delay a in the ditributed buffer cheme. Often in conjunction with thi cheme, wire izing i ued to reduce the cloc phae delay. Widening the branche that are cloe to the cloc ource can alo 98

113 reduce ew caued by aymmetric cloc tree load and wire width deviation [75][55]. The ditributed buffer cheme i often preferred over the ingle buffer cheme a the chip ize increae due to it flexibility and mall cloc phae delay [9][3]. For power minimization in a cloc tree, the ditributed buffer cheme i alo preferred due to it capability to hut down ubytem by replacing buffer with logic gate. (a (b Figure 69: Two cloc tree driving cheme: (a Single driver cheme (b ditributed buffer cheme The reonant cloc rail driver wor in a imilar way a the ingle driver cheme. The cloc driver can drive any arbitrary capacitance for a given lew rate and total load capacitance during the deign procedure. Therefore, no intermediate cloc buffer i needed. To reduce RC delay reulting from the relatively long wire length from a cloc pin to leaf node, cloc wire can be expanded at the expene of increaed load capacitance. However, the cot i coniderably maller than a conventional ingle driver cheme becaue of the high energy efficiency of the 99

114 reonant cloc rail driver. Conidering the low cloc frequency requirement and hierarchical cloc tree configuration of the propoed deign, the reonant cloc rail driver can be eaily applied. In addition, hutting down ubytem uch a FIR filter ban i controlled by control ignal rather than gated cloc ignal. When the read enable ignal i not aerted, read accee to the data memory i not triggered, and thu the local cloc ignal i automatically diabled. Figure 7: Serpentine cloc ditribution networ. Figure 7: Balanced H-tree cloc ditribution networ. Several cloc routing topologie can be applied for the reonant cloc rail driver. Figure 7 how one poible topology where each load i driven by a ingle pointto-point wire and length are matched uing a erpentine tructure [7]. Thi

115 tructure i relatively imple to deign and ha virtually zero ew for identical load a long a coupling capacitance are inignificant. A ymmetric H-tree [5][5] hown in Figure 7 ha much maller cloc capacitance than the erpentine tructure with a negligible cloc ew for ideal load ditribution. However, tuning tree topologie to drive highly non-uniform load with low ew can be much more difficult.

116 5.5 Implementation Two prototype 6-b FIR filter - 64-tap and 6-tap - were deigned and implemented in the TSMC.5-µm n-well CMOS proce. A tandard ASIC deign flow wa generally applied to generate datapath bloc including MAC and controller uing a tandard-cell library from Artian. A timing contraint for the datapath bloc wa et to 4.n at.5v to meet the read acce latency of the memory. A Wallace tree multiplier and carry looahead adder tructure are ued for MAC. The 6-tab and 64-tab FIR filter occupy 39.6-µm x 496.-µm and µm x µm, repectively. Table 5 ummarize the characteritic of the prototype FIR filter. ayout plot for the two FIR filter are preented in Figure 7 and Figure 73. Table 5: Summary of the proce technology and the tet chip

117 Figure 7: A layout plot of the 6-tap FIR filter. 3

118 Figure 73: A layout plot of the 64-tap FIR filter. 4