LOW INPUT CURRENT HIGH GAIN SPLIT DARLINGTON OPTOCOUPLERS

Size: px

Start display at page:

Download "LOW INPUT CURRENT HIGH GAIN SPLIT DARLINGTON OPTOCOUPLERS"

Rudolph Johns
6 years ago
Views:

1 6N DESCRIPTION The 6N/9 and / optocouplers consist of an AlGaAs LED optically coupled to a high gain split darlington photodetector. The split darlington configuration separating the input photodiode and the first stage gain from the output transistor permits lower output saturation voltage and higher speed operation than possible with conventional darlington phototransistor optocoupler. In the dual channel devices, /HCPL7, an integrated emitter base resistor provides superior stability over temperature. The combination of a very low input current of.5 ma and a high current transfer ratio of % makes this family particularly useful for input interface to MOS, CMOS, LSTTL and EIA RSC, while output compatibility is ensured to CMOS as well as high fanout TTL requirements. An internal noise shield provides exceptional common mode rejection of kv/µs. An improved package allows superior insulation permitting a 4 V working voltage compared to industry standard V. FEATURES Low current.5 ma Superior CTR% Superior CMR kv/µs Double working voltage4v RMS CTR guaranteed 7 C U.L. recognized (File # E97) Dual Channel APPLICATIONS Digital logic ground isolation Telephone ring detector EIARSC line receiver High common mode noise line receiver µp bus isolation Current loop receiver N/C V CC + 7 V B V F _ 6 V O N/C 4 5 GND 6N / + V CC V F _ 7 V _ 6 V V F GND / ABSOLUTE MAXIMUM RATINGS (No derating required up to 5 C) Parameter Symbol Value Units Storage Temperature T STG 55 to +5 C Operating Temperature T OPR 4 to +5 C Lead Solder Temperature TSOL 6 for sec C EMITTER DC/Average Forward Input Current IF (avg) ma Peak Forward Input Current (5% duty cycle, ms P.W.) I F (pk) 4 ma Peak Transient Input Current (!" µs P.W., pps) I F (trans). A Reverse Input Voltage V R 5 V Input Power Dissipation PD 5 mw DETECTOR Average Output Current I O (avg) 6 ma EmitterBase Reverse Voltage (6N and ) V EB.5 V Supply Voltage, Output Voltage (6N, ).5 to 7 V CC, V (, ) O.5 to V Output power dissipation P D Fairchild Semiconductor Corporation DS /5/ OF

2 6N ELECTRICAL CHARACTERISTICS (T A = to 7 C unless otherwise specified.) INDIVIDUAL COMPONENT CHARACTERISTICS Parameter Test Conditions Symbol Device Min Typ** Max Unit EMITTER T A =5 C)..7 V F All V Input Forward Voltage (I F =.6 ma).75 (T A = 5 C, I R = µa) Input Reverse Breakdown Voltage BV R All 5. V Temperature coefficient of forward voltage (I F =.6 ma) (#V F /#T A ) All. mv/ C DETECTOR (I F = ma, V O = V CC = V). µa I OH Logic high output current (I F = ma, V O = V CC = 7 V) 6N. 5 (I F =.6 ma, V O = Open) 6N.4.5 (V CC = V) Logic low supply I CCL ma (I F = I F =.6 ma, V CC = V). (V O = V O = Open, V CC = 7 V) (I F = ma, V O = Open) 6N.5 Logic high supply (V CC = V) I CCH µa (I F = I F = ma, V CC = V). (V O = V O = Open, V CC = 7 V) ** All typicals at T A = 5 C OF /5/ DS

3 6N TRANSFER CHARACTERISTICS (TA = to 7 C Unless otherwise specified) Parameter Test Conditions Symbol Device Min Typ** Max Unit COUPLED (I F =.5 ma, V O =.4 V, V CC = 4.5 V) 4 5 % Current transfer ratio (I F =.6 ma, V O =.4 V, V CC = 4.5 V) CTR 5 (Notes,) 5 % (I F =.6 ma, V O =.4 V, V CC = 4.5 V) 6N 5 % (I F =.5 ma, I O = ma, V CC = 4.5 V)..4 (I F =.6 ma, I O = ma, V CC = 4.5 V)..4 Logic low output voltage (I F = 5 ma, I O = 5 ma, V CC = 4.5 V)..4 output voltage V OL V (Note ) (I F = ma, I O = 4 ma, V CC = 4.5 V)..4 (I F =.6 ma, I O = 4. ma, V CC = 4.5 V) 6N..4 ** All typicals at T A = 5 C DS /5/ OF

4 6N SWITCHING CHARACTERISTICS (T A = to 7 C unless otherwise specified., V CC = 5 V) Parameter Test Conditions Symbol Device Min Typ** Max Unit (R L = 4.7 k$, I F =.5 ma) T A = 5 C 4 5 (R L = 4.7 k$, I F =.5 ma) T A = 5 C Propagation delay (R L = 7 $, I F = ma) µs time to logic low T A = 5 C. (Note ) (Fig. ) (R L = 7 $, I F = ma) T PHL T A = 5 C. (R L =. k$, I F =.6 ma) 5 6N T A = 5 C.5 (R L =. k$, I F =.6 ma) 5 T A = 5 C (R L = 4.7 k$, I F =.5 ma) (R L = 4.7 k$, I F =.5 ma) T A = 5 C (R L = 7 $, I F = ma) Propagation delay T A = 5 C. 7 time to logic high T PLH (R L = 7 $, I F = ma) 5 µs (Note ) (Fig. ) T A = 5 C (R L =. k$, I F =.6 ma) 6N / (R L =. k$, I F =.6 ma) T A = 5 C 6N 7 / 6 Common mode (I F = ma, %V CM % = V PP ) 6N transient T A = 5 C, (R L =. k$) (Note ) (Fig. ) immunity at logic high CM H Common mode (I F =.6 ma, %V CM % = V PP, R L =. k$) 6N transient T A = 5 C (Note ) (Fig. ) immunity at logic low CM L ,, V/µs,, V/µs ** All typicals at T A = 5 C 4 OF /5/ DS

5 6N ISOLATION CHARACTERISTICS (T A = to 7 C Unless otherwise specified) Characteristics Test Conditions Symbol Min Typ** Max Unit (Relative humidity = 45%) Inputoutput (T A = 5 C, t = 5 s) insulation leakage current (V IO = VDC) I IO. µa (Note ) Withstand insulation test voltage (RH! 5%, T A = 5 C) (Note 4) ( t = min.) V ISO 5 V RMS Resistance (input to output) (Note 4) (V IO = 5 VDC) R IO $ Capacitance (input to output) (Note 4,5) (f = MHz) C IO.6 pf InputInput (RH! 45%, V II = 5 VDC) (Note 6) Insulation leakage current t = 5 s, (/7 only) I II.5 µa InputInput Resistance (V II = 5 VDC) (Note 6) (/7 only) R II $ InputInput Capacitance (f = MHz) (Note 6) (/7 only) C II. pf ** All typicals at T A = 5 C NOTES. Current Transfer Ratio is defined as a ratio of output collector current, IO, to the forward LED input current, IF, times %.. Pin 7 open. (6N and only). Common mode transient immunity in logic high level is the maximum tolerable (positive) dvcm/dt on the leading edge of the common mode pulse signal, VCM, to assure that the output will remain in a logic high state (i.e., &. V). Common mode transient immunity in logic low level is the maximum tolerable (negative) dvcm/dt on the trailing edge of the common mode pulse signal, VCM, to assure that the output will remain in a logic low state (i.e., '. V). 4. Device is considered a two terminal device: Pins,, and 4 are shorted together and Pins 5, 6, 7 and are shorted together. 5. For dual channel devices, C IO is measured by shorting pins and or pins and 4 together and pins 5 through shorted together. 6. Measured between pins and shorted together, and pins and 4 shorted together. DS /5/ 5 OF

6 6N ELECTRICAL CHARACTERISTICS (T A = 5 C unless otherwise specified) Current Limiting Resistor Calculations R (NonInvert) = V DD V DF V OL I F R (Invert) = V DD V OH V DF I F R = V DD = V OLX (@ I L I ) I L INPUT OUTPUT Where: V DD Input Supply Voltage V DD Output Supply Voltage V DF Diode Forward Voltage V OL Logic Voltage of Driver V OH Logic Voltage of Driver I F Diode Forward Current V OLX Saturation Voltage of Output Transistor I L Load Current Through Resistor R I Input Current of Output Gate CMOS 5 V 74XX 74LXX 74SXX 74LSXX 74HXX R ($) R ($) R ($) R ($) R ($) R ($) R ($) R ($) CMOS 5 V INV. 5 CMOS NONINV. V INV XX NONINV. INV. 74LXX NONINV INV. 74SXX NONINV. INV. 6 74LSXX NONINV. INV. 74HXX NONINV. INV. Fig. Resistor Values for Logic Interface V DD V DD V DD 7 R IN 7 R IN R 6 OUT R 6 OUT Fig. NonInverting Logic Interface Fig. Inverting Logic Interface 6 OF /5/ DS

7 CURRENT TRANSFER RATIO CTR (%) CTR CURRENT TRANSFER RATIO % TIME, T (µs) TIME µs FORWARD CURRENT IF (ma) FORWARD LTAGE VF (V) LOW INPUT CURRENT 6N Fig. 4 LED Forward Current vs. Forward Voltage Fig. 5 LED Forward Voltage vs. Temperature.5 IF =.6 ma TA = 5 C.4 T A = 7 C... T A = 4 C. TA = C FORWARD LTAGE V F (V) TEMPERATURE T A ( C) Fig. 6 Nonsaturated Rise and Fall Times vs. Load Resistance (6N / Only) Fig. 7 Nonsaturated Rise and Fall Times vs. Load Resistance ( / Only) T A = 5 C tf t f tr tr IF ADJUSTED FOR L = V. R L LOAD RESISTANCE (k$). R L LOAD RESISTANCE (k$) Fig. Current Transfer Ratio vs. Forward Current (6N / Only) V CC = 5 V =.4 V 6 Fig. 9 Current Transfer Ratio vs. Forward Current ( / Only) 5 V CC = 5 V =.4 V 4 TA = 7 C T A = 5 C T A = 5 C T A = C 4 TA = 7 C T A = C TA = 4 C T A = 4 C.. I F FORWARD CURRENT (ma). I F FORWARD CURRENT ma DS /5/ 7 OF

8 IOOUTPUT CURRENT ma LOW INPUT CURRENT 6N Fig. Output Current vs Output Voltage (6N / Only) Fig. Output Current vs Output Voltage ( / Only) IO OUTPUT CURRENT (ma) V CC = 5V 5 ma 4.5 ma 4 ma.5 ma ma.5 ma ma.5 ma ma 6 4 T A = 5 C VCC = 5. V I F = 4. ma IF =.5 ma IF = 4.5 ma IF = 5. ma I F =. ma IF =.5 ma I F =. ma IF =.5 ma IF =. ma IF =.5 ma V O OUTPUT LTAGE (V) V OOUTPUT LTAGE V Fig. Output Current vs. Input Diode Forward Current (6N / Only) VCC = 5. V =.4 V Fig. Output Current vs Input Diode Forward Current ( / Only) IO OUTPUT CURRENT (ma) V CC = 5 V V O =.4 V TA = 5 C T A = 7 C IO OUTPUT CURRENT ma TA = 5 C T A = 4 C TA = C T A = 4 C.... I F INPUT DIODE FORWARD CURRENT (ma) IF INPUT DIODE FORWARD CURRENT ma 4. Fig. 4 Logic Low Supply Current vs. Input Diode Forward Current (6N / Only) Fig. 5 Logic Low Supply Current vs. Input Diode Forward Current ( / Only) ICCL LOGIC LOW SUPPLY CURRENT (ma) VCC = 5 V VCC = V ICCL LOGIC LOW SUPPLY CURRENT ma T A = 5 C VCC = V VCC = 7 V I F FORWARD CURRENT (ma).. I F INPUT DIODE FORWARD CURRENT ma OF /5/ DS

9 6N Fig. 6 Propagation Delay vs. Input Diode Forward Current (6N / Only) Fig. 7 Propagation Delay vs. Input Diode Forward Current ( / Only) VCC = 5 V 6 V CC = 5 V tp PROPAGATION DELAY µs 5 4 (t PHL) R L =. kω or 4.7 kω (tplh) RL = 4.7 kω tp PROPAGATION DELAY µs 5 4 (t PHL) R L =. kω or 4.7 kω (tplh) RL = 4.7 kω (tplh) RL =. kω (t PLH) R L =. kω I F INPUT DIODE FORWARD CURRENT ma 4 6 I F INPUT DIODE FORWARD CURRENT ma Fig. Propagation Delay to Logic Low vs. Pulse Period (6N / Only) Fig. 9 Propagation Delay to Logic Low vs. Pulse Period ( / Only) tphl PROPAGATION DELAY to LOGIC LOW µs T INPUT PULSE PERIOD ms IF =.5 ma RL = 4.7 kω 6N IF =.6 ma RL =. kω T A = 5 C... tphl PROPAGATION DELAY to LOGIC LOW µs IF =.5 ma RL = 4.7 kω IF =.6 ma RL =.kω... T INPUT PULSE PERIOD ms T A = 5 C Fig. Propagation Delay vs. Temperature (6N / Only) Fig. Propagation Delay vs. Temperature ( / Only) 5 : I F =.6 ma, R L =. k : IF =.5 ma, R L = 4.7 k 5 : I F =.6 ma, R L =. k : IF =.5 ma, RL = 4.7 k tp PROPAGATION DELAY µs 4 t PLH () t PHL () t PHL () t PLH () tp PROPAGATION DELAY µs 4 t PLH () t PHL () t PHL () t PLH () T A TEMPERATURE ( C) T A TEMPERATURE ( C) DS /5/ 9 OF

10 6N Pulse Generator I tr = 5ns F Z O = 5 $ % D.C. I/ f< ( s I F Monitor R m + V F 4 Noise Shield 7 6 V CC V B 5 GND R L. µf +5 V V O C L = 5 µf* Pulse Generator tr = 5ns Z O = 5 $ % DUTY CYCLE I/f < µs IF MONITOR Rm I F + VF VF + Noise Shield VCC RL. µf V V GND +5 V C L = 5 µf* Test Circuit for 6N, Test Circuit for and I F 5 V.5 V.5 V V OL TPHL TPLH *Includes Probe and Fixture Capacitance Fig. Switching Time Test Circuit V FF B A I F + V F Noise Shield 4 7 V CC V B V 6 O 5 GND R L. µf +5 V V FF B I F A + VF VF + 4 Noise Shield VCC RL V V GND. µf +5 V + V CM Pulse Gen V CM + Pulse Gen Test Circuit for 6N and Test Circuit for and V CM V 9% 9% % % V t r t f Switch at A : I F = ma 5 V Switch at B : I F =.6 ma L Fig. Common Mode Immunity Test Circuit OF /5/ DS

11 6N Package Dimensions (Through Hole) Package Dimensions (Surface Mount) 4 PIN ID. 4.9 (9.9).7 (9.4) PIN ID (6.6).5 (6.5).7 (6.6).5 (6.5).9 (9.9).7 (9.4) SEATING PLANE. (5.).5 (.9).7 (.7).45 (.4). (.5) MIN.54 (.9). (.5).7 (.7).45 (.4). (.5) MIN. (7.6) TYP.6 (.4). (.). (.56).6 (.4).6 (.4). (.). (.54) TYP 5 MAX. (7.6) TYP. (.54) TYP. (.56).6 (.4).45 [.4].5 (.) MIN.45 (.) MIN Lead Coplanarity :.4 (.) MAX Package Dimensions (.4 Lead Spacing) 4 PIN ID..7 (6.6).5 (6.5) (9.9).7 (9.4) SEATING PLANE. (5.).5 (.9).7 (.7).45 (.4).4 (.) MIN.54 (.9). (.5) NOTE All dimensions are in inches (millimeters). (.56).6 (.4).6 (.4). (.). (.54) TYP.4 (.6) TYP to5 DS /5/ OF

12 ORDERING INFORMATION 6N Order Entry Option Identifier Description R.R Opto Plus Reliability Conditioning S.S Surface Mount Lead Bend SD.SD Surface Mount; Tape and reel W.W.4 Lead Spacing QT Carrier Tape Specifications ( D Taping Orientation) 4.9 ±.. ±.5 4. ±.. ±. 4. ±. Ø.55 ±.5.75 ±.. ±.. ±. 7.5 ±. 6. ±.. MAX. ±. Ø.6 ±. User Direction of Feed Corporate Headquarters North American Sales European Sales QT Optoelectronics QT Optoelectronics Quality Technologies Deutschland GmbH 6 North Mary Avenue 6775 Addison Rd.,Suite MaxHuberStrasse Sunnyvale, CA 946 Addison, TX 75 D577 Ismaning, Germany (4) 744 Phone (97) 447 Phone 49 [] 9/96..5 Phone (4) 74 Fax (97) Fax 49 [] 9/ Fax European Sales Asia/Pacific Sales European Sales QT Optoelectronics QT Optoelectronics Quality Technologies (U.K) Ltd. Le Levant B6, 6th Floor, Prebendal Court, Oxford Road, rue du Nouveau Bercy East Wing, Wisma Tractors Aylesbury, Buckinghamshire F9477CHARENTONLE PONT Cedex Jalan SS6/, Subang Jaya HP9EY United Kingdom FRANCE 475 Petaling Jaya 44 [] 96/ Phone [] Phone Selangor Darul Eshan, Malaysia 44 [] 96/9.4. Fax [] Fax 6/7547 Phone 6/76 Fax OF /5/ DS

13 DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Fairchild Semiconductor Corporation DS /5/ OF

HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS

HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS DESCRIPTION The, /6 single-channel and /6 dual-channel optocouplers consist of a 5 nm AlGaAS LED, optically coupled to a very high speed integrated photodetector logic gate with a strobable output. This