HCPL0600, HCPL0601, HCPL0611, HCPL0637, HCPL0638, HCPL0639 High Speed-10 MBit/s Logic Gate Optocouplers (0.48) (0.25) (0.

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1 HCPL, HCPL, HCPL, HCPL7, HCPL8, HCPL9 High Speed- MBit/s Logic Gate Optocouplers Single Channel: HCPL, HCPL, HCPL Dual Channel: HCPL7, HCPL8, HCPL9 Features Compact SO8 package Very high speed- MBit/s Superior CMR Logic gate output Strobable output (single channel devices) Wired OR-open collector U.L. recognized (File # E97) VDE approval pending Applications Ground loop elimination LSTTL to TTL, LSTTL or 5-volt CMOS Line receiver, data transmission Data multiplexing Switching power supplies Pulse transformer replacement Computer-peripheral interface Package Dimensions SEATING PLANE Pin Description. (5.).8 (.). (.). (.).9 (.8) January 7 The HCPLXX optocouplers consist of an AlGaAS LED, optically coupled to a very high speed integrated photo-detector logic gate with a strobable output (single channel devices). The devices are housed in a compact small-outline package. This output features an open collector, thereby permitting wired OR outputs. The HCPL, HCPL and HCPL output consists of bipolar transistors on a bipolar process while the HCPL7, HCPL8, and HCPL9 output consists of bipolar transistors on a CMOS process for reduced power consumption. The coupled parameters are guaranteed over the temperature range of - C to +85 C. An internal noise shield provides superior common mode rejection. tm. (.). (.). (.5). (.).8 (.). (.5). (.8). (.8).5 (.7) TYP Lead Coplanarity :. (.) MAX Note: All dimensions are in inches (millimeters). (.9). (5.9) Fairchild Semiconductor Corporation

2 N/C + V F _ N/C 5 GND Single-channel circuit drawing (HCPL, HCPL and HCPL) TRUTH TABLE (Positive Logic) Input Enable Output H H L L H H H L H L L H H* NC* L* L* NC* H* *Dual channel devices or single channel devices with pin 7 not connected. A.µF bypass capacitor must be connected between pins 8 and 5. (See note ) 8 7 V CC V E V O + V F V F + 5 GND Dual-channel circuit drawing (HCPL7, HCPL8 and HCPL9) 8 7 V CC V V

3 Absolute Maximum Ratings (No derating required up to 85 C) Symbol Parameter Value Units T STG Storage Temperature - to +5 C T OPR Operating Temperature - to +85 C EMITTER I F DC/Average Forward Input Current (each channel) Recommended Operating Conditions Single Channel 5 ma Dual Channel V E Enable Input Voltage Single Channel 5.5 V Not to exceed VCC by more than 5mV V R Reverse Input Voltage (each channel) 5. V P I Power Dissipation Single Channel 5 mw Dual Channel DETECTOR V CC Supply Voltage 7. V ( minute max) I O Output Current (each channel) Single Channel 5 ma Dual Channel 5 V O Output Voltage (each channel) 7. V P O Collector Output Power Dissipation Single Channel 85 mw Dual Channel 85 Symbol Parameter Min. Max. Units I FL Input Current, Low Level 5 µa I FH Input Current, High Level *. 5 ma V CC Supply Voltage, Output V V EL Enable Voltage, Low Level Single Channel only.8 V V EH Enable Voltage, High Level Single Channel only. V CC V T A Operating Temperature C N Fan Out (TTL load) Single Channel 8 TTL Loads Dual Channel 5 R L Output Pull-up K Ω *.ma is a guard banded value which allows for at least % CTR degradation. Initial input current threshold value is 5.mA or less

4 Electrical Characteristics (T A = - C to +85 C Unless otherwise specified.) Individual Component Characteristics Symbol Parameter Test Conditions Min. Typ.** Max. Unit EMITTER V F Input Forward Voltage I F = ma.8 V T A = 5 C.75 B VR Input Reverse Breakdown Voltage I R = µa 5. V VF/ TA Input Diode Temperature Coefficient I F = ma -.5 mv/ C DETECTOR I CCH High Level Supply Current I F = ma, V E =.5 V V CC = 5.5V Single Channel ma Dual Channel 5 I CCL Low Level Supply Current I F = ma, V E =.5 V Single Channel ma V CC = 5.5V Dual Channel I EL Low Level Enable Current V CC = 5.5V, V E =.5V Single Channel -. ma I EH High Level Enable Current V CC = 5.5V, V E =.V Single Channel -. ma V EH High Level Enable Voltage V CC = 5.5V, I F = ma Single Channel. V V EL Low Level Enable Voltage V CC = 5.5V, I F = ma () Single Channel.8 V Switching Characteristics (T A = - C to +85 C, V CC = 5 V, I F = 7.5 ma Unless otherwise specified.) Symbol AC Characteristics Test Conditions Device Min. Typ. Max. Unit T PLH Propagation Delay Time to Output High Level R L = 5Ω, C L = 5pF () T A = 5 C All 75 ns (Fig. ) T PHL Propagation Delay Time R L = 5Ω, C L = 5pF () T A = 5 C All 5 75 ns to Output Low Level (Fig. ) T PHL -T PLH Pulse Width Distortion R L = 5Ω, C L = 5pF (Fig. ) All 5 ns t r Output Rise Time (-9%) R L = 5Ω, C L = 5pF (5) (Fig. ) Single Ch 5 ns Dual Ch 7 t f Output Fall Time (9-%) R L = 5Ω, C L = 5pF () (Fig. ) Single Ch ns Dual Ch 5 t ELH t EHL CM H CM H Enable Propagation Delay Time to Output High Level Enable Propagation Delay Time to Output Low Level I F = 7.5mA, V EH =.5V, R L = 5Ω, C L = 5pF (7) (Fig. ) I F = 7.5mA, V EH =.5V, R L = 5Ω, C L = 5 pf (8) (Fig. ) HCPL HCPL HCPL HCPL HCPL HCPL Common Mode Transient Immunity (at Output High Level) Common Mode Transient Immunity (at Output Low Level) R L = 5Ω, T A =5 C, I F = ma, V OH (Min.) =. V (9) (Fig., ) R L = 5Ω, T A =5 C, I F = 7.5mA, V OL (Max.) =.8 V () (Fig., ) V CM = V HCPL HCPL7 V CM = 5V HCPL 5 HCPL8 V CM =,V HCPL, HCPL9 5, V CM = V HCPL HCPL7 V CM = 5V HCPL 5 HCPL8 V CM =,V HCPL, HCPL9 5, ns ns V/µs V/µs

5 Transfer Characteristics (T A = - C to +85 C Unless otherwise specified.) Symbol DC Characteristics Test Conditions Min. Typ.** Max. Unit µa. V I OH High Level Output Current V CC = 5.5V, V O = 5.5 V, I F = 5µA, V E =.V () V OL Low Level Output Voltage V CC = 5.5V, I F = 5mA, V E =.V, I OL = ma () I FT Input Threshold Current V CC = 5.5V, V O =.V, V E =.V, I OL = ma 5 ma Isolation Characteristics (T A = - C to +85 C Unless otherwise specified.) Symbol Characteristics Test Conditions Min. Typ.** Max. Unit I I-O Input-Output Insulation Leakage Current ** All typical values are at V CC = 5 V, T A = 5 C Relative humidity = 5%, T A = 5 C, t = 5s, V I-O = VDC () V ISO Withstand Insulation Test Voltage R H < 5%, T A = 5 C, I I-O µa, t = min. () Notes:. The V CC supply to each optoisolator must be bypassed by a.µf capacitor or larger. This can be either a ceramic or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible to the package V CC and GND pins of each device.. Enable Input No pull up resistor required as the device has an internal pull up resistor.. t PLH Propagation delay is measured from the.75 ma level on the HIGH to LOW transition of the input current pulse to the.5v level on the LOW to HIGH transition of the output voltage pulse.. t PHL Propagation delay is measured from the.75 ma level on the LOW to HIGH transition of the input current pulse to the.5v level on the HIGH to LOW transition of the output voltage pulse. 5. t r Rise time is measured from the 9% to the % levels on the LOW to HIGH transition of the output pulse.. t f Fall time is measured from the % to the 9% levels on the HIGH to LOW transition of the output pulse. 7. t ELH Enable input propagation delay is measured from the.5v level on the HIGH to LOW transition of the input voltage pulse to the.5v level on the LOW to HIGH transition of the output voltage pulse. 8. t EHL Enable input propagation delay is measured from the.5v level on the LOW to HIGH transition of the input voltage pulse to the.5v level on the HIGH to LOW transition of the output voltage pulse. 9. CM H The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the high state (i.e., V OUT >. V). Measured in volts per microsecond (V/µs).. CM L The maximum tolerable rate of fall of the common mode voltage to ensure the output will remain in the low output state (i.e., V OUT <.8 V). Measured in volts per microsecond (V/µs).. Device considered a two-terminal device: Pins,, and shorted together, and Pins 5,,7 and 8 shorted together..* µa 75 V RMS R I-O Resistance (Input to Output) V I-O = 5V () Ω C I-O Capacitance (Input to Output) f = MHz (). pf 5

6 Typical Performance Curves (HCPL, HCPL and HCPL only) IF - FORWARD CURRENT (ma) ITH - INPUT THRESHOLD CURRENT (ma) Fig. Forward Current vs. Input Forward Voltage T A = 7 C T A = 5 C T A = 85 C V F - FORWARD VOLTAGE (V) Fig. Input Threshold Current vs. Temperature V CC = 5V V O =.V R L = 5Ω R L = KΩ T A - TEMPERATURE ( C) T A = - C T A = C Fig. Output Voltage vs. Forward Current Vo - OUTPUT VOLTAGE (V) IOH - HIGH LEVEL OUTPUT CURRENT (µa) 5 R L = kω R L = 5Ω 5 I F - FORWARD INPUT CURRENT (ma) Fig. High Level Output Current vs. Temperature 8 T A - TEMPERATURE ( C) T A = 5 C V CC = 5V V O = V CC = 5.5V V E = V I F = 5 µa

7 Typical Performance Curves (HCPL, and HCPL and HCPL only) VOL - LOW LEVEL OUTPUT VOLTAGE (V) TP - PROPAGATION DELAY (ns) Fig. 5 Low Level Output Voltage vs. Temperature V = 5.5V CC V E = V I F = 5mA I O = ma I O =.ma I O =.8mA I O = 9.mA T A - TEMPERATURE ( C) Fig. 7 Propagation Delay vs. Temperature I F = 7.5mA t PLH R L = kω t PLH R L = 5Ω t PHL RL = 5Ω & kω T A - TEMPERATURE ( C) Fig. Low Level Output Current vs. Temperature T A - TEMPERATURE ( C) IOL - LOW LEVEL OUTPUT CURRENT (ma) TP - PROPAGATION DELAY (ns) V E = V V OL =.V I F = -5mA I F = 5mA Fig. 8 Propagation Delay vs. Pulse Input Current T A = 5 C t PLH R L = kω t PLH R L = 5Ω t PHL RL = 5Ω & kω I F - PULSE INPUT CURRENT (ma) 7

8 Typical Performance Curves (HCPL, HCPL and HCPL only) PWD - PULSE WIDTH DISTORTION (ns) Fig. 9 Typical Enable Propagation Delay vs. Temparature te - ENABLE PROPAGATION DELAY (ns) V EH = V V EL = V I F = 7.5mA t ELH R L = kω t ELH R L = 5Ω t EHL RL = 5Ω & kω T A - TEMPERATURE ( C) T A - TEMPERATURE ( C) Fig. Typical Pulse Width Distortion vs. Temperature I F = 7.5mA R L = kω T A - TEMPERATURE ( C) Fig. Typical Rise and Fall Time vs. Temperature tf - FALL TIME (ns) R L = 5Ω 8 I F = 7.5mA t r R L = kω t r R L = 5Ω t f R L = 5Ω & kω 8

9 Typical Performance Curves (HCPL7, HCPL8 and HCPL9 only) IF - FORWARD CURRENT (ma) IOH - HIGH LEVEL OUTPUT CURRENT (na) VOL - LOW LEVEL OUTPUT VOLTAGE (V) Fig. Input Forward Current vs. Forward Voltage T A = 85 C T A = C T A = - C T A = C T A = 5 C V F - FORWARD VOLTAGE (V) Fig. High Level Output Current vs. Ambient Temperature V O = V CC = 5.5V V E = V (Single Channel Only) I F = 5 µa T A - AMBIENT TEMPERATURE ( C) Fig. Low Level Output Voltage vs. Ambient Temperature Fig. Input Threshold Current vs. Ambient Temperature Fig. 5 Low Level Output Current vs. Ambient Temperature V = 5.5V CC V E = V (Single Channel Only) I F = 5mA I O =.ma I O =.8mA I O = 9.mA I O = ma ITH - INPUT THRESHOLD CURRENT (ma) IOL - LOW LEVEL OUTPUT CURRENT (ma) PWD - PULSE WIDTH DISTORTION (ns) V CC = 5.5V V O =.V R L = kω R L = 5Ω R L = kω T A - AMBIENT TEMPERATURE ( C) V = 5.5V CC V E = V (Single Channel Only) V OL =.V I F = 5-5mA 7 5 T A - AMBIENT TEMPERATURE ( C) Fig. 7 Pulse Width Distortion vs. Ambient Temperature I F = 7.5mA RL = kω RL = kω RL = 5Ω. T A - AMBIENT TEMPERATURE ( C) T A - AMBIENT TEMPERATURE ( C) 9

10 Typical Performance Curves (HCPL7, HCPL8 and HCPL9 only) TP - PROPAGATION DELAY (ns) 8 I F = 7.5mA Fig. 8 Propagation Delay vs. Ambient Temperature t PLH RL = kω t PHL RL = 5Ω, kω, kω t PLH RL = kω t PLH RL = 5Ω T A - AMBIENT TEMPERATURE ( C) Fig. 9 Rise and Fall Times vs. Ambient Temperature T A - AMBIENT TEMPERATURE ( C) tr - RISE TIME (ns) I F = 7.5mA t r - RL = kω t f - RL = 5Ω, kω, kω t r - RL = kω t r - RL = 5Ω 7 5 tf - FALL TIME (ns)

11 Pulse Gen. t f = t r = 5 ns Z O = 5 Ω Input Monitor (I F) 7Ω +5V Pulse Gen. Z O = 5 Ω t f = t r = 5 ns Dual Channel I F V CC 8 V CC 8 Input.µf 7 R L Monitoring Bypass Node 7 Output (V O) C L R M GND 5 5 GND Test Circuit for HCPL, HCPL and HCPL Pulse Generator tr = 5ns Z O= 5Ω 7.5 ma V CC GND Input Monitor (V E).µf bypass Test Circuit for HCPL7, HCPL8 and HCPL9 R L C L +5V Output (V O) Input (V E ) tehl Output (V O) Input (I F) t PHL Output (V O) Output (V ) O Fig. Test Circuit and Waveforms for t PLH, t PHL, t r and t f. Fig. Test Circuit t EHL and t ELH.. V.5 V R L +5 V.µF Bypass Output V O Monitoring Node C L* telh tf.5 V 9% % t PLH tr I F = 7.5 ma I =.75 ma F.5 V

12 VCM V 5V VO VO.5 V V FF A B I F Peak V CC GND V CM Pulse Gen Switching Pos. (A), I F= V O (Min) V O (Max) µf bypass Test Circuit for HCPL, HCPL, and HCPL Switching Pos. (B), I F= 7.5 ma 5Ω +5V Output (V O) Fig. Test Circuit Common Mode Transient Immunity (HCPL, HCPL and HCPL) CM H CM L

13 VCM V Peak.V VO VO.5 V I F V FF B A Switching Pos. (A), I = V O (Min) Dual Channel F V CC 8 V O (Max) Switching Pos. (B), I = 7.5 ma Fig. Test Circuit Common Mode Transient Immunity (HCPL7, HCPL8 and HCPL9) 7 GND 5 V CM + Pulse Generator Z O = 5 Ω F R L.µF Bypass Test Circuit for HCPL7, HCPL8 and HCPL9 +.V Output V O Monitoring Node CM H CM L

14 8-Pin Small Outline. (.). (.5).75 (.99).55 (.9).5 (.7)

15 Ordering Information Option Order Entry Identifier Description No Suffix HCPL Shipped in tubes (5 units per tube) V HCPLV VDE88 (pending approval) R HCPLR Tape and Reel (5 units per reel) RV HCPLRV VDE88 (pending approval), Tape and Reel (5 units per reel) R HCPLR Tape and Reel (5 units per reel) RV HCPLRV VDE88 (pending approval), Tape and Reel (5 units per reel) Marking Information Definitions Fairchild logo Device number V 5 VDE mark (Note: Only appears on parts ordered with VDE option See order entry table) One digit year code, e.g., 5 Two digit work week ranging from to 5 Assembly package code X YY S 5

16 Carrier Tape Specifications Reflow Profile C 8. ±..5 ±.. ±.5 Ø.5 MIN. MAX. ±..75 ±. 5.5 ±.5 8. ±.. ±. 5. ± MAX. ±. 8 7 Ø.5 ±./- User Direction of Feed C >5 C = Sec Time above 8 C = 9 Sec.8 C/Sec Ramp up rate Sec Time (s)

17 FAIRCHILD SEMICONDUCTOR TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx ActiveArray Bottomless Build it Now CoolFET CROSSVOLT DOME EcoSPARK E CMOS EnSigna FACT FAST FASTr FPS FRFET FACT Quiet Series GlobalOptoisolator GTO HiSeC I C i-lo ImpliedDisconnect IntelliMAX ISOPLANAR LittleFET MICROCOUPLER MicroFET MicroPak MICROWIRE MSX MSXPro Across the board. Around the world. The Power Franchise Programmable Active Droop DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms OCX OCXPro OPTOLOGIC OPTOPLANAR PACMAN POP Power7 PowerEdge PowerSaver PowerTrench QFET QS QT Optoelectronics Quiet Series RapidConfigure RapidConnect µserdes ScalarPump SILENT SWITCHER SMART START SPM Stealth SuperFET SuperSOT - SuperSOT - SuperSOT -8 SyncFET TCM TinyBoost TinyBuck TinyPWM TinyPower TinyLogic TINYOPTO TruTranslation UHC. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. UniFET VCX Wire Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I 7

HCPL0600, HCPL0601, HCPL0611, HCPL0630, HCPL0631, HCPL0661 High Speed-10 MBit/s Logic Gate Optocouplers

HCPL0600, HCPL0601, HCPL0611, HCPL0630, HCPL0631, HCPL0661 High Speed-10 MBit/s Logic Gate Optocouplers HCPL, HCPL, HCPL, HCPL, HCPL, HCPL High Speed- MBit/s Logic Gate Optocouplers Single Channel: HCPL, HCPL, HCPL Dual Channel: HCPL, HCPL, HCPL Features Compact SO8 package Very high speed- MBit/s Superior