RFP12N10L. Features. 12A, 100V, Ohm, Logic Level, N-Channel Power MOSFET. Ordering Information. Symbol. Packaging. Data Sheet April 2005
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1 RFP12N1L Data Sheet April 25 12A, 1V,.2 Ohm, Logic Level, N-Channel Power MOSFET These are N-Channel enhancement mode silicon gate power field effect transistors specifically designed for use with logic level (5V) driving sources in applications such as programmable controllers, automotive switching and solenoid drivers. This performance is accomplished through a special gate oxide design which provides full rated conduction at gate biases in the 3V to 5V range, thereby facilitating true on-off power control directly from logic circuit supply voltages. Formerly developmental type TA9526. Ordering Information PART NUMBER PACKAGE BRAND RFP12N1L TO-22AB F12N1L NOTE: When ordering, include the entire part number. Features 12A, 1V r DS(ON) =.2Ω Design Optimized for 5V Gate Drives Can be Driven Directly from QMOS, NMOS, TTL Circuits Compatible with Automotive Drive Requirements SOA is Power-Dissipation Limited Nanosecond Switching Speeds Linear Transfer Characteristics High Input Impedance Majority Carrier Device Related Literature - TB334 Guidelines for Soldering Surface Mount Components to PC Boards Symbol D G S Packaging JEDEC TO-22AB DRAIN (TAB) SOURCE DRAIN GATE 25 Fairchild Semiconductor Corporation RFP12N1L Rev. B1
2 Absolute Maximum Ratings T C = 25 o C, Unless Otherwise Specified RFP12N1L UNITS Drain to Source Voltage (Note 1) V DS 1 V Drain to Gate Voltage (R GS = 1MΩ) (Note 1) V DGR 1 V Continuous Drain Current I D 12 A Pulsed Drain Current (Note 3) I DM 3 A Gate to Source Voltage V GS ±1 V Maximum Power Dissipation P D 6 W Above T C = 25 o C, Derate Linearly W/ o C Operating and Storage Temperature T J, T STG -55 to 15 o C Maximum Temperature for Soldering Leads at.63in (1.6mm) from Case for 1s T L 3 Package Body for 1s, See Techbrief T pkg 26 CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. T J = 25 o C to 125 o C. RFP12N1L o C o C Electrical Specifications T C = 25 o C, Unless Otherwise Specified Zero Gate Voltage Drain Current I DSS PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BV DSS I D = 25µA, V GS = V V Gate to Threshold Voltage V GS(TH) V GS = V DS, I D = 25µA (Figure 7) 1-2 V V GS = V T C = 125 o C µa V DS = 8V µa Gate to Source Leakage Current I GSS V GS = 1V, V DS = V na Drain to Source On Resistance (Note 2) r DS(ON) I D = 12A, (Figures 5, 6) Ω Input Capacitance C ISS V GS = V, V DS = 25V, f = 1MHz pf (Figure 8) Output Capacitance C OSS pf Reverse-Transfer Capacitance C RSS pf Turn-On Delay Time t d(on) I D = 6A, V DD = 5V, R G = 6.25Ω, ns Rise Time t r (Figures 9, 1, 11) ns Turn-Off Delay Time t d(off) ns Fall Time t f ns Thermal Resistance Junction to Case R θjc TO oc/w Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage (Note 2) V SD I SD = 6A V Diode Reverse Recovery Time t rr I SD = 4A, di SD /dt = 5A/µs ns NOTES: 2. Pulsed: pulse duration = 8µs max, duty cycle = 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. 25 Fairchild Semiconductor Corporation RFP12N1L Rev. B1
3 RFP12N1L Typical Performance Curves Unless Otherwise Specified POWER DISSIPATION MULTIPLIER I D, DRAIN CURRENT (A) 1 1 OPERATION IN THIS REGION IS LIMITED BY r DS(ON) I D (MAX) CONTINUOUS DC OPERATION 6W T C = 25 o C TJ = MAX RATED T C, CASE TEMPERATURE ( o C) V DS, DRAIN TO SOURCE VOLTAGE (V) 1 FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. FORWARD BIAS OPERATING AREA I D, DRAIN CURRENT (A) PULSE DURATION = 8µs DUTY CYCLE.5% T C = 25 o C V GS = 1V V DS, DRAIN TO SOURCE VOLTAGE (V) 5V 4V 3V 2V I D(ON), ON-STATE DRAIN CURRENT (A) V DS = 1V PULSE DURATION = 8µs DUTY CYCLE.5% 125 o C 25 o C -4 o C -4 o C V GS, GATE TO SOURCE VOLTAGE (V) 125 o C 5 FIGURE 3. SATURATION CHARACTERISTICS FIGURE 4. TRANSFER CHARACTERISTICS r DS(ON), DRAIN TO SOURCE ON RESISTANCE (Ω) o C 25 o C -4 o C PULSE DURATION = 8µs DUTY CYCLE.5% I D, DRAIN CURRENT (A) NORMALIZED DRAIN TO SOURCE ON RESISTANCE , I D = 12A PULSE DURATION = 8µs DUTY CYCLE.5% T J, JUNCTION TEMPERATURE ( o C) FIGURE 5. DRAIN TO SOURCE ON RESISTANCE vs DRAIN CURRENT FIGURE 6. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 25 Fairchild Semiconductor Corporation RFP12N1L Rev. B1
4 RFP12N1L Typical Performance Curves Unless Otherwise Specified (Continued) NORMALIZED GATE THRESHOLD VOLTAGE (V) V DS = V GS I D = 25µA C, CAPACITANCE (pf) V GS = V, f = 1MHz C ISS = C GS + C GD C RSS = C GD C OSS C DS + C GD C ISS C OSS.6 C RSS T J, JUNCTION TEMPERATURE ( o C) V DS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 7. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE FIGURE 8. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE DRAIN TO SOURCE VOLTAGE (V) BV DSS R L = 8.33Ω I G (REF) =.56mA GATE V DD = BV DSS SOURCE V VOLTAGE DD = BV DSS.75BV DSS.5BV DSS.25BV DSS DRAIN SOURCE VOLTAGE 2 I G (REF) I G (ACT) 8 IG (REF) t, TIME (µs) I G (ACT) GATE TO SOURCE VOLTAGE (V) NOTE: Refer to Fairchild Applications Notes AN7254 and AN726 FIGURE 9. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms t ON t d(on) t OFF t d(off) R L t r t f V DS 9% 9% + V DD - 1% 1% V GS R GS DUT V GS 1% 5% PULSE WIDTH 9% 5% FIGURE 1. SWITCHING TIME TEST CIRCUIT FIGURE 11. RESISTIVE SWITCHING WAVEFORMS 25 Fairchild Semiconductor Corporation RFP12N1L Rev. B1
5 RFP12N1L Test Circuits and Waveforms (Continued) V DS R L V DD Q g(tot) V DS V GS = 1V V GS + Q g(5) V DD - V GS I G(REF) DUT V GS = 1V Q g(th) I G(REF) FIGURE 12. GATE CHARGE TEST CIRCUIT FIGURE 13. GATE CHARGE WAVEFORMS 25 Fairchild Semiconductor Corporation RFP12N1L Rev. B1
6 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx ActiveArray Bottomless CoolFET CROSSVOLT DOME EcoSPARK E 2 CMOS EnSigna FACT FACT Quiet Series DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms FAST FASTr FPS FRFET GlobalOptoisolator GTO HiSeC I 2 C i-lo ImpliedDisconnect Across the board. Around the world. The Power Franchise Programmable Active Droop IntelliMAX ISOPLANAR LittleFET MICROCOUPLER MicroFET MicroPak MICROWIRE MSX MSXPro OCX OCXPro OPTOLOGIC OPTOPLANAR PACMAN POP Power247 PowerEdge PowerSaver PowerTrench QFET QS QT Optoelectronics Quiet Series RapidConfigure RapidConnect µserdes SILENT SWITCHER SMART START 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Datasheet Identification Product Status Definition SPM Stealth SuperFET SuperSOT -3 SuperSOT -6 SuperSOT -8 SyncFET TinyLogic TINYOPTO TruTranslation UHC UltraFET UniFET VCX Advance Information Preliminary No Identification Needed Formative or In Design First Production Full Production This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I15
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FC58AP Single P-Channel Logic Level PowerTrench MOSFET -3V, -A, 5mΩ General escription This P-Channel Logic Level MOSFET is produced using Fairchild's advanced PowerTrench process. It has been optimized
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3V P-Channel PowerTrench MOSFET October 2 General Description This P-Channel MOSFET is a rugged gate version of Fairchild Semiconductor s advanced PowerTrench process. It has been optimized for power management
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400V N-Channel MOSFET General Description These N-Channel enhancement mode power field effect transistors are produced using Fairchild s proprietary, planar, DMOS technology. This advanced technology has
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500V N-Channel MOSFET November 2001 General Description These N-Channel enhancement mode power field effect transistors are produced using Fairchild s proprietary, planar, DMOS technology. This advanced
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60V N-Channel MOSFET May 2001 QFET TM General Description These N-Channel enhancement mode power field effect transistors are produced using Fairchild s proprietary, planar stripe, DMOS technology. This
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