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2 Low Power Consumption Wide Common-Mode and Differential Voltage Ranges Low Input Bias and Offset Currents Output Short-Circuit Protection Low Total Harmonic Distortion % Typ description/ordering information SLOS080J SEPTEMBER 978 REVISED MARCH 2005 Low Noise V n = 8 nv/ Hz Typ at f = khz High Input Impedance... JFET Input Stage Internal Frequency Compensation Latch-Up-Free Operation High Slew Rate... 3 V/µs Typ Common-Mode Input Voltage Range Includes V CC+ The JFET-input operational amplifiers in the TL07x series are similar to the TL08x series, with low input bias and offset currents and fast slew rate. The low harmonic distortion and low noise make the TL07x series ideally suited for high-fidelity and audio preamplifier applications. Each amplifier features JFET inputs (for high input impedance) coupled with bipolar output stages integrated on a single monolithic chip. The C-suffix devices are characterized for operation from 0 C to 70 C. The I-suffix devices are characterized for operation from 40 C to 85 C. The M-suffix devices are characterized for operation over the full military temperature range of 55 C to 25 C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2005, Texas Instruments Incorporated POST OFFICE BOX DALLAS, TEXAS 75265

3 SLOS080J SEPTEMBER 978 REVISED MARCH 2005 description/ordering information (continued) TA 0 C to 70 C VIOmax AT 25 C ORDERING INFORMATION PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING Tube of 50 TL07CP TL07CP PDIP (P) Tube of 50 TL072CP TL072CP PDIP (N) Tube of 25 TL074CN TL074CN Tube of 75 TL07CD Reel of 2500 TL07CDR TL07C Tube of 75 TL072CD SOIC (D) Reel of 2500 TL072CDR TL072C 0 mv Tube of 50 TL074CD Reel of 2500 TL074CDR TL074C SOP (NS) Reel of 2000 TL074CNSR TL074 Reel of 2000 TL07CPSR TL07 SOP (PS) Reel of 2000 TL072CPSR T072 Reel of 2000 TL072CPWR T072 TSSOP (PW) Tube of 90 TL074CPW Reel of 2000 TL074CPWR T074 Tube of 50 TL07ACP TL07ACP PDIP (P) Tube of 50 TL072ACP TL072ACP PDIP (N) Tube of 25 TL074ACN TL074ACN 6 mv 3 mv SOIC (D) Tube of 75 Reel of 2500 Tube of 75 Reel of 2500 Tube of 50 Reel of 2500 TL07ACD TL07ACDR TL072ACD TL072ACDR TL074ACD TL074ACDR 07AC 072AC TL074AC SOP (PS) Reel of 2000 TL072ACPSR T072A SOP (NS) Reel of 2000 TL074ACNSR TL074A PDIP (P) Tube of 50 TL07BCP TL07BCP Tube of 50 TL072BCP TL072BCP PDIP (N) Tube of 25 TL074BCN TL074BCN SOIC (D) Tube of 75 Reel of 2500 Tube of 75 Reel of 2500 Tube of 50 Reel of 2500 TL07BCD TL07BCDR TL072BCD TL072BCDR TL074BCD TL074BCDR 07BC 072BC TL074BC SOP (NS) Reel of 2000 TL074BCNSR TL074B Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at 2 POST OFFICE BOX DALLAS, TEXAS 75265

4 description/ordering information (continued) SLOS080J SEPTEMBER 978 REVISED MARCH 2005 ORDERING INFORMATION TA VIOmax AT 25 C PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING Tube of 50 TL07IP TL07IP PDIP (P) Tube of 50 TL072IP TL072IP PDIP (N) Tube of 25 TL074IN TL074IN Tube of 75 TL07ID 40 C to 85 C 6 mv Reel of 2500 TL07IDR TL07I 55 C to 25 C SOIC (D) Tube of 75 Reel of 2500 Tube of 50 Reel of 2500 TL072ID TL072IDR TL074ID TL074IDR TL072I TL074I CDIP (JG) Tube of 50 TL072MJGB TL072MJGB 6 mv CFP (U) Tube of 50 TL072MUB TL072MUB LCCC (FK) Tube of 55 TL072MFKB TL072MFKB CDIP (J) Tube of 25 TL074MJB TL074MJB 9 mv CFP (W) Tube of 25 TL074MWB TL074MWB LCCC (FK) Tube of 55 TL074MFKB TL074MFKB Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at POST OFFICE BOX DALLAS, TEXAS

5 SLOS080J SEPTEMBER 978 REVISED MARCH 2005 OFFSET N IN IN+ V CC TL07, TL07A, TL07B D, P, OR PS PACKAGE (TOP VIEW) V CC+ OUT OFFSET N2 TL072, TL072A, TL072B D, JG, P, PS, OR PW PACKAGE (TOP VIEW) OUT IN IN+ V CC OUT IN IN+ V CC TL072 U PACKAGE (TOP VIEW) V CC+ 2OUT 2IN 2IN+ V CC+ 2OUT 2IN 2IN+ TL074A, TL074B D, J, N, NS, OR PW PACKAGE TL D, J, N, NS, PW, OR W PACKAGE (TOP VIEW) OUT IN IN+ V CC+ 2IN+ 2IN 2OUT OUT 4IN 4IN+ V CC 3IN+ 3IN 3OUT TL07 FK PACKAGE (TOP VIEW) TL072 FK PACKAGE (TOP VIEW) TL074 FK PACKAGE (TOP VIEW) IN IN+ OFFSET N V CC OFFSET N2 V CC+ OUT IN IN+ OUT VCC IN+ V CC 2OUT 2IN IN+ V CC+ 2IN+ 2IN IN 2OUT OUT 3OUT 4OUT 3IN 4IN IN+ V CC 3IN+ No internal connection symbols OFFSET N TL07 TL072 (each amplifier) TL074 (each amplifier) IN+ IN + OUT IN+ IN + OUT OFFSET N2 4 POST OFFICE BOX DALLAS, TEXAS 75265

6 SLOS080J SEPTEMBER 978 REVISED MARCH 2005 schematic (each amplifier) VCC+ IN+ IN 64 Ω 28 Ω OUT 64 Ω C 8 pf 080 Ω 080 Ω VCC ÁÁÁÁÁ OFFSET N ÁÁÁ OFFSET N2 TL07 Only All component values shown are nominal. COMPONENT COUNT COMPONENT TYPE TL07 TL072 TL074 Resistors Transistors JFET Diodes 2 4 Capacitors 2 4 epi-fet 2 4 Includes bias and trim circuitry POST OFFICE BOX DALLAS, TEXAS

7 SLOS080J SEPTEMBER 978 REVISED MARCH 2005 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage (see Note ): V CC V V CC V Differential input voltage, V ID (see Note 2) ±30 V Input voltage, V I (see Notes and 3) ±5 V Duration of output short circuit (see Note 4) Unlimited Package thermal impedance, θ JA (see Notes 5 and 6): D package (8 pin) C/W D package (4 pin) C/W N package C/W NS package C/W P package C/W PS package C/W PW package (8 pin) C/W PW package (4 pin) C/W U package C/W Package thermal impedance, θ JC (see Notes 7 and 8): FK package C/W J package C/W JG package C/W W package C/W Operating virtual junction temperature, T J C Case temperature for 60 seconds: FK package C Lead temperature,6 mm (/6 inch) from case for 0 seconds: J, JG, or W package C Storage temperature range, T stg C to 50 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:. All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC. 2. Differential voltages are at IN+, with respect to IN. 3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 5 V, whichever is less. 4. The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure that the dissipation rating is not exceeded. 5. Maximum power dissipation is a function of TJ(max), θja, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) TA)/θJA. Operating at the absolute maximum TJ of 50 C can affect reliability. 6. The package thermal impedance is calculated in accordance with JESD Maximum power dissipation is a function of TJ(max), θjc, and TC. The maximum allowable power dissipation at any allowable case temperature is PD = (TJ(max) TC)/θJC. Operating at the absolute maximum TJ of 50 C can affect reliability. 8. The package thermal impedance is calculated in accordance with MIL-STD POST OFFICE BOX DALLAS, TEXAS 75265

8 SLOS080J SEPTEMBER 978 REVISED MARCH 2005 electrical characteristics, V CC± = ±5 V (unless otherwise noted) TL07C TL07AC TL07BC TL07I PARAMETER TEST CONDITIONS TA TL072C TL072AC TL072BC TL072I TL074C TL074AC TL074BC TL074I UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX 25 C VIO Input offset voltage VO = 0, RS = 50 Ω mv Full range Temperature α VIO coefficient of input offset voltage IIO Input offset current VO = 0 IIB Input bias current VO = 0 VO = 0, RS = 50 Ω Full range µv/ C 25 C pa Full range na 25 C pa Full range na Common-mode VICR input voltage range C ± to ± to ± to ± to V Maximum peak RL = 0 kω 25 C ±2 ±3.5 ±2 ±3.5 ±2 ±3.5 ±2 ±3.5 VOM output voltage RL 0 kω ±2 ±2 ±2 ±2 V swing Full range RL 2 kω ±0 ±0 ±0 ±0 V Large-signal AVD differential voltage VO = ±0 V, RL 2 kω amplification 25 C Full range V/mV B Unity-gain bandwidth 25 C MHz ri Input resistance 25 C Ω CMRR Common-mode VIC = VICRmin, rejection ratio VO = 0, RS = 50 Ω Supply-voltage VCC = ±9 V to ±5 V, ksvr rejection ratio VO = 0, RS = 50 Ω ( VCC ±/ VIO) ICC Supply current (each amplifier) 25 C db 25 C db VO = 0, No load 25 C ma VO/VO2 Crosstalk attenuation AVD = C db All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range is TA = 0 C to 70 C for TL07_C,TL07_AC, TL07_BC and is TA = 40 C to 85 C for TL07_I. Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in Figure 4. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as possible. POST OFFICE BOX DALLAS, TEXAS

9 SLOS080J SEPTEMBER 978 REVISED MARCH 2005 electrical characteristics, V CC± = ±5 V (unless otherwise noted) TL07M TL074M PARAMETER TEST CONDITIONS TL072M TA MIN TYP MAX MIN TYP MAX UNIT 25 C VIO Input offset voltage VO = 0, RS = 50 Ω mv Full range 9 5 αv IO Temperature coefficient of input offset voltage IIO Input offset current VO = 0 IIB Input bias current VO = 0 VICR VOM AVD Common-mode input voltage range Maximum peak output voltage swing Large-signal differential voltage amplification VO = 0, RS = 50 Ω Full range 8 8 µv/ C 25 C pa Full range na 25 C pa 25 C ± 2 to na RL = 0 kω 25 C ±2 ±3.5 ±2 ±3.5 RL 0 kω RL 2 kω VO = ±0 V, RL 2 kω Full range ± 2 to 5 ±2 ±2 V ±0 ±0 25 C B Unity-gain bandwidth TA = 25 C 3 3 MHz ri Input resistance TA = 25 C Ω CMRR ksvr ICC Common-mode rejection VIC = VICRmin, ratio VO = 0, RS = 50 Ω Supply-voltage rejection VCC = ±9 V to ±5 V, ratio ( VCC±/ VIO) VO = 0, RS = 50 Ω Supply current (each amplifier) V V/mV 25 C db 25 C db VO = 0, No load 25 C ma VO/VO2 Crosstalk attenuation AVD = C db Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in Figure 4. Pulse techniques must be used that will maintain the junction temperature as close to the ambient temperature as possible. All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range is TA = 55 C to 25 C. 8 POST OFFICE BOX DALLAS, TEXAS 75265

10 operating characteristics, V CC± = ±5 V, T A = 25 C SLOS080J SEPTEMBER 978 REVISED MARCH 2005 SR tr Vn In THD PARAMETER Slew rate at unity gain VI = 0 V, CL = 00 pf, TEST CONDITIONS RL = 2 kω, See Figure TL07xM ALL OTHERS MIN TYP MAX MIN TYP MAX UNIT V/µs Rise-time overshoot VI = 20 mv, RL = 2 kω, µs factor CL = 00 pf, See Figure 20% 20% Equivalent input noise f = khz 8 8 nv/ Hz voltage RS = 20 Ω f = 0 Hz to 0 khz 4 4 µv Equivalent input noise current Total harmonic distortion RS = 20 Ω, f = khz pa/ Hz VIrms = 6 V, RL 2 kω, f = khz AVD =, RS kω, % 0.003% PARAMETER MEASUREMENT INFORMATION 0 kω VI + CL = 00 pf VO RL = 2 kω VI kω + RL VO CL = 00 pf Figure. Unity-Gain Amplifier Figure 2. Gain-of-0 Inverting Amplifier IN IN+ + TL07 N 00 kω N2 OUT.5 kω VCC Figure 3. Input Offset-Voltage Null Circuit POST OFFICE BOX DALLAS, TEXAS

11 SLOS080J SEPTEMBER 978 REVISED MARCH 2005 TYPICAL CHARACTERISTICS Table of Graphs FIGURE IIB Input bias current vs Free-air temperature 4 VOM AVD Maximum output voltage Large-signal differential voltage amplification vs Frequency 5, 6, 7 vs Free-air temperature 8 vs Load resistance 9 vs Supply voltage 0 vs Free-air temperature vs Frequency 2 Phase shift vs Frequency 2 Normalized unity-gain bandwidth vs Free-air temperature 3 Normalized phase shift vs Free-air temperature 3 CMRR Common-mode rejection ratio vs Free-air temperature 4 ICC Supply current vs Supply voltage 5 vs Free-air temperature 6 PD Total power dissipation vs Free-air temperature 7 Normalized slew rate vs Free-air temperature 8 Vn Equivalent input noise voltage vs Frequency 9 THD Total harmonic distortion vs Frequency 20 Large-signal pulse response vs Time 2 VO Output voltage vs Elapsed time 22 0 POST OFFICE BOX DALLAS, TEXAS 75265

12 SLOS080J SEPTEMBER 978 REVISED MARCH 2005 TYPICAL CHARACTERISTICS IIB Input Bias Current na VCC± = ±5 V INPUT BIAS CURRENT vs FREE-AIR TEMPERATURE VOM V OM Maximum Peak Output Voltage V ±5 ±2.5 ±0 ±7.5 ±5 ÁÁÁ ±2.5 MAXIMUM PEAK OUTPUT VOLTAGE vs FREQUEY ÎÎÎÎÎ VCC± = ±5 V VCC± = ±0 V VCC± = ±5 V RL = 0 kω TA = 25 C See Figure TA Free-Air Temperature C Figure k 0 k 00 k M 0 M f Frequency Hz Figure 5 VOM V Maximum Peak Output Voltage V ÁÁ ÁÁ ±5 ±2.5 ±0 ±7.5 ±5 ±2.5 MAXIMUM PEAK OUTPUT VOLTAGE vs FREQUEY ÎÎÎÎÎ VCC± = ±5 V VCC± = ±0 V VCC± = ±5 V RL = 2 kω TA = 25 C See Figure 2 VOM V Maximum Peak Output Voltage V ±5 ±2.5 ±0 ±7.5 ±5 ÁÁÁ ÁÁÁ ±2.5 MAXIMUM PEAK OUTPUT VOLTAGE vs FREQUEY ÎÎÎÎ TA = 25 C TA = 25 C ÎÎÎÎÎ TA = 55 C VCC± = ±5 V RL = 2 kω See Figure k 0 k 00 k f Frequency Hz M 0 M 0 0 k 40 k 00 k 400 k M 4 M 0 M f Frequency Hz Figure 6 Figure 7 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX DALLAS, TEXAS 75265

13 SLOS080J SEPTEMBER 978 REVISED MARCH 2005 TYPICAL CHARACTERISTICS VOM V Maximum Peak Output Voltage V ÁÁ ±5 ±2.5 ±0 ±7.5 ±5 ± MAXIMUM PEAK OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE VCC± = ±5 V See Figure 2 RL = 0 kω ÎÎÎÎ RL = 2 kω VOM V Maximum Peak Output Voltage V ÁÁ ±5 ±2.5 ±0 ±7.5 ±5 ± MAXIMUM PEAK OUTPUT VOLTAGE vs LOAD RESISTAE VCC± = ±5 V TA = 25 C See Figure TA Free-Air Temperature C RL Load Resistance kω Figure 8 Figure 9 VOM V OM Maximum Peak Output Voltage V ±5 ±2.5 ±0 ±7.5 ±5 ÁÁ ÁÁ ±2.5 MAXIMUM PEAK OUTPUT VOLTAGE vs SUPPLY VOLTAGE RL = 0 kω TA = 25 C A AVD Large-Signal Differential Voltage Amplification V/mV LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION vs FREE-AIR TEMPERATURE VCC± = ±5 V VO = ±0 V RL = 2 kω VCC± Supply Voltage V TA Free-Air Temperature C Figure 0 Figure Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 2 POST OFFICE BOX DALLAS, TEXAS 75265

14 A AVD Large-Signal Differential Voltage Amplification SLOS080J SEPTEMBER 978 REVISED MARCH 2005 TYPICAL CHARACTERISTICS LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE SHIFT vs FREQUEY Phase Shift VCC± = ±5 V to ±5 V RL = 2 kω TA = 25 C Differential Voltage Amplification Phase Shift 0 00 k 0 k 00 k M f Frequency Hz Figure M.3 NORMALIZED UNITY-GAIN BANDWIDTH AND PHASE SHIFT vs FREE-AIR TEMPERATURE.03 Normalized Unity-Gain Bandwidth.2 Unity-Gain Bandwidth Phase Shift VCC± = ±5 V RL = 2 kω f = B for Phase Shift TA Free-Air Temperature C Figure Normalized Phase Shift Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX DALLAS, TEXAS

15 SLOS080J SEPTEMBER 978 REVISED MARCH 2005 TYPICAL CHARACTERISTICS CMRR Common-Mode Rejection Ratio db COMMON-MODE REJECTION RATIO vs FREE-AIR TEMPERATURE VCC± = ±5 V RL = 0 kω ICC± Supply Current Per Amplifier ma ÁÁ SUPPLY CURRENT PER AMPLIFIER vs SUPPLY VOLTAGE TA = 25 C No Signal No Load TA Free-Air Temperature C VCC± Supply Voltage V 6 Figure 4 Figure 5 ICC± Supply Current Per Amplifier ma ÁÁÁ ÁÁÁ SUPPLY CURRENT PER AMPLIFIER vs FREE-AIR TEMPERATURE VCC± = ±5 V No Signal No Load PD P D Total Power Dissipation mw TOTAL POWER DISSIPATION vs FREE-AIR TEMPERATURE VCC± = ±5 V No Signal No Load TL074 ÎÎÎÎ TL072 TL TA Free-Air Temperature C TA Free-Air Temperature C 25 Figure 6 Figure 7 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 4 POST OFFICE BOX DALLAS, TEXAS 75265

16 SLOS080J SEPTEMBER 978 REVISED MARCH 2005 TYPICAL CHARACTERISTICS Normalized Slew Rate V/µs VCC± = ±5 V RL = 2 kω CL = 00 pf NORMALIZED SLEW RATE vs FREE-AIR TEMPERATURE ÁÁÁ 50 ÁÁÁ V Vn n Equivalent Input Noise Voltage nv/hz Hz ÁÁÁ EQUIVALENT INPUT NOISE VOLTAGE vs FREQUEY VCC± = ±5 V AVD = 0 RS = 20 Ω TA = 25 C TA Free-Air Temperature C k 4 k 0 k 40 k 00 k f Frequency Hz Figure 8 Figure 9 THD Total Harmonic Distortion % TOTAL HARMONIC DISTORTION vs FREQUEY VCC± = ±5 V AVD = VI(RMS) = 6 V TA = 25 C V I and V O Input and Output Voltages V ÁÁ 4 ÁÁ VOLTAGE-FOLLOWER LARGE-SIGNAL PULSE RESPONSE Output ÎÎÎ Input VCC± = ±5 V RL = 2 kω CL = 00 pf TA = 25 C k 4 k 0 k 40 k 00 k f Frequency Hz t Time µs 3.5 Figure 20 Figure 2 POST OFFICE BOX DALLAS, TEXAS

17 SLOS080J SEPTEMBER 978 REVISED MARCH 2005 TYPICAL CHARACTERISTICS 28 OUTPUT VOLTAGE vs ELAPSED TIME V VO O Output Voltage mv ÁÁÁ Overshoot 0% 90% tr VCC± = ±5 V RL = 2 kω TA = 25 C t Elapsed Time µs 0.7 Figure 22 6 POST OFFICE BOX DALLAS, TEXAS 75265

18 SLOS080J SEPTEMBER 978 REVISED MARCH 2005 APPLICATION INFORMATION Table of Application Diagrams APPLICATION DIAGRAM PART NUMBER FIGURE 0.5-Hz square-wave oscillator TL07 23 High-Q notch filter TL07 24 Audio-distribution amplifier TL kHz quadrature oscillator TL AC amplifier TL07 27 RF = 00 kω VCC+ 3.3 kω CF = 3.3 µf f 2 R C F F + 5 V TL07 5 V 3.3 kω kω 9. kω Output Input R C3 C R2 R3 C2 TL07 + VCC Output R R2 2R3.5 M C C2 C3 0 pf 2 f O khz 2 R C Figure Hz Square-Wave Oscillator Figure 24. High-Q Notch Filter VCC+ MΩ VCC+ + TL074 Output A VCC Input µf + TL074 VCC+ 00 kω VCC 00 kω + TL074 Output B 00 µf 00 kω 00 kω VCC+ VCC VCC+ TL074 Output C + VCC Figure 25. Audio-Distribution Amplifier POST OFFICE BOX DALLAS, TEXAS

19 SLOS080J SEPTEMBER 978 REVISED MARCH 2005 APPLICATION INFORMATION 8 pf 6 sin ωt N448 8 kω (see Note A) 5 V VCC+ 8 pf kω 88.4 kω + TL kω VCC+ TL072 6 cos ωt 8 pf VCC + VCC N448 kω 8 kω (see Note A) 5 V 88.4 kω NOTE A: These resistor values may be adjusted for a symmetrical output. Figure kHz Quadrature Oscillator VCC+ 0. µf 0 kω IN 0 kω MΩ 50 Ω TL07 OUT IN+ + N2 0. µf 0 kω N 00 kω Figure 27. AC Amplifier 8 POST OFFICE BOX DALLAS, TEXAS 75265

20 PACKAGE OPTION ADDENDUM 8-Jul-2006 PACKAGING INFORMATION Orderable Device Status () Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) HA OBSOLETE 0 TBD Call TI Call TI A ACTIVE LCCC FK 20 TBD POST-PLATE HA ACTIVE CFP U 0 TBD A42 SNPB PA ACTIVE CDIP JG 8 TBD A42 SNPB A ACTIVE LCCC FK 20 TBD POST-PLATE CA ACTIVE CDIP J 4 TBD A42 SNPB DA ACTIVE CFP W 4 TBD A42 SNPB JM3850/905BPA ACTIVE CDIP JG 8 TBD A42 SNPB JM3850/906BCA OBSOLETE CDIP J 4 TBD Call TI Call TI TL07ACD ACTIVE SOIC D 8 75 Green (RoHS & TL07ACDE4 ACTIVE SOIC D 8 75 Green (RoHS & TL07ACDR ACTIVE SOIC D Green (RoHS & TL07ACDRE4 ACTIVE SOIC D Green (RoHS & TL07ACP ACTIVE PDIP P 8 50 Pb-Free TL07ACPE4 ACTIVE PDIP P 8 50 Pb-Free TL07BCD ACTIVE SOIC D 8 75 Green (RoHS & TL07BCDE4 ACTIVE SOIC D 8 75 Green (RoHS & TL07BCDR ACTIVE SOIC D Green (RoHS & TL07BCDRE4 ACTIVE SOIC D Green (RoHS & TL07BCP ACTIVE PDIP P 8 50 Pb-Free TL07BCPE4 ACTIVE PDIP P 8 50 Pb-Free TL07CD ACTIVE SOIC D 8 75 Green (RoHS & TL07CDE4 ACTIVE SOIC D 8 75 Green (RoHS & TL07CDR ACTIVE SOIC D Green (RoHS & TL07CDRE4 ACTIVE SOIC D Green (RoHS & TL07CP ACTIVE PDIP P 8 50 Pb-Free TL07CPE4 ACTIVE PDIP P 8 50 Pb-Free TL07CPSR ACTIVE SO PS Green (RoHS & TL07CPSRE4 ACTIVE SO PS Green (RoHS & Addendum-Page

21 PACKAGE OPTION ADDENDUM 8-Jul-2006 Orderable Device Status () Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) TL07CPWLE OBSOLETE TSSOP PW 8 TBD Call TI Call TI TL07ID ACTIVE SOIC D 8 75 Green (RoHS & TL07IDE4 ACTIVE SOIC D 8 75 Green (RoHS & TL07IDR ACTIVE SOIC D Green (RoHS & TL07IDRE4 ACTIVE SOIC D Green (RoHS & TL07IJG OBSOLETE CDIP JG 8 TBD Call TI Call TI TL07IP ACTIVE PDIP P 8 50 Pb-Free TL07IPE4 ACTIVE PDIP P 8 50 Pb-Free TL07MFKB OBSOLETE LCCC FK 20 TBD Call TI Call TI TL07MJG OBSOLETE CDIP JG 8 TBD Call TI Call TI TL07MJGB OBSOLETE CDIP JG 8 TBD Call TI Call TI TL072ACD ACTIVE SOIC D 8 75 Green (RoHS & TL072ACDE4 ACTIVE SOIC D 8 75 Green (RoHS & TL072ACDR ACTIVE SOIC D Green (RoHS & TL072ACDRE4 ACTIVE SOIC D Green (RoHS & TL072ACJG OBSOLETE CDIP JG 8 TBD Call TI Call TI TL072ACP ACTIVE PDIP P 8 50 Pb-Free TL072ACPE4 ACTIVE PDIP P 8 50 Pb-Free TL072ACPSR ACTIVE SO PS Green (RoHS & TL072ACPSRE4 ACTIVE SO PS Green (RoHS & TL072BCD ACTIVE SOIC D 8 75 Green (RoHS & TL072BCDE4 ACTIVE SOIC D 8 75 Green (RoHS & TL072BCDR ACTIVE SOIC D Green (RoHS & TL072BCDRE4 ACTIVE SOIC D Green (RoHS & TL072BCP ACTIVE PDIP P 8 50 Pb-Free TL072BCPE4 ACTIVE PDIP P 8 50 Pb-Free TL072CD ACTIVE SOIC D 8 75 Green (RoHS & Level-2-260C-YEAR Level-2-260C-YEAR Level-2-260C-YEAR Level-2-260C-YEAR Level-2-260C-YEAR TL072CDE4 ACTIVE SOIC D 8 75 Green (RoHS & Level-2-260C-YEAR Addendum-Page 2

22 PACKAGE OPTION ADDENDUM 8-Jul-2006 Orderable Device Status () Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) TL072CDG4 ACTIVE SOIC D 8 75 Green (RoHS & TL072CDR ACTIVE SOIC D Green (RoHS & TL072CDRE4 ACTIVE SOIC D Green (RoHS & TL072CDRG4 ACTIVE SOIC D Green (RoHS & TL072CP ACTIVE PDIP P 8 50 Pb-Free TL072CPE4 ACTIVE PDIP P 8 50 Pb-Free TL072CPSLE OBSOLETE SO PS 8 TBD Call TI Call TI TL072CPSR ACTIVE SO PS Green (RoHS & TL072CPSRE4 ACTIVE SO PS Green (RoHS & TL072CPWR ACTIVE TSSOP PW Green (RoHS & TL072CPWRE4 ACTIVE TSSOP PW Green (RoHS & TL072ID ACTIVE SOIC D 8 75 Green (RoHS & TL072IDE4 ACTIVE SOIC D 8 75 Green (RoHS & TL072IDG4 ACTIVE SOIC D 8 75 Green (RoHS & TL072IDR ACTIVE SOIC D Green (RoHS & TL072IDRE4 ACTIVE SOIC D Green (RoHS & TL072IDRG4 ACTIVE SOIC D Green (RoHS & TL072IP ACTIVE PDIP P 8 50 Pb-Free TL072IPE4 ACTIVE PDIP P 8 50 Pb-Free Level-2-260C-YEAR Level-2-260C-YEAR Level-2-260C-YEAR Level-2-260C-YEAR Level-2-260C-YEAR Level-2-260C-YEAR Level-2-260C-YEAR Level-2-260C-YEAR Level-2-260C-YEAR Level-2-260C-YEAR TL072MFKB ACTIVE LCCC FK 20 TBD POST-PLATE TL072MJG ACTIVE CDIP JG 8 TBD A42 SNPB TL072MJGB ACTIVE CDIP JG 8 TBD A42 SNPB TL072MUB ACTIVE CFP U 0 TBD A42 SNPB TL074ACD ACTIVE SOIC D 4 50 Green (RoHS & TL074ACDE4 ACTIVE SOIC D 4 50 Green (RoHS & TL074ACDR ACTIVE SOIC D Green (RoHS & TL074ACDRE4 ACTIVE SOIC D Green (RoHS & Addendum-Page 3

23 PACKAGE OPTION ADDENDUM 8-Jul-2006 Orderable Device Status () Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) TL074ACJ OBSOLETE CDIP J 4 TBD Call TI Call TI TL074ACN ACTIVE PDIP N 4 25 Pb-Free TL074ACNE4 ACTIVE PDIP N 4 25 Pb-Free TL074ACNSR ACTIVE SO NS Green (RoHS & TL074ACNSRE4 ACTIVE SO NS Green (RoHS & TL074BCD ACTIVE SOIC D 4 50 Green (RoHS & TL074BCDE4 ACTIVE SOIC D 4 50 Green (RoHS & TL074BCDR ACTIVE SOIC D Green (RoHS & TL074BCDRE4 ACTIVE SOIC D Green (RoHS & TL074BCN ACTIVE PDIP N 4 25 Pb-Free TL074BCNE4 ACTIVE PDIP N 4 25 Pb-Free TL074BCNSR ACTIVE SO NS Green (RoHS & TL074BCNSRE4 ACTIVE SO NS Green (RoHS & TL074CD ACTIVE SOIC D 4 50 Green (RoHS & TL074CDE4 ACTIVE SOIC D 4 50 Green (RoHS & TL074CDR ACTIVE SOIC D Green (RoHS & TL074CDRE4 ACTIVE SOIC D Green (RoHS & TL074CN ACTIVE PDIP N 4 25 Pb-Free TL074CNE4 ACTIVE PDIP N 4 25 Pb-Free TL074CNSR ACTIVE SO NS Green (RoHS & TL074CNSRE4 ACTIVE SO NS Green (RoHS & TL074CPW ACTIVE TSSOP PW 4 90 Green (RoHS & TL074CPWE4 ACTIVE TSSOP PW 4 90 Green (RoHS & TL074CPWLE OBSOLETE TSSOP PW 4 TBD Call TI Call TI TL074CPWR ACTIVE TSSOP PW Green (RoHS & TL074CPWRE4 ACTIVE TSSOP PW Green (RoHS & TL074ID ACTIVE SOIC D 4 50 Green (RoHS & Addendum-Page 4

24 PACKAGE OPTION ADDENDUM 8-Jul-2006 Orderable Device Status () Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) TL074IDE4 ACTIVE SOIC D 4 50 Green (RoHS & TL074IDR ACTIVE SOIC D Green (RoHS & TL074IDRE4 ACTIVE SOIC D Green (RoHS & TL074IJ OBSOLETE CDIP J 4 TBD Call TI Call TI TL074IN ACTIVE PDIP N 4 25 Pb-Free TL074INE4 ACTIVE PDIP N 4 25 Pb-Free TL074MFK ACTIVE LCCC FK 20 TBD POST-PLATE TL074MFKB ACTIVE LCCC FK 20 TBD POST-PLATE TL074MJ ACTIVE CDIP J 4 TBD A42 SNPB TL074MJB ACTIVE CDIP J 4 TBD A42 SNPB TL074MWB ACTIVE CFP W 4 TBD A42 SNPB () The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free, Pb-Free (RoHS Exempt), or Green (RoHS & - please check for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free : TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either ) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & : TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 5

25 MECHANICAL DATA MCER00A JANUARY 995 REVISED JANUARY 997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE (0,6) (9,00) (7,) (6,22) (,65) (,4) (,60) 0.05 (0,38) (0,5) MIN 0.30 (7,87) (7,37) (5,08) MAX Seating Plane 0.30 (3,30) MIN 0.00 (2,54) (0,58) 0.05 (0,38) 0.04 (0,36) (0,20) /C 08/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD 835 GDIP-T8 POST OFFICE BOX DALLAS, TEXAS 75265

26

27 MECHANICAL DATA MCFP00A JANUARY 995 REVISED DECEMBER 995 U (S-GDFP-F0) CERAMIC DUAL FLATPACK (,4) (0,66) (6,35) (6,0) Base and Seating Plane (2,03) (,27) (0,20) (0,0) (7,62) MAX (0,48) 0.05 (0,38) (7,) (5,84) (,27) (8,89) (6,35) (8,89) (6,35) 4 Places (0,3) MIN / B 03/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification only. E. Falls within MIL STD 835 GDFP-F0 and JEDEC MO-092AA POST OFFICE BOX DALLAS, TEXAS 75265

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29 MECHANICAL DATA MLCC006B OCTOBER 996 FK (S-CQCC-N**) 28 TERMINAL SHOWN LEADLESS CERAMIC CHIP CARRIER NO. OF TERMINALS ** MIN A MAX MIN B MAX (8,69) (9,09) (7,80) (9,09) A SQ B SQ (,23) (6,26) (8,78) (23,83).4 (28,99) (,63) (6,76) 0.76 (9,32) (24,43).65 (29,59) (0,3) (2,58) (2,58) (2,6).047 (26,6) (,63) (4,22) (4,22) (2,8).063 (27,0) (0,5) 0.00 (0,25) (2,03) (,63) (0,5) 0.00 (0,25) (,40) (,4) (,4) (0,89) (0,7) (0,54) (,27) (,4) (0,89) / D 0/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-004 POST OFFICE BOX DALLAS, TEXAS 75265

30 MECHANICAL DATA MPDI00A JANUARY 995 REVISED JUNE 999 P (R-PDIP-T8) PLASTIC DUAL-IN-LINE (0,60) (9,02) (6,60) (6,0) (,78) MAX (0,5) MIN (8,26) (7,62) 0.05 (0,38) (5,08) MAX Gage Plane Seating Plane 0.25 (3,8) MIN 0.00 (0,25) NOM 0.02 (0,53) 0.05 (0,38) 0.00 (2,54) 0.00 (0,25) M (0,92) MAX /D 05/98 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-00 For the latest package information, go to POST OFFICE BOX DALLAS, TEXAS 75265

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36 MECHANICAL DATA MTSS00C JANUARY 995 REVISED FEBRUARY 999 PW (R-PDSO-G**) 4 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,65 0,0 M 0, ,50 4,30 6,60 6,20 0,5 NOM Gage Plane A ,25 0,75 0,50,20 MAX 0,5 0,05 Seating Plane 0,0 DIM PINS ** A MAX 3,0 5,0 5,0 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9, /F 0/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,5. D. Falls within JEDEC MO-53 POST OFFICE BOX DALLAS, TEXAS 75265

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