An Accurate Delay Modeling Technique for Switch-Level Timing Verification. Seung H. Hwang, Young H. Kim, and A.R. Newton

Transcription

1 An Accurate Delay Modeling Technique for Switch-Level Timing Verification Seung H. Hwang, Young H. Kim, and A.R. Newton Department of Electrical Engineering and Computer Sciences University of California, Berkeley, CA A new delay modeling technique for accurate timing verification of digital MOS circuits is presented. The technique is based on the ELogic approach and provides the user with a continuous speed-accuracy trade-off in addition to more accurate timing information than available with existing switch-level timing verifiers. The new technique has been implemented in the Crystal timing analyzer and experimental results comparing this method with those used in Crystal are included. Comparisons indicate that the ELogk-based approach, while slower than present approaches, provides a more robust and more accurate delay analysis at the switch level. Previous Work. INTRODUCI ION Digital circuits are designed as either asynchronous or synchronous logic systems. For asynchro nous designs, great care must be exercised to avoid possible timing errors due to any difference in state sequencing and output values under conditions of arbitrary, differential signal delays through circuit paths. Synchronous systems are clocked and their implementation functions correctly only if the clock period is long compared to the delays in the circuit. Therefore, the speed of the circuit is determined by the slowest of all possible signal paths, which is called the critical-path of the circuit. on the other hand, unnecessarily fast sections of the circuit consume extra power. Designers attempt to verify the timing of the circuit and correct timing errors while optimizing speed-power product. This is becoming a more and more difficult task as circuit size and complexity increase and the growing competition for high-performance circuits makes circuit speed ever more critical. Simulation is often a very inefficient technique for solving this problem. Furthermore, pathological conditions may not be detected if simulation is used, unless particular inputs are in the correct state. Therefore, timing veri@zdon has played a very important role in designing the digital integrated circuit and in optimizing its performance [.2, 3,4. There are two main approaches used in timing verification, called path enumer ation and criric&- path analysis. The basic difference between the two methods is that in the path enumeration [5 method all possible paths in the circuit are checked, while in the critical-path analysis method the search is pruned and only the slowest paths are detected. Path enumeration is conceptually simple, but it suffers from long CPU-time due to the potentially millions of possible paths. Even though a major difficulty of the critical-path analysis is its greater implementation complexity, it has been successfully implemented and applied at the MOS switch level in programs such as Crystal [4 and TV [3. Unlike simulation, the critical-path analysis method used in these programs is v&eindependent. This means that, for example, if a signal change occurs at the input of a gate or switch, its effect is always propagated to the output node, regardless of the signal states at the other input terminals. In simulation, the changing signal propagates to the output of the gate if and only if the signal states at the other input terminals support the propagation. Value independence is both a strength and a weakness of critical-path analysis. It enables the critical-path analysis to avoid checking for all possible input vectors, which grows exponentially with the number of input nodes. As a result, the critical-path analysis can save much CPU-time, compared to simulation. However, since the critical-path analysis ignores specific signal values, it may report critical paths which can never occur under real operating conditions. These paths are called f&se puths. The false paths tend to hide the real critical paths in the circuits under test. In this case, a mechanism called case analysis, which fixes the node value, must be used. Some timing verifiers model the circuit at switch-level, i.e., they represent the nonlinear MOS transistor by a linear resistor with switch in series. Then they calculate the delay time by using RCbased approaches. While the RC approaches are very efficient in terms of CPU-time, they assume X/86/0000/0227$ IEEE 23rd Design Automation Conference 227

2 that there is only one direct path from power sup ply or ground to any n&e of a stage, for delay time calculation. For example, in the case of NMOS inverter, only the driver is considered for delay time calculation when it is on, and the load is ignored even though it is on too. While some of the RC approaches incorporate information about input waveform shape and load condition in order to obtain more accurate delay estimates, they use the ratio approach which was first suggested by Pilling and Skalnik [6]. The ratio approach improves the accuracy of delay time in most circuits but it may still result in large error. Neither do the RC approaches provide an accuracy-speed trade-off. ln this paper, a new, accurate delay modeling technique for timing verification is presented. The technique, based on ELogic [7], provides a continuous accuracy-speed trade-off and more accurate timing information than switch-level logic simulation. Its implementation in the switch-level timing verification program Crystal [8,9,4 is described. In the remainder of this section we review the Eb gic modeling approach and introduce its application to timing verification. In Section 2, the implementation of ELogic in an existing timing verifier is described in detail, and in Section 3 experimental comparisons between our new approach and a state-of-the-art switch-level timing verifier are presented. EL.opic Modeling The Electrical-Logic (EL.++) method [7,0] is a relkxafion-based multi-level, multi-strength, switchlevel circuit modeling and analysis technique which provides a consistent framework for more accurate time-domain simulation of digital MOS circuits than existing switch-level logic simulators, at almost same speed. In ELogic, we define a set of discrete voltage levels called voltage states which can be considered the same as the logic levels of switch-level logic simulators [I, 2,3, 34,5, except that an actual voltage value is assigned to each state. A strength value for the ELogic model is defined for each circuit element with a specific conducting path, unlike the switch-level logic simulation where the sltrength is an abstraction of conductance from a node to ground or to power sup ply. In ELogic, circuit nodes are allowed to make a transition from one voltage state to an adjacent voltage state only - multiple voltage step transitions are not permitted in a single solution. ELogic solves for the amount of time required to make the single transition, rather than solving for the amount of voltage change at each node to the given time step as in conventional electrical simulators. Consider an NMOS inverter of Figure I(a). EL.ogic assumes that there is a grounded capacitor at each signal-node. Figure I(b) represents an input waveform fragment and Figure l(c) represents a corresponding output waveform which ELogic computes. For example, the input waveform achieves a new voltage state VI from VO, at time I,. However the input state VI is not high enough to pull down the output of the inverter and therefore it remains high. When the input reaches its new voltage state V2 at time tz, from VI, the output begins to pull down from V5 to its new state V4. and ELogic calculates the time, AT, required for that transition using the electrical properties of the NMOS inverter. Then, ELogic m-processes the output node at t3. In this way, ELogic computes the output waveform. To summarize, ELogic determines whether or not the output can change its state in following two cases : () when the output reaches the new state (event-driven) (2) when the input reaches the new state (selective-trace) Ml o----j q 7 M2 J - - V5 v4 v3 v2 Vl VO I v5 v4 V3 [--- Y---L A? : I- b _ t t2 t3 t4 time (a) NMOS Inverter Fig. NMOS Inverter (b) Input Waveform Example using ELogic (C) Output Waveform 228

3 and if it changes, ELogic calculates the cox-responding transition time. The number of the voltage states can be varied and the values of the voltage states may be nonuniform. Most of CPU-time savings of logic simulation over electrical simulation comes from fewer time points evaluated rather than fewer iterations at the same time point. Since there is no restriction in defining the number and/or the values of the voltage states, EL.+ can provide a continuous speed-accuracy trade-off. EL&c uses either a small-signal model or a line-thru-origin model for MOS transistors, and the state values can be obtained experimentally by measurement or can be computed using a standard MOS simulation model, such as the Schichman- Hodges model, [6]. The small-signal model linearizes the MOS transistor by an incremental conductance at the operating point and a current source in parallel. The line-thru-origin model linearizes the MOS transistor by a simple conductance between drain and source. These models are represented by tables containing the Norton equivalent for all output ports as a function of the controlling voltage states for the MOS transistor. That is, G = T, ( Vin ), Z = T, (?in ) () where % are the controlling voltage states and TG and T, are tables which are stored in the library of the program, once the fabrication technology is determined. The other class of circuit element used in ELOgic is the node which includes a grounded capacitor. The inputs to the node model are the Norton equivalent {G,. Ij ) pairs obtained from the fanin elements and the fanin nodes. The output is a new voltage state at the node, vnext, and the time point Tnext at which Vnext is achieved. The composite ELogic model of an NMOS inverter(fig. l(a)) is shown in Figure 2. If node A achieves its new state before node B has reached its new state (fast input transition), the pending event is canceled and a new voltage state and a new transition time for node B are computed (fanoutadjustment). If node B has not been supposed to change its state(latent), it may or may not be scheduled to change the state, depending on the electrical properties of the inverter being analyzed (activating latent fanout nodes). In Figure 2, node B serves as an input node as well as an output node of the inverter. Therefore, EL&c automatically takes account of different input and output loading conditions. This is one of the reasons why ELogic is more accurate than conventional switch-level logic simulators. ELogic belongs to the class of timing simulators since it does not iterate to convergence. Assume that node N is processed by EL.ogic. First, the ELogic approach decouples a sub-circuit, consisting of only node N and its fanin nodes, from a given circuit. Then, the transition time for the node N to achieve next state is calculated from the information associated with the sub-circuit. Two versions of ELogic, ELogic- and ELogic-2, are described in this section. ELogic- can be derived directly from timing simulation where instead of continuous voltage at a node, a discrete set of states is permitted. Ehgic- models the grounded capacitor at all fanin nodes of N, as an ideal voltage source without resistance. Then, the total conductance Gn- and current ZN at node N are computed : Nin Nin Gx = Gj. ZN =, j=l j=, where Nin is the number of fanin nodes at node N. Then the circuit being analyzed is simplified to a RC-network of Figure 3 and the transition time, AT, to reach the next state is computed by following first-order approximation : AT = CN x AV IN -(V, x GN) where V, is the voltage at node N point. (2) (3 at present time Strong coupling in a circuit slows the convergence speed of relaxation-based methods, unless proper methods such as partitioning algorithm are used [7]. While strong coupling slows the conver- Fig. 2 ELogic Composite Model of NMOS inverter Fig. 3 Norton Equivalnet Circuit When Node N is solved by ELogic- 229

4 gence speed of relaxation methods, in,5&g&~ it may occasionally cause a wrong decision on whether the node can make a transition to a new state, since ELo;pic does not iterate to convergence. As a solution, small voltage step sizes may be used for circuits which contains strong coupling and the states required for the accurate analysis of a particular circuit can be determined by a pre-analysis of the circuit topology and relative device sizes. ELogic-2 uses the Trapezoidal integration method to discretize the grounded capacitor at strongly coupled fanin nodes so that they can be solved together with node N, and models the rest of the fanin nodes as ideal voltage sources. Since the Trapezoidal integration method involves a transition time in its discretized capacitor model, ELagic-2 needs to solve a polynomial equation for a transition time and is more expensive. ELonic in Timing Verification In general, timing verification programs are partitioned into two sections such as path-analysis section and delay modeler, as illustrated in Figure 4. The path-analysis section extracts a part of the circuit systematically using the signal flow graph which spreads from fanin nodes to fanout nodes, and transfers il. to a delay modeler. The delay modeler computes the delay for the extracted part of the circuit. Using the delay information obtained from the delay modeler, the timing verifier locates the critical paths of the circuit. ELogic was implemented as a delay modeler in a timing verifier Crystal. Crystal finds all nodes that may possibly change as a consequence of the change in the input, computes the worst-case delays to those nodes, and provides the designer with information about the last nodes to settle and the worst-case path:; leading from the input to those nodes. Crystal traces out and extracts the circuit into chains of transistors called stages from the circuit. A stage consists of not only transistors but also nodes between a signal source and a place where the signal is used. Since a single transistor can participate :in many different stages during a single timing verification run, Crystal extracts all the stages triggered by a change at a node dynamically during timing verification [8]. Each stage is then passed to a delay modeler that computes how long it will take for the output of the stage to change value. Once the stage has been used, it is discarded. Crystal uses a depth-first search to trace out stages and locate the critical paths and it stores with each node the slowest delay time to that node that has been found so far. When a node appears as the output of a stage, the new delay time from the stage is compared to the time stored in the node. Timing Verifier Fig. 4 Simplified Partition of Structure of Timing Verifier The slower time :is stored in the node. Some other programs such as TV [3 use a breadth-first search. The comparison of the depth-first and breadth-first approaches, in applying ELogic as a delay modeler, is described in Section 3. Since delay modeler is separate from the path analysis section in the timing verification program, ELogic can be used as a basis to calculate the delay time of the stages. 2. IMPLEMENTATION OF ELOGIC MODEL IN A TIMING VERIFIER The stand-alone ELogic delay modeler was added in Crystal with emphasis on consistency of the program structure and minimum modification of the existing code rather than for performance optimization. Since ELogic is a simulation technique, a pointer was added into the structure of the stage to store the waveform segment of its output node. Note that Crystal assumes each gate of transistors in a stage, except the input node, can take only one of two states, i.e., Vdd or ground. Since the version Crystal employing the EL.ogic delay model uses the same structure, the simulation is not ideal. When Crystal calls a delay modeler, it transfers the information on the stage. Since a stage is created as a chain of transistors from the signal source to a gate or output node, the stage, as is, may not be the correct subcircuit to be simulated using the Ebgic technique. In this case, a signal source is any strong source of a logic 0 or. For example, if Input of Figure 5 turns on, four stages are created for delay evaluation, such as M2-M3- M4, M2-M3-M5, Ml -M3-M4 and Ml-M3-M5. It is observed that either Ml or M2 is missing for the stages. Therefore, a function called StageSetufij was implemented to complete the stage by tracing out missing parts from input file, if there is any. The definition of the delay was slightly modified from the conventional definition of the propagation delay. The propagation time is a time difference between 50% points of the input and output pulse waveforms. However, the delay time used by Cry- 230

5 +Vdd - I =le M3 Fig. 5 Circuit Fragment -I- stal is based on the typical logic threshold voltages Vinv, at which the input voltage is equal to the output voltage of the inverter. Once the output waveform segment is obtained for a stage with delay time, the segment is stored for the output node i. Later, the stored output waveform segment is used as an input waveform segment for the stage whose input node is i. The simulation by the ELQ gic technique is performed until the output waveform reaches a steady state. Note that the simulation is necessary only for one transition of low to high logic state, or high to low logic state. Crystal provides the information whether the current stage is rising or falling. The ELqic model was implemented using a. mixed algorithm of Ehgic- and ELogic-2 (mined Ehgic). When it evaluates the delay time, ELogic-I algorithm is used Hurst for each transition. If a node fails to make that transition for some reason, perhaps too large a voltage step, the algorithm switches from EL&c-l to ELogic-2 which guarantees that the node will make a transition, if -I- M4 appropriate. The high-level pseudo-code description of the algorithm is as follows. /* evaluate the delay by ELogic technique */ ELogicDelay(stage) /* complete the stage for Ehgic */ StageSetup(stage); /* process all nodes at beginning */ init(stage); M5 /* obtain the waveform at output node */ while(the queue is not empty OR output node is not in steady state) { get next node j from the queue; nodeqroc(j ; forall(fanout nodes i of j) nodeqroc(i ; calculate a de&y from waveform segments; retum(deloy >; nodeqroc(j > t use EL&c-0; if (j made a transition) retum0; else use ELogic-20; 3. EXPERIMENTAL RESULTS The ELogic model was evaluated using a CMOS microprocessor SOAR[I8]. The chip has 34,526 transistors and 3,3 nodes. The critical paths of the entire chip were extracted using the distributed slope model which is the best model available in Crystal, and they were also processed by mixed ELogic and SPICE2 for comparison purposes. Table summarizes the results. The last column illustrates the sum of CPU-times spent for the delay calculation of 2 critical paths. The experiments were done on VAX 8600 with UNIX. Figure 6 and 7 compare the mixed EL.ogic model (0.2~ step) and distributed slope model to SPICE2. The horizontal axes are the delay times of SPICE2 and the vertical axes are those of each model. Each line corresponds to one critical path, and each segment of the line corresponds to a stage in the path. The point compares each model s and SPICE2 s estimates for the total delay in the critical path up through that stage. From Figures 6 and 7, it is observed that mixed ELogic produces much more accurate delay estimates than the distributed slope model. Notice that, from Figure 7, the actual critical path A, as predicted by SPICE2, may be hidden by other paths. This can be avoided if one uses a more accurate delay model. To observe the effect of voltage step change of ELogic and the difference between Ebgic- and the mixed ELogic algorithm, the ALU part of the circuit was extensively evaluated. This circuit consists of 694 transistors and 89 nodes. Crystal with each model was run on the circuit to extract 5 critical paths. Figures 8, 9, and 0 illustrate the comparisons between the mixed ELogic model of 25 states (0.2 volt step), the mixed ELogic model of 0 states (0.5 volt step), and the Crystal distributed slope model, respectively, with SPICE2. The improved accuracy of the ELogic approach is clear from these results, however, the distributed slope model in Crystal is also relatively accurate in this case. The results for the ALU are summarized in Table 2. The last two columns of the table illustrates the CPU-time spent by each delay modeler and the total CPU-time. Every modeler does not extract the same number of stages evaluated. But the numbers differed within 3 percent for this cir- 23

6 Table A Comparison of the Delay Models ( SOAR > I Model Table 2 A C!omparison of the Delay Models ( ALU ) SPICE2 II - I - I I II I I L 2ON SPICE2 Fig. 6 Mixed ELogic (0.2V step) VS. SPICE2 for SOAR 20N SPICE Fig. 8 Mixed ELogic (0.2V step) VS. SPICE2 for ALU 20N SPICE2 5OON Fig. 7 Crystal Distributed Slope Model vs. SPICE2 for SOAR cuit. Note the difference of CPU-time between the ELogic- model and the mixed ELqic model with same voltage steps. This is due to the fact that when the given voltage step is small, ELogic- can make transitions in most cases. When ELogic- can not make a transition, the mixed EL&c may not either, which i-mplies that the call of ELogic-2 is almost unnecessary and ELogic- is more advantageous, with small voltage step size. However, when the voltage step is increased, ELogic- model can not guarantee a successful transition even if it should make a transition with the circuit. Note that the CPU-time of ELogic- model (0.~ step) Fig. 9 Mixed ELogic (0.W step) vs. SPICE2 for ALU 20N SPICE 232

7 ACKNOWLEDGEMENTS The authors would like to thank Resve A. Saleh for many long hours of useful discussion of EL&c. The support of Digital Equipment Corporation and the Semiconductor Research Corporation under contract number SRC is also gratefully acknowledged. WON Fig. 0 Crystal Distributed Slope Model VS. SPICE2 for ALU SPICE2 and the mixed ELogic model (0.2~ step> in Table 2 are almost equal, but the mixed ELogic model is more accurate. According to the experiences of the authors, it is suggested that the mixed ELogic model is more suitable in practice. The EL.ogic delay model was implemented in Crystal which uses depth-first analysis. Depth-first analysis has the advantage in handling circuits with cycles in a natural way. Even though depth-first analysis has the disadvantage that the model is applied to each node several times (on the average), when the delay modeler takes a small portion of total analyzing time like in the original Crystal, it is not a significant issue. If the Ehgic model had been implemented in breadth-first analysis and the stage information had been extracted more suitably for an ELqic model, the delay modeler may have been applied only once for each node and the total run time could have been reduced significantly. This is a direction for our future work in this area. 4. SUMMARY A new delay modeling technique based on EL.5 gic was implemented in a timing verifier Crystal. The major features of this new model, accuracyspeed trade-of and a consistent approach for a wide range of design styles, have been verified by experimental results using a CMOS chip. The experimental results also illustrate the accuracy of the delay time estimates is much improved over existing switch-level techniques. It is believed that the technique also works well for NMOS circuits REFERENCES T.. Kirkpatrick and N.R. Clark, PERT as an Aid to Logic Design. IBM Jour. of Research and Deve.?opment. pp (966). T. M. McWilliams. Verification of Timing Constraints on Large Digital Systems. 7th Design Automution Gmference,ZEEE. pp (980). N. P. Jouppi. Timing Analysis for NMOS VLSI. Proceedings of the 20th Design Automation Conference. pp (983). J. K. Ousterhout. Crystal:A Timing Analyzer for NMOS VLSI Circuits.* Proceedinp of the third Caltech VLSZConference. pp (98:). I P. Ng. W. Glauert. and R. Kirk, A Timing Verafication System Based on Extracted MOS/VLSI Circuit Parameters, 8th Design Atiomation Conference,ZEEE. pp (June 98). D. J. Pilling and J. C. Skalnik. A Circuit Model for Predicting Transient Delays in LSI Logic Systems. A-oc. 6th Asilomar Conference on Circuit and Systems. pp (972). Y. H. Kim, J. E. Kleckner. R. A. Saleh. and A. R. Newton, Electrical-Logic Simulation. Digest 2984 Znt. Conf. on CAD, IEEE. (Nov 984). J. K. Ousterhout. A Switch-Level Timing Veri$er for Digital MOS VLSI, University of California, Berkeley (Feb ). J. K. Ousterhout. Using Crystal for Timing Analysis, University of California, Berkeley (Sept ). Y. H. Kim, ELOGIC : A Relaxation-Based Switch-Level Simulation Technique. UCBIERL M86/2. University of California. (. R. A. Saleh. Iterated Timing Analysis and SPLICE, CJCB/ERL M&#/2. University of California. Berkeley, (Jan 984). LOGIS: User s Manual Versiuz 4, ISD Corporation (980). F. Jenkins, ZZ&CS: User s Mwuul, Simutec (982). R.E. Bryant, An Algorithm for MOS Logic Simulation. LAMBDA. pp, (4th Quarter 980). CM. Baker and C. Terman. Tools for Verifying Integrated Circuit Designs, LAMBDA. (4th Quarter 980). H. Schichman and D.A. Hodges. Modeling and Simulation of Insulated Gate Field-Effect Transistor Switching Circuits, IEEE Journ. on Solid State Circuits Vol. SC- 3 pp (Sept. 968). J. White and A. Sangiovanni-Vincentelli. Partitioning Algorithms and Parallel Implementations of Waveform Relaxation Algorithms for Circuit Simulation, Proc. 985 Znt. Sym. of Circuits and Systems, (June 985). C. C. Ma&o. Smalltalk on a RISC - CMOS Zmplementation, University of California, Berkeley (May 985). MS. Report 233