Microelectronics Reliability

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1 Microelectronics Reliability 51 (211) Contents lists available at ScienceDirect Microelectronics Reliability journal homepage: NBTI reliability on high-k metal-gate SiGe transistor and circuit performances Jiann-Shiun Yuan a,, Wen-Kuan Yeh b, Shuyu Chen a, Chia-Wei Hsu b a Department of Electrical Engineering and Computer Science, University of Central Florida, Orlando, FL 32816, USA b Department of Electrical Engineering, National University of Kaohsiung, Kaohsiung, Taiwan article info abstract Article history: Received 12 November 21 Received in revised form 14 December 21 Accepted 28 December 21 Available online 17 January 211 Negative-bias temperature instability (NBTI) on high-k metal-gate SiGe p-channel MOSFETs has been examined. SiGe p-mosfets shows reduced interface states and enhanced NBTI reliability compared to their Si p-channel control devices as evidenced by experimental data. Impact of NBTI reliability on digital and RF circuits has been also examined using extracted fresh and stressed BSIM4 model parameters in circuit simulation. High-k metal-gate SiGe pmosfets demonstrate less inverter pull-up delay, smaller noise figure of a cascode low-noise amplifier, and larger output power and power-added efficiency than their Si counterparts when subject to NBTI stress. Ó 21 Elsevier Ltd. All rights reserved. 1. Introduction Logic processing products with transistors made of high-k and metal-gate have been first introduced at the 45 nm technology node [1]. Second generation of high-k metal-gate transistors on 32 nm node is already in production in continuous support of Moore s law [2]. The Hf-based high-k metal-gate transistors enabled very aggressive equivalent oxide thickness scaling (.9 1. nm), while demonstrating significant reduction in gate leakage current. This comes with more than % higher operating electric fields than 65 nm node (which used polysilicon/sio 2 gate stack) and as a result, reliability issues such as hot carrier effect, gate oxide breakdown, and bias temperature instability (BTI) become challenging. Negative-bias temperature instability (NBTI) [3] is often monitored by the shift of threshold voltage DV t. Its time dependence could be modeled as power-law characteristic. Based on the data over the years, it has been reported that NBTI shift in devices with pure SiO 2 or thin SiON gate dielectrics may be attributed to interface traps generation at the Si/SiO 2 interface. High-k metal gate NBTI mechanism was consistent with that seen in SiO 2 at the interface [4]. It has been suggested that in addition to interface traps generation, hole trapping in preexisting defects plays an important role in determining overall time kinetics of NBTI degradation in thick thermal SiON and high-k materials. A systematic study of the time-dependent NBTI degradation over all timescales for different types of devices can be found in [5,6]. Furthermore, the on-thefly measurement technique evaluates DV t at the stress gate bias so that the stress was maintained during the measurement. Corresponding author. Tel.: ; fax: address: yuanj@mail.ucf.edu (J.-S. Yuan). NBTI effect on silicon semiconductor devices has been extensively studied in the past 15 years. Impact of NBTI on digital and analog circuit performances were investigated [7 15]. For example, NBTI increases the gate delay of the inverter [7] and decreases the noise margin of the SRAM [8]. Digital and analog circuits were designed to evaluate reliability [9 11], a processor was designed to be NBTI aware [12], a synthesis method was proposed to characterize the delay of every gate in the standard cell library as a function of the signal probability [13], and an efficiency method was presented to identify critical gates to effectively protect the circuit from aging [14]. However, NBTI effect on RF circuit performances is less understood. In this paper, we evaluate high-k metal-gate SiGe pmos on device and circuit reliability, especially for RF circuit performances. Drain current degradations as a function of NBTI stress time for SiGe pmosfets are compared with the Si control sample experimentally. The interface state density is extracted using the charge pumping method. NBTI effects on inverter pull-up delay, low-noise amplifier (LNA) noise figure, and power amplifier output power and power-added efficiency are studied using the fresh and stressed model parameters obtained from device measurement. 2. SiGe PFET device performance and NBTI reliability In order to enhance transistor driving capability, strained-sige layer is an attractive channel material due to its high carrier mobility [15,16] and compatibility with conventional CMOS process. It is, however, not easy to obtain a high quality gate oxide on strained SiGe layer using high temperature thermal oxidation because it results in high interface states and thus strongly decreases transistor performances [17]. One effective way is to offer a good interface and prevent post thermal induced Ge diffusion resulting in device degradation is to keep the SiGe channel away from the gate using a /$ - see front matter Ó 21 Elsevier Ltd. All rights reserved. doi:1.116/j.microrel

2 J.-S. Yuan et al. / Microelectronics Reliability 51 (211) thin Si cap layer. A thin SiO 2 interfacial layer (IL) was also formed before high-k dielectric layer deposition. Hf-based oxide was deposited by atomic layer deposition method. After the gate stack formation with a TiN metal electrode, an appropriate laser spiking annealing was used to activate source and drain junctions without degrading the property of high-k and metal gate. Finally, an advanced metallization process was performed to finish the high-k, metal-gate SiGe channel MOSFET as shown in Fig. 1. Strained SiGe layer on Si substrate provides a compressive strain to enhance channel mobility l p effectively. The improvement in hole mobility is a function of Si cap layer and SiGe thicknesses. A thick Si cap layer reduces the SiGe compressive strain which is not favorable for hole mobility enhancement. On the other hand, a thin Si cap layer may not be helpful to reduce interface states. An optimization of Si cap layer to SiGe channel thickness leads to a ratio of.9 (Si cap layer thickness = 4.6 nm and SiGe thickness = 5 nm), which gives much higher drain current driving capability as evidenced by the experimental data in Fig. 2. As seen in this figure the drain current of SiGe pmosfet is much larger than that of Si control device. This is because the compressive strain reduces the holes effective mass and splitting of heavy and light holes band. The holes mobility is thus higher in strained SiGe channel than that in Si channel. Fig. 3 shows the measured drain current degradation for devices versus NBTI stress time (V G = V T 1.8 V with other terminals grounded). Constant gate stress technique has been used by other publications (see Fig. 9 in Ref. [18]). In addition, the gate voltage stress effect is consistent with RF circuit operation. Larger I D degradations are seen for p-channel devices with. For pmos- FET NBTI is an interface trap driven phenomena associated with breaking of Si H bonds. Although the H is released as atomic H, they convert to and diffuse as molecular H 2. The activation and time exponent of NBTI are defined by this diffusion of molecular neutral H 2. Furthermore, less drain current degradations were observed for SiGe transistors. By introduction of strained SiGe layer in pmosfets, the holes are primarily located in the SiGe channel due to valence band offset [19,2] and thus the holes concentration in Si surface channel is lower than that of control Si pmosfet. Since NBTI is mainly caused by holes, the SiGe pmosfets with lower carrier concentration can improve NBTI effect. With an optimized ratio of Si cap layer to SiGe channel thickness, holes are confined even more effectively in the strained SiGe layer. To further examine the interface state density N it located in the high-k and IL stack layer, the charge-pumping measurement was conducted. During the charge-pumping measurement, a square pulse wave with a 1.2 V fixed amplitude, 1 ns rise and fall time, and a 5% duty cycle pulse width from a pulse generator (HP 8111 A) was applied to the gate of the p-channel MOSFET. As Drain Current (µa/µm) I D Degradation (%) W /L = 1µm/.6µm Pure Si 6.6 / 8 ~ / 5 ~.9 V G - V Th = 1V V G - V Th = V Drain Voltage (V) Fig. 2. Drain current versus drain voltage. W = 1µm L = 1µm NBTI Vstress = V T -1.8V 6.6 / 8 ~ / 5 ~.9 Fig. 3. Drain current degradation versus stress time. shown in Fig. 4 N it is much lower for the SiGe pmosfets with SiGe channel, while the pmos transistors with has higher interface states density. For Si-cap/SiGe pmosfet, an undoped Si-capping layer was formed by epitaxial growth directly on SiGe layer. In this work, with appropriate Si-cap/SiGe layer ratio, strained-sige devices can exhibit lower interface defect even in comparison with pure Si control devices. Similar measurement data differences between strain silicon and conventional silicon MOSFETs can be seen in Fig. 17 in Ref. [21]. N it (1/cm 2 ) 4x x x x x1 11 2x / 8 ~ / 5 ~.9.5MHz 1MHz 3 256kHz 1/Frequency (1/Hz) 6 125kHz 9 Fig. 1. Schematic of HfO 2 metal gate SiGe pmosfet. Fig. 4. Interface trap density versus inverse frequency.

3 916 J.-S. Yuan et al. / Microelectronics Reliability 51 (211) Threshold Votlage (V) Hole Mobility (cm 2 /V. s) SiGe SiGe SiGe SiGe RFin Cin Lin C shunt1 3. Circuit impact C shunt2 V bias1 V bias2 R bias1 I D V D and I D V G characteristics of p-channel MOSFETs with Si or SiGe channel are measured. Transistor BSIM4 model parameters L s M 1 R bias2 M 2 L D C out L out1 Fig. 7. Schematic of p-channel low-noise amplifier. L out2 C shunt3 RF out Fig. 5. Threshold voltage and hole mobility versus stress time. Normalized Noise Figure (%) SiGe SiGe Fig. 8. Normalized noise figure versus stress time. Pull-Up Delay (ps) RFin Cin Lin V bias1 R bias1 L s M 1 C out C shunt L shunt RF out 15 L D Fig. 6. Schematic of three cascaded inverters and second inverter s pull-up delay versus stress time. Fig. 9. Schematic of a single-stage p-channel power amplifier.

4 J.-S. Yuan et al. / Microelectronics Reliability 51 (211) Output Power (db) Power-added Efficiency (%) Fig. 1. Output power and power-added efficiency versus stress time. and L shunt and C shunt are used to short all higher order harmonics. The power amplifier is designed at 5.2 GHz in the class A mode of operation ( = 1.8 V and V bias1 =.8 V). For the class A power amplifier, the output power can be expressed as [23,24]. P out ¼ 1 2 ð V DSAT Þ I m ðh sin hþ 2p ð1þ where is the supply voltage, V DSAT is the knee voltage, I m is the maximum drain current of the p-channel transistor, and h is the conduction angle. The drain efficiency of the power amplifier is given by g D ¼ V m h sin h 4 sin h ð2þ h 2 2 cosðh 2 where V m is the maximum output voltage. Note that the drain efficiency is defined as P out /P DC, where P DC is the DC power from the supply voltage. g D reaches the maximum when V m is approaching. The power amplifier output power and power-added efficiency ( (P out P in )/P DC ) versus stress time are shown in Fig. 1. As seen in this figure the power amplifier using the SiGe pmosfet at input power P in of dbm with Si/SiGe thickness ratio of.9 results in larger output power and power-added efficiency than those of the PA using either the pmosfet with Si/SiGe thickness ratio of.8 or with the. This is due to larger I m and V m from the SiGe pmosfet with Si/SiGe thickness ratio of.9 that those from the other two devices. To reduce NBTI sensitivity on the power amplifier, adaptive gate biasing technique [25] may be used. The adaptive gate biasing increases the gate voltage to compensate the drain current degradation due to NBTI stress effect. Thus, the change of output power and power-added efficiency after NBTI can be minimized. are extracted using BSIMPro + software. Fig. 5 shows the threshold voltage and hole mobility as a function of NBTI stress time. After NBTI the p-channel threshold voltage magnitude increases and l p decreases with stress time. The rate of change is much faster for the first 2 min and gradually saturates with stress time. The fresh and stressed model parameters are then used in Agilent Advanced Design System [22] for circuit simulation. Fig. 6a shows three stage inverters. The first stage inverter has identical transistors to the second and third stage transistors. The first stage inverter is used to generate realistic input waveform to the second stage inverter, while the third stage inverter is for the capacitive load of the second stage inverter. The pull-up delay of the second stage inverter is evaluated. As shown in Fig. 6b the pull-up delay increases with NBTI stress time, especially for the first 2 min of stress consistent with the drain current characteristics in Fig. 3. Out of the three different devices the inverter using pmosfet with SiGe channel exhibits smaller pull-up delay than its counterpart over a wide range of NBTI stress time. The inverter pull-up delay is inversely proportional to the drain current of the pmosfet. Fig. 7 shows a low-noise amplifier using two p-channel transistors. In Fig. 7 M 1 is the main transistor which dominates the RF performance, while M 2 is the cascode transistor mainly for input and output isolation. C shunt1, L in, C shunt2 are used for the input matching and L out1,c shunt3, and L out2 are for the output matching. The normalized noise figure of the LNA versus stress time is displayed in Fig. 8. The noise figure increases significantly with NBTI stress time, especially for the LNA using the pmos transistors. The NBTI effect on the RF power amplifier is also evaluated as shown in Fig. 9. InFig. 9 C in is the input coupling capacitor and C out is the output coupling capacitor. L in is used for the input matching 4. Conclusion High-k metal-gate SiGe p-channel MOSFETs have been fabricated to demonstrate the advantage of drain current over their Si channel control devices due to compressive strain in the SiGe channel. Interface states of SiGe pmosfets are extracted using charge-pumping measurement. The experimental data show that SiGe pmosfets have smaller interface states density than that of their Si control counterpart. The Si cap layer to SiGe channel thickness ratio of.9 gives better drain current driving capability and reduced NBTI degradation due to SiGe valence band offset. Impact of NBTI reliability on digital and RF circuits has been examined in ADS circuit simulation using the fresh and stressed BSIM4 model parameters extracted from device measurement data. The cascaded inverters exhibit smaller pull-up delay over a wide range of NBTI stress time when SiGe pmosfets are used. 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