University of Southern C alifornia School Of Engineering Department Of Electrical Engineering

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1 University of Southern C alifornia School Of Engineering Department Of Electrical Engineering EE 348: Homework Assignment #04 Spring, 2001 (Due 02/27/2001) Choma Problem #16: n monolithic circuits, diodes are commonly realized as appropriate interconnections of bipolar junction transistors (BJTs). To this end, the static volt ampere characteristics of each of the bipolar circuits shown in Fig. (P16) emulate those of a PN junction diode; that is, the indicated current,, relates to the indicated voltage,, in accordance with the approximate algebraic expression, n f T eff e 1. For each configuration, use the Ebers Moll model to deduce an expression for the effective diode saturation current, eff, in terms of the transport saturation current ( s ), the forward beta (β f ), the reverse beta (β r ), and the base-emitter junction injection coefficient (n f ), of the bipolar junction transistor. For simplicity, assume that the injection coefficients of both BJT junctions are identical, and ignore the intrinsic base (R b ), emitter (R e ), and collector (R c ) resistances. Also, assume that the junction injection coefficients, n f and n r, are identical. Problem #17: (a). (b). Fig. (P16) The basic current mirror in Fig. (P17) is typically designed to ensure that transistor Q1 is biased within in its linear active domain. f the circuit is to provide a static collector biasing current, CQ, that is nominally independent of temperature over reasonable baseemitter junction temperature excursions, the circuit must be designed so that the two transistors, Q1 and Q2, are electrically identical and conduct equal collector current densities. n turn, this design constraint guarantees that the two transistor base-emitter voltages, BE1 and BE2, match one another over a wide range of operating temperatures. Consider the case in which the baseemitter junction area of transistor Q1 is A 21 times larger than that of transistor Q2. (a). Assuming that the circuit is designed correctly to ensure acceptable temperature desensitization, derive an expression for the static collector current, CQ, in terms of circuit (c).

2 parameters, applied static voltages, and transistor h FE and BE. (b). What design criterion must be satisfied to render CQ almost independent of h FE? (c). Why is the biasing current, CQ, nominally independent of the voltage, P? (d). For a fixed collector load resistance, R l, what smallest value of applied static voltage, P, ensures transistor Q1 operation in its linear regime? CC P R 1 R l Q2 Q1 CQ R 2 R ee Fig. (P17) Problem #18: The three transistors in the base current compensated bias current mirror of Fig. (P18) are electrically identical and conduct identical collector current densities. As usual, the circuit is designed to ensure that all transistors operate in their respective linear regimes. CC P R R l Q3 CQ Q2 Q1 R x Fig. (P18) (a). Derive an expression for the bias current, CQ, in terms of circuit parameters, transistor h FE, and transistor BE. (b). What design requirements must be satisfied to render CQ almost independent of h FE? (c). What purpose is served by resistor R X? Would the circuit operate acceptably over wide Homework #04 35 Spring Semester, 2001

3 temperature ranges if R X were supplanted by an open circuit? Problem #19: The TN2219AM NPN transistor has the following abridged set of SPCE parameters. Use SPCE to generate, and submit plots of, the following static characteristic curves. Save copies of these plots; you will need them in subsequent homework assignments! (a). Base current ( B ) -versus- base-emitter voltage ( BE ) for collector-emitter voltages ( CE ) of 1.5, 2.5, and 3.5 volts. ary BE from zero -to- 800 m. (b). Collector current ( C ) -versus- BE for CE =1.5, 2.5, and 3.5 volts. ary BE from zero - to- 800 m. (c). Static current gain (h FE = C / B ) -versus- C for CE =1.5, 2.5, and 3.5 volts. ary C from 100 na -to- 10 ma, and plot C on a logarithmic scale. PARAMETER DESCRPTON ALUE UNTS S Transport Saturation Current 1.80 fa βf Forward Current Gain 140 NF B-E Junction Emission Coefficient 1.0 AF Forward Early oltage 54 volts KF Forward Knee Current 22 ma SE B-E Leakage Saturation Current 800 fa NE B-E Leakage Emission Coefficient 2.05 βr Reverse Current Gain 0.2 NR B-C Junction Emission Coefficient 1.0 RB Average Base Resistance 150 ohms RE Average Emitter Resistance 2 ohms RC Average Collector Resistance 120 ohms CJE Zero Bias B-E Junction Capacitance 5 ff JE B-E Built-n Potential 950 m MJE B-E Junction Grading Coefficient 0.5 CJC Zero Bias B-C Junction Capacitance 10 ff JC B-C Built-n Potential 790 m MJC B-C Junction Grading Coefficient 0.34 CJS Zero Bias Substrate Capacitance 50 ff JS Substrate-Collector Built-n Potential 700 m MJS Subs.-Collector Junction Grading Coeff. 0.5 TF Forward Minority Carrier Transit Time 9 psec TR Reverse Minority Carrier Transit Time 46.9 nsec Problem #20: Use the TN2219AM NPN transistor to design the circuit of Fig. (P17) to Homework #04 36 Spring Semester, 2001

4 meet the following requirements and specifications (presumed quoted at 27 ºC). CC = P = 3.3 volts Both transistors biased for linear operation Both transistors identical, inclusive of junction areas CQ = 1.5 CE1 = 1.5 volts R l 6R ee CQ changes by no more than 10% for temperatures ranging from 27 ºC - to- 75 ºC. Simulate the circuit, making sure to check the following performance indices. When the simulations do not track with either specifications or calculations, find out why and execute the required corrective actions. (a). Collector current ( CQ ) at temperature (T) = 27 ºC, 50 ºC, 75 ºC. (b). oltage at base of transistor Q1, with respect to ground, at T = 27 ºC, 50 ºC, 75 ºC. (c). oltage at collector of transistor Q1, with respect to ground, at T = 27 ºC, 50 ºC, 75 ºC. (d). oltage at emitter of transistor Q1, with respect to ground, at T = 27 ºC, 50 ºC, 75 ºC. Homework #04 37 Spring Semester, 2001

5 University of Southern C alifornia School Of Engineering Department Of Electrical Engineering EE 348: Homework Assignment #04 Spring, 2001 (SOLUTONS: Due 02/27/2001) Choma Problem #16: Homework #04 38 Spring Semester, 2001

University of Southern C alifornia School Of Engineering Department Of Electrical Engineering

University of Southern C alifornia School Of Engineering Department Of Electrical Engineering EE 348: Homework Assignment #05 Spring, 2002 (Due 03/05/2002) Choma Problem #18: The biasing circuit in Fig.