DESIGN GUIDE. Carrier Board. for SOM-6X80 Module

Transcription

1 ESIGN GUIE arrier oard for SOM-X80 Module

2 opyright opyright 08 VI Technologies Incorporated. ll rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise without the prior written permission of VI Technologies, Incorporated. Trademarks ll trademarks are the property of their respective holders. isclaimer No license is granted, implied or otherwise, under any patent or patent rights of VI Technologies. VI Technologies makes no warranties, implied or otherwise, in regard to this document and to the products described in this document. The information provided in this document is believed to be accurate and reliable as of the publication date of this document. However, VI Technologies assumes no responsibility for the use or misuse of the information (including use or connection of extra device/equipment/add-on card) in this document and for any patent infringements that may arise from the use of this document. The information and product specifications within this document are subject to change at any time, without notice and without obligation to notify any person of such change. VI Technologies, Inc. reserves the right the make changes to the products described in this manual at any time without prior notice.

3 Revision History Revision ate escription.00 08//08 Initial release iii

4 Table of ontents. Introduction.... ocument Overview.... cronyms Used.... Schematic onventions.... General arrier oard Recommendations.... P Stackup Layer P Stackup Example Layer P Impedance ontrol.... General Layout and Routing Guidelines..... Routing Styles and Topology..... General Trace ttribute Recommendation General lock Routing onsiderations SOM-X80 Module and SOM R SOIMM Slot Specification Overview SOM-X80 Module Placement SOM-X80 Module Mechanical haracteristics SOM-X80 Module and arrier oard imensions SOM R SOIMM Slot..... SOM R SOIMM Slot imensions..... SOM R SOIMM Slot Footprint.... SOM R SOIMM Slot Pin ssignments.... Layout and Routing Recommendation.... HMI Interface..... HMI Signal efinition..... HMI Layout and Routing Recommendations HMI Reference Schematics Ethernet Interface Ethernet Signal efinition Ethernet Layout and Routing Recommendations..... Ethernet Reference Schematics.... US Interface..... US Signal efinition..... US Layout and Routing Recommendations..... US Reference Schematics.... OM and URT Interface OM and URT Signal efinition OM and URT Layout and Routing Recommendations OM and URT Reference Schematics L Interface L Signal efinition L Layout and Routing Recommendations..... L Reference Schematics.... Touch Panel Interface..... Touch Panel Signal efinition..... Touch Panel Layout and Routing Recommendations..... Touch Panel Reference Schematics....7 GPIO Interface GPIO Signal efinition GPIO Layout and Routing Recommendation....8 I² Interface I² Signal efinition I² Layout and Routing Recommendation SPI Interface... 8 iv

5 .9. SPI Signal efinition SPI Layout and Routing Recommendation udio Interface udio Signal efinition udio Layout and Routing Recommendations udio Interface Reference Schematics S Interface..... S Signal efinition..... S Layout and Routing Recommendations..... S Interface Reference Schematics... ppendix..som arrier oard Reference Schematics... v

6 List of Figures Figure : Schematic conventions... Figure : Microstrip P stackup example... Figure : Stripline P stackup example... Figure : -Layer P board stackup detail... Figure : Point-to-point and multi-drop examples... Figure : aisy-chain example... Figure 7: lternate multi-drop example... Figure 8: Signal trace width and spacing example... 7 Figure 9: ifferential signal trace width and spacing example... 7 Figure 0: Suggested clock trace spacing... 8 Figure : lock trace layout in relation to the ground plane... 8 Figure : Series termination for multiple clock loads... 8 Figure : SOM-X80 module placement example on the carrier board... 9 Figure : arrier board with SOM-X80 module (side view)... 9 Figure : arrier board and SOM-X80 module height distribution (side view)... 9 Figure : imensions of the SOM-X80 module... 0 Figure 7: imensions of the reference carrier board... 0 Figure 8: imensions of the SOM R SOIMM slot (top view)... Figure 9: imensions of the SOM R SOIMM slot (side view)... Figure 0: P footprint of the SOM R SOIMM slot... Figure : P footprint of the SOM R SOIMM slot with SOM-X80 module... Figure : SOM R SOIMM slot schematics... Figure : HMI routing topology... Figure : HMI differential trace width and spacing example... 7 Figure : HMI single-ended trace width and spacing example... 7 Figure : HMI reference circuitry... 9 Figure 7: Ethernet routing topology... 0 Figure 8: Ethernet single-ended trace width and spacing example... Figure 9: Ethernet differential trace width and spacing example... Figure 0: Ethernet reference circuitry... Figure : US routing topology... Figure : US differential signal routing example... Figure : US differential trace width and spacing example... Figure : US host reference circuitry... Figure : US client reference circuitry... Figure : OM and URT routing topology... 8 Figure 7: OM and URT reference circuitry... 9 Figure 8: L routing topology... Figure 9: L reference circuitry... Figure 0: Touch panel routing topology... Figure : Touch panel reference circuitry... Figure : Line-in & reference circuitry... 0 Figure : Headphone reference circuitry... 0 Figure : Mono speaker out reference circuitry... 0 Figure : Right channel speaker reference circuitry... Figure : Left channel speaker reference circuitry... Figure 7: Onboard microphone reference circuitry... Figure 8: S routing topology... Figure 9: S reference circuitry... vi

7 List of Tables Table : cronyms used... Table : -Layer P impedance control... Table : Recommended trace width and spacing... 7 Table : SOM R SOIMM slot sample... Table : SOM R SOIMM slot pinouts... Table : HMI signal definition... Table 7: HMI trace properties... 7 Table 8: HMI layout guidelines... 8 Table 9: HMI routing topology and signal type... 8 Table 0: Ethernet signal definition... 0 Table : Ethernet trace properties... Table : Ethernet layout guidelines... Table : Ethernet reference plane, signal type and routing topology... Table : US signal definition... Table : US trace properties... Table : US termination option, signal type and routing topology... Table 7: US layout guidelines... Table 8: OM and URT signal definition... 7 Table 9: OM and URT trace properties... 8 Table 0: OM and URT topology, signal type and layout guidelines... 9 Table : L signal definition... 0 Table : L trace properties... Table : L signal type, topology and reference plane... Table : L layout guidelines... Table : Touch panel signal definition... Table : Touch panel trace properties... Table 7: Touch panel signal type, routing topology and reference plane... Table 8: Touch panel layout guidelines... Table 9: GPIO signal definition... Table 0: GPIO trace properties... Table : GPIO signal type, topology and layout guidelines... Table : I² signal definition... 7 Table : I² trace properties... 7 Table : I² signal type, topology and layout guidelines... 7 Table : SPI signal definition... 8 Table : SPI trace properties... 8 Table 7: SPI signal type, topology and layout guidelines... 8 Table 8: udio signal definition... 9 Table 9: udio trace properties... 9 Table 0: udio signal type, topology and layout guidelines... 0 Table : S signal definition... Table : S trace properties... Table : S signal type, topology and layout guidelines... vii

8 . Introduction This document provides design guidelines and rule recommendations for the developers of a carrier board that supports the features of the VI SOM-X80 module. This document includes the layout and routing guidelines for general board designs and major underlying interfaces (e.g. HMI, Ethernet, US). In addition, the document includes the placement and mechanical information on the SOM R SOIMM slot which is used to provide high-speed interfaces between the carrier board and the module. Please note that this document is considered to be a reference guide only. This document is not intended to be a specification. ll information and examples listed below are considered to be accurate as of the publication date. However, developers must be aware that this document is only a reference guide.. ocument Overview brief description of each chapter is given below. hapter : Introduction This chapter briefly introduces the structure of the design guide document. hapter : General arrier oard Recommendations The general design schemes and recommended layout rules are shown in this chapter. hapter : SOM-X80 Module and SOM R SOIMM Slot Specification Overview etailed information about the SOM-X80 module and SOM R SOIMM slot placement and dimensions are described in this chapter. hapter : Layout and Routing Recommendations etailed layout and routing guidelines for each major interface are described in this chapter. ppendix : arrier oard Reference Schematics Reference schematics of the SOM evaluation carrier board.

9 . cronyms Used Term escription SI pplication-specific Integrated ircuit R ouble ata Rate EMI Electromagnetic Interference ES Electrostatic-discharge GPIO General Purpose Input/Output HMI High-efinition Multimedia Interface I² Inter-I I Integrated ircuit L Liquid-rystal isplay LVS Low-Voltage ifferential Signaling PP Point-to-Point P Printed ircuit oard RG Red, Green and lue RJ- Registered Jack RS- Recommend Standard number S Secure igital SOIMM Small Outline ual In-line Memory Module SMT Surface Mount Technology SOM System-On-Module SPI Serial Peripheral Interface URT Universal synchronous Receiver-Transmitter US Universal Serial us US OTG US On-The-Go Table : cronyms used

10 . Schematic onventions The reference schematics depicted in this document show the directional flow of the signals. irectional flow is indicated by the pointed ends of the arrow shapes. Input signal flow idirec onal signal flow I/onnector Output signal flow Figure : Schematic conventions

11 . General arrier oard Recommendations This section contains general guidelines for the P stackup and the layout of traces. The general guidelines for routing style, topology, and trace attribute recommendations are also discussed.. P Stackup The P stackup consists of signal layers and reference layers (power and ground). The signal layers are referred to as the component layer (top), inner layer and solder layer (bottom). The carrier board designers can choose between two basic categories of P stackup design: microstrip and stripline. The microstrip designs have the outer signal layers exposed. The stripline designs have the outermost signal layers shielded by reference layers. The following figures show an example of microstrip and stripline designs.. omponent layer Microstrip stackup design Ground layer Inner layer Signal layers Power layer Ground layer Solder layer Reference layers Figure : Microstrip P stackup example Stripline stackup design Ground layer omponent layer Inner layer Signal layers Power layer Solder layer Ground layer Reference layers Figure : Stripline P stackup example The choice of microstrip or stripline design depends on the application for which the carrier board is being designed. If the carrier board is being designed for locations where sensitivity to EMI is an issue, a stripline design is recommended for reducing EMI and noise coupling. For applications where the tolerance for EMI levels is greater, a microstrip design is recommended to reduce costs. ue to the inherent nature of stripline P stacks, broad-side coupling is possible.

12 .. -Layer P Stackup Example The following figure shows the recommended -layer P stackup design for the carrier board of the SOM- X80 module. LYER Soldermask = 0.79mil Pla ng = 0.8mil TOP =.0oz (.mil) opper foil + Pla ng PP (Er) =.7 mil LYER GROUN =.0oz (.8mil) opper foil ore (Er) =.88mil.8mil LYER POWER =.0oz (.8mil) PP (Er) =.7 mil opper foil LYER OTTOM =.0 oz (.mil) opper foil + Pla ng Pla ng = 0.8mil Soldermask = 0.79mil Figure : -Layer P board stackup detail.. -Layer P Impedance ontrol ± 0% 0Ω Single-end 0Ω Single-end Ω Single-end Layer mil 8mil 7mil Layer mil 8mil 7mil 8Ω ifferential 7.8 : 9 : 7.8 mil 7.8 : 9 : 7.8 mil 90Ω ifferential 7. : 8 : 7. mil 7. : 8 : 7. mil 90Ω ifferential 7 : 7. : 7 mil 7 : 7. : 7 mil Table : -Layer P impedance control

13 . General Layout and Routing Guidelines This section provides general layout rules and routing guidelines for designing carrier boards for the SOM-X80 module... Routing Styles and Topology Topology is the physical connectivity of a net or a group of nets. There are two types of topologies for a carrier board layout: point-to-point (PP) and multi-drop. n example of these topologies is shown in Figure. Figure : Point-to-point and multi-drop examples High-speed bus signals are sensitive to transmission line stubs, which can result in ringing on the rising edge caused by the high impedance of the output buffer in the high state. In order to maintain better signal quality, transmission stubs should be kept as short as possible (less than. ). Therefore, daisy chain style routing is strongly recommended for these signals. Figure below shows an example of daisy chain routing. Figure : aisy-chain example If daisy chain routing is not allowed in some circumstances, different routings may be considered. n alternative topology is shown in Figure 7. In this case, the branch point is somewhere between both ends. It may be near the source or near the loads, but being close to the load side is best. The separated traces should be equal in length. Figure 7: lternate multi-drop example

14 .. General Trace ttribute Recommendation mil trace width and 0mil spacing are generally advised for most signal traces on a carrier board layout. To reduce trace inductance the minimum power trace width is recommended to be 0mil. s a quick reference, the overall recommended trace width and spacing for different trace types are listed in Table, and the recommended trace width and spacing for each signal group is shown in hapter. Table : Recommended trace width and spacing Trace Type Trace Width (mil) Spacing (mil) Regular Signal or wider 0 or wider Interface or us Reference Voltage Signal 0 or wider 0 or wider Power 0 or wider 0 or wider General rules for minimizing crosstalk in high-speed bus designs are listed below: Maximize the distance between traces. Maintain 0mil minimum spaces between traces wherever possible. Maximize the distance (0mil minimum) between two adjacent routing areas of different signal groups wherever possible. void parallelism between traces on adjacent layers. Provide stable reference planes for all high-speed signals. Never route high-speed signals over splits in their perspective reference planes. Select a board stack-up that minimizes coupling between adjacent traces. S W Signal S Figure 8: Signal trace width and spacing example Reference Plane S W Signal S W Signal S Reference Plane Figure 9: ifferential signal trace width and spacing example Notes:. W: Trace width. S: The spacing to other traces. S: ifferential pair spacing 7

15 .. General lock Routing onsiderations The clock routing guidelines are listed below: The recommended clock trace width is mil. The minimum space between one clock trace and adjacent clock traces is 0mil. The minimum space from one segment of a clock trace to other segments of the same clock trace is at least two times of the clock width. That is, more space is needed from one clock trace to others or its own trace to avoid signal coupling (see Figure 0). The clock traces should be parallel to their reference ground planes. That is, a clock trace should be right beneath or on top of its reference ground plane (see Figure ). The series terminations (damping resistors) are needed for all clock signals (typically 0Ω to 7Ω). When two loads are driven by one clock signal, the series termination layout is shown in Figure. When multiple loads (more than two) are applied, a clock buffer solution is preferred. Isolating clock synthesizer power and ground planes through ferrite beads or narrow channels (typically 0mil to 0mil wide) is preferred. No clock traces on the internal layer if a six-layer board is used. Figure 0: Suggested clock trace spacing Figure : lock trace layout in relation to the ground plane Figure : Series termination for multiple clock loads 8

16 . SOM-X80 Module and SOM R SOIMM Slot Specification Overview. SOM-X80 Module Placement The following figure shows the depiction of the top view of the carrier board P (SOM) with the appropriate amount of space reserved for the SOM-X80 module. O mm.mm 8mm 7.mm Figure : SOM-X80 module placement example on the carrier board arrier board. SOM-X80 Module Mechanical haracteristics VI SOM-X80 module Screw SOM R SOIMM slot arrier board P Standoff spacer Figure : arrier board with SOM-X80 module (side view) 8mm.mm.mm.mm.8mm Figure : arrier board and SOM-X80 module height distribution (side view) 9

17 . SOM-X80 Module and arrier oard imensions The following figures show the mechanical dimensions of the SOM-X80 module and the reference carrier board (SOM). O mm.mm mm 0mm 9mm 7.mm mm Figure : imensions of the SOM-X80 module O mm mm 77mm mm.8mm mm 00mm 9.mm VTS8 SOM.8mm Figure 7: imensions of the reference carrier board.mm 0mm 0

18 . SOM R SOIMM Slot The SOM R SOIMM slot can handle high-speed signals and comprises 0 pins to connect the SOM-X80 module. Table shows the specification sample of the SOM R SOIMM slot. Part Number escription Height Vendor Table : SOM R SOIMM slot sample R SOIMM.H.V ST PLSTI LTH SSEMLY.. SOM R SOIMM Slot imensions.mm eren 0.mm.70mm.70mm 7.90mm±0..9mm±0..mm 0.mm 9mm 0.mm 9mm mm.mm mm.7mm 7.mm Figure 8: imensions of the SOM R SOIMM slot (top view).9mm±0..mm mm.mm mm.0mm±0.0.8mm±0. SOM-X80 module.0mm 0.80mm mm 0.0mm 9.80mm mm mm 7.mm Slot 0.0mm PIN ONTRT Figure 9: imensions of the SOM R SOIMM slot (side view).0mm±0.0 mm.mm REF. 0.mm 0.8mm

19 .. SOM R SOIMM Slot Footprint 9mm 0.mm±0.0 Pin # 0 mm.mm.mm Pin # 0 Ø.0mm±0.0 (Hole) 0.0mm (Pitch) 9mm Figure 0: P footprint of the SOM R SOIMM slot mm mm Pin # Pin # mm mm.0mm±0.0 (X).0mm±0.0 (X) mm±0.0 Ø.0mm±0.0 (Hole) arrier board P Figure : P footprint of the SOM R SOIMM slot with SOM-X80 module

20 . SOM R SOIMM Slot Pin ssignments The SOM R SOIMM slot consists of 0 pins. The pinouts of the SOM R SOIMM slot are shown below. Pin Signal Pin Signal USTT0 GN USI0 nush+ USSW0 nush- 7 GN 8 GN 9 SPI0MISO 0 nush+ SPI0MOSI nush- SPI0LK GN SPI0SS0- nush0+ 7 GN 8 nush0-9 S0LK 0 GN S0T URT_TS S0WP URT_RTS S0T0 URT_RX 7 S0M 8 URT_TX 9 S0T 0 URT_TS S0T URT_RTS S0PWRSW URT_RX S0 URT_TX 7 M0_LINK 8 URT_RTS 9 M0_SPEE 0 URT_RX PWMOUT0 URT_TX PWMOUT URT_TS GN URT_RTS 7 NET_RX- 8 URT_TS 9 NET_RX+ 0 URT_TX GN URT_RX NET_TX- VHSYN NET_TX+ VVSYN 7 GN 8 VEN 9 nhmihp 0 VLK nhmie VOUT0 nhmis VOUT8 nhmisl VOUT 7 GN 8 VOUT0 9 N 70 VOUT 7 N 7 VOUT 7 GN 7 VOUT 7 nhmilk+ 7 VOUT 77 nhmilk- 78 VOUT Pin Signal Pin Signal 79 GN 80 VOUT 8 nhmi0+ 8 VOUT9 8 nhmi0-8 VOUT7 8 GN 8 VOUT 87 nhmi+ 88 VOUT 89 nhmi- 90 VOUT 9 GN 9 VOUT9 9 nhmi+ 9 VOUT 9 nhmi- 9 VOUT8 97 GN 98 VOUT7 99 VIN0 00 VOUT0 0 VIN 0 VOUT 0 VIN 0 VOUT 0 VIN 0 VOUT 07 VIN 08 VOUT 09 VLK 0 URTRX GN URTTX VIN N MOUT N 7 VIN 8 URT0RX 9 VIN7 0 URT0TX VVSYN SM VHSYN SLK GPIO ST0 7 GPIO 8 ST 9 GN 0 ST SPK_OUT_R- ST SPK_OUT_R+ SPWRSW GN SWP 7 SPK_OUT_L- 8 I0S 9 SPK_OUT_L+ 0 I0SL GN ISL HPOUTR IS OUT IS 7 HPOUTL 8 ISL 9 MIIS 0 SUS_GPIO0 GN PWRG LINPUT WKEUP0 LINPUT SPIMOSI

21 Pin Signal Pin Signal 7 LINPUT 8 GN 9 GN 0 SPILK RINPUT SPISS0- RINPUT SPIMISO GN GPIO 7 WKEUP 8 GPIO0 9 PWRENV 70 GPIO 7 WKEUP 7 GPIO 7 IRIN 7 GPIO 7 PWRENMEM 7 GPIO 77 PWRENV 78 GPIO 79 SUS_GPIO 80 GPIO9 8 PWRTN- 8 GPIO7 8 RSMRST- 8 VSUS 8 PWMOUT 8 VSUS 87 PWMOUT 88 V 89 PWREN_MIN 90 V 9 V-T 9 V 9 N 9 N 9 VIN 9 GN 97 VIN 98 GN 99 VIN 00 GN 0 VIN 0 GN 0 VIN 0 GN Table : SOM R SOIMM slot pinouts

22 Figure : SOM R SOIMM slot schematics

23 . Layout and Routing Recommendation The information presented in this chapter includes the signal definition, topology, layout and routing guidelines for each bus interface, and reference schematics example. The information provided is intended for designing carrier boards that are compliant with the SOM-X80 module.. HMI Interface The SOM-X80 module features one HMI interface. The HMI interface uses four control signals, one differential clock, and three differential data pair signals that carry video and audio signals... HMI Signal efinition The following table provides the definition of the HMI signals that are implemented in the SOM R SOIMM slot. Signal Name Pin # I/O escription nhmi0+ 8 nhmi0-8 nhmi+ 87 nhmi- 89 nhmi+ 9 nhmi- 9 nhmilk+ 7 nhmilk- 77 Table : HMI signal definition O HMI differential pair lines lane 0 O HMI differential pair lines lane O HMI differential pair lines lane nhmisl IO HMI SL nhmis IO HMI S O HMI differential pair clock lines nhmie O HMI consumer electronics connector nhmihp 9 O HMI hot plug detect SOM R SOIMM Slot nhmi0+ nhmi0- L L Route ifferen ally EMI filter ES ES L L nhmi+ nhmi- L L Route ifferen ally ES L L SOM-X80 Edge finger nhmi+ nhmilk+ nhmi- nhmilk- L L L L Route ifferen ally Route ifferen ally ES ES L L L L HMI port nhmis nhmisl L L N-hannel igital FET ES L L nhmie L L nhmihp L L Figure : HMI routing topology Note: The EMI filters and ES components must be placed near the HMI port.

24 .. HMI Layout and Routing Recommendations Trace lengths should be kept to a minimum. Each trace of differential pairs should not have more than two via holes. Each differential pairs signal should route to parallel to each other with the same trace length. ifferential pair should be all referenced to ground. Route the differential pairs on a single layer adjacent to a ground plane. The spacing between the differential pair signal and other signals should be at least three times the trace width. S HMI Signal ifferen al Pair W S W S Reference Plane Figure : HMI differential trace width and spacing example S HMI Signal Single-ended W S Reference Plane Figure : HMI single-ended trace width and spacing example Signal Group ata Signal Name nhmi0+ nhmi+ nhmi+ nhmi0- nhmi- nhmi- Trace Impedance 00Ω ± % (ifferential) Trace & Spacing (mil) (S : W : S : W : S) : : 7 : : Pair to Pair Trace Mismatch <mil (ifferential) Spacing to Other Signal mil lock ontrol nhmilk+ 00Ω ± % nhmilk- (ifferential) nhmisl nhmis nhmie nhmihp 0Ω ± % : : 7 : : : 0 (W:S) <mil (ifferential) mil mil 0mil Table 7: HMI trace properties 7

25 Signal Group Signal Name Routing Layer ata lock ontrol nhmi0+ nhmi+ nhmi+ nhmilk+ nhmisl nhmis nhmie nhmihp Table 8: HMI layout guidelines ccumulated Trace Length (L+ L = LT) Length ifference (mil) To lock In Group Top/ottom LT < " <00 <000 Top/ottom LT < " <00 <000 Top/ottom LT < " <00 <000 nhmi0- nhmi- nhmi- nhmilk- Signal Group Signal Name Reference Plane Routing Topology Signal Type nhmi0+ nhmi0- ata nhmi+ nhmi- Ground Point-to-Point ifferential Pairs nhmi+ nhmi- lock nhmilk+ nhmilk- Ground Point-to-Point ifferential Pairs nhmisl ontrol nhmis nhmie Ground Point-to-Point Single-ended nhmihp Table 9: HMI routing topology and signal type 8

26 .. HMI Reference Schematics Figure : HMI reference circuitry 9

27 . Ethernet Interface The SOM-X80 module features one Ethernet (0/00Mbps) interface. The Ethernet interface consists of two differential data signals and two control signals for activity link and speed indicators... Ethernet Signal efinition The following table provides the definition of the Ethernet signals that are implemented in the SOM R SOIMM slot. Signal Name Pin # I/O escription NET_TX+ NET_TX- NET_RX+ 9 NET_RX- 7 Table 0: Ethernet signal definition O O Ethernet differential pair lines Transmit Ethernet differential pair lines Receive M0_SPEE 9 O Ethernet controller 0 00Mbps speed indicator M0_LINK 7 O Ethernet controller 0 00Mbps link indicator SOM R SOIMM Slot NET_TX+ L Route ifferen ally L NET_TX- L L SOM-X80 Edge finger NET_RX+ NET_RX- L L Route ifferen ally Magne c module (Transformer) L L RJ- port M0_SPEE LT M0_LINK LT Figure 7: Ethernet routing topology Note: The magnetic module has to be placed as close as possible to the RJ- port. The distance must be less than ". 0

28 .. Ethernet Layout and Routing Recommendations Route differential pairs close together and away from other signals. Route any other trace parallel to one of the differential trace. Keep trace length within each differential pair equal. Keep proper impedance between two traces within a differential pair. Each trace of differential pairs should not have more than two via holes. The spacing between the differential pair signal and other signals should be at least three times the trace width. Each differential pair of signals is required to be parallel to each other with the same trace length (Tolerance ±0mil) on the component (top) layer and to be parallel to a respective ground plane. The length difference between the shortest and longest pairs should be less than 00mil. The accumulated trace length of the differential signals pair between the SOM R SOIMM slot and magnetic module should be less than ". The accumulated trace length of the differential signals pair between the magnetic module and RJ- connector should be less than ". Isolate ground plane and connect to chassis. Keep each differential pair on the same plane. To prevent any noise from injecting into the differential pairs, be sure to keep digital signals or other signals away from the differential signals. The external magnetic module should be placed close to the RJ- connector to limit EMI emissions. S Ethernet Signal Single-ended W S Reference Plane Figure 8: Ethernet single-ended trace width and spacing example S Ethernet Signal ifferen al Pair W S W S Reference Plane Figure 9: Ethernet differential trace width and spacing example.

29 Signal Group ata ontrol Trace Impedance 00Ω ± % (ifferential) Trace & Spacing (mil) (S : W : S : W : S) Pair to Pair Trace Mismatch Spacing to Other Signal 0 : 0 : : 0 : 0 0mil 0mil Ω ± % :0-0mil Table : Ethernet trace properties Signal Group Signal Name Routing Layer ata ontrol NET_TX+ NET_RX+ M0_SPEE M0_LINK Table : Ethernet layout guidelines ccumulated Trace Length (L+ L = LT) Length ifference (mil) To lock Top/ottom LT < " <00 Top/ottom LT < " <00 Signal Name NET_TX+ NET_TX- NET_RX+ NET_RX- M0_SPEE M0_LINK NET_TX- NET_RX- Signal Group Signal Name Reference Plane Signal Type Routing Topology NET_TX+ ata NET_TX- NET_RX+ Ground/Power ifferential Pairs Point-to-Point NET_RX- ontrol M0_SPEE M0_LINK Ground/Power Single-ended Point-to-Point Table : Ethernet reference plane, signal type and routing topology.. Ethernet Reference Schematics Figure 0: Ethernet reference circuitry

30 . US Interface The SOM-X80 module features three US.0 interfaces. Two of the three US interfaces can only be used as a host. The other interface can be configured to be used as either the host or client. The US interface signals use three bi-directional differential data pairs... US Signal efinition The following table provides the definition of the US signals that are implemented in the SOM R SOIMM slot. Signal Name Pin # I/O escription nush0+ OTG Universal Serial us port 0, data+ IO nush0-8 OTG Universal Serial us port 0, datanush+ 0 Universal Serial us port, data+ IO nush- Universal Serial us port, datanush+ Universal Serial us port, data+ IO nush- Universal Serial us port, data- USTT0 I Universal Serial us device attach detect USI0 I Port I pin USSW0 I Universal Serial us power control pin Table : US signal definition SOM R SOIMM Slot nush+ nush- L L EMI filter ES L L US port ES nushnush+ L L L L US port ES SOM-X80 Edge finger nush0+ nush0- USTT0 R L L L L US port (Micro US) R USSW0 US Overcurrent Protector I V VSUS R R USI0 R Figure : US routing topology

31 .. US Layout and Routing Recommendations The differential pair signals should be all referenced to ground. Each trace of differential pairs should not have more than two via holes. ifferential pair route in parallel and in equal length. The amount of vias and corners used for the US signal layout should be minimized; this is to prevent the occurrence of reflection and impedance changes. Each pair of US data lines is required to be parallel to each other with the same trace length, and not parallel with other signals to minimize crosstalk. Separate the signal traces into similar groups and route similar signal traces together. In addition, it is recommended to have differential pairs routed together on the carrier board. ontrol trace signals impedance should maintain Ω ± 0%. For the US traces, do not route them under oscillators, crystals, clock synthesizers, magnetic devices or I s which could be using duplicate clocks. The routing example for two pairs of US data buses is shown in Figure. Recommended SOM R SOIMM Slot US port nush+ nush- Not recommended nush- nush+ US port Figure : US differential signal routing example US Signal ifferen al Pair S W S W S W S W S Reference Plane Figure : US differential trace width and spacing example

32 Trace Impedance Trace & Spacing (mil) (S : W : S : W : S) Pair to Pair Trace Mismatch Spacing to Other Signal 90Ω ± % 0 : 7: 7. : 7 : 0 00mil 0mil Ω ± 0% : 0-0mil Signal Group ata ontrol Port Port Port Signal Name nush+ nush+ nush0+ USTT0 USI0 USSW0 Termination Option Table : US termination option, signal type and routing topology Signal Type Topology 90Ω ifferential ata Pairs Point-to-Point 0Ω - Point-to-Point Signal Group Signal Name Routing Layer ata ontrol Port Port Port Table 7: US layout guidelines nush+ nush+ nush0+ Signal Group Signal Name nush+ nushnush+ ata nushnush0+ nush0- USTT0 ontrol USI0 USSW0 Table : US trace properties nush- nush- nush0- nush- nush- nush0- USTT0 USI0 USSW0 Length ifference (In Pair) ccumulated Trace Length (L+ L = LT) Top/ottom <00mil LT < " Top/ottom - LT < "

33 .. US Reference Schematics Figure : US host reference circuitry The US port mode can be controlled by the signal USI0. In the reference circuitry example below, the USI0 signal is referenced to ground that makes the US port mode as client US (or US OTG port). Figure : US client reference circuitry

34 . OM and URT Interface The SOM-X80 module features OM and URT interfaces that enable the interfacing of four OM or two URT on the carrier board. The four OM interfaces are used for RS- serial communications and the two URT can be used for TX/RX, RTS, TS and debugging TX/RX... OM and URT Signal efinition The following table provides the definition of the OM and URT signals that are implemented in the SOM R SOIMM slot. Signal Name Pin # I/O escription URT_TX O URT Port- transmit data URT_RX I URT Port- receive data URT_RTS O URT Port- request to send URT_TS 0 I URT Port- clear to send URT_TX 8 O URT Port- transmit data URT_RX I URT Port- receive data URT_RTS O URT Port- request to send URT_TS I URT Port- clear to send URT_TX O URT Port- transmit data URT_RX 0 I URT Port- receive data URT_RTS 8 O URT Port- request to send URT_TS I URT Port- clear to send URT_TX 0 O URT Port- transmit data URT_RX I URT Port- receive data URT_RTS O URT Port- request to send URT_TS 8 I URT Port- clear to send URTTX O URT Port- transmit data URTRX 0 I URT Port- receive data URT0TX 0 O URT Port-0 transmit data URT0RX 8 I URT Port-0 receive data Table 8: OM and URT signal definition 7

35 SOM R SOIMM Slot ES URT_TX L L L L URT_RX URT_RTS L L L L Tranceiver I L L L L OM port URT_TS L L L L URT pin header ES URT_TX L L L L URT_RX URT_RTS L L L L Tranceiver I L L L L OM port URT_TS L L L L SOM-X80 Edge finger ES URT_TX L L L L URT_RX URT_RTS L L L L Tranceiver I L L L L OM port URT_TS L L L L URT pin header ES URT_TX L L L L URT_RX URT_RTS L L L L Tranceiver I L L L L OM port URT_TS L L L L Figure : OM and URT routing topology.. OM and URT Layout and Routing Recommendations The transmit and receive data trace signals should be routed in parallel and in equal length. The amount of vias and corners used for the OM and URT signal layout should be minimized; this is to prevent the occurrence of reflection and impedance changes. ontrol trace signals impedance should maintain Ω ± 0%. Signal Group ata ontrol Signal Name URT[:]_TX URT[:]_RX URT[:0]TX URT[:0]RX URT[:]_TS URT[:]_RTS Trace (mil) (Width : Spacing) Trace Impedance Spacing in Other Group : Ω ± 0% mil : Ω ± 0% mil Table 9: OM and URT trace properties 8

36 Signal Group Signal Name Signal Type Topology ata ontrol URT[:]_TX URT[:]_RX URT[:0]TX URT[:0]RX URT[:]_TS URT[:]_RTS Table 0: OM and URT topology, signal type and layout guidelines.. OM and URT Reference Schematics Reference Plane ccumulated Trace Length (L + L + L + L = LT) Single-ended Point-to-Point Ground/Power <0" Single-ended Point-to-Point Ground/Power <0" Figure 7: OM and URT reference circuitry 9

37 . L Interface The SOM-X80 module features one (RG) L interface. The L interface is a parallel bus signal provided for interfacing the L connector for LVS L display as the main display interface. The L interface is a singlechannel that supports 8-bit and -bit interfaces... L Signal efinition The following table provides the definition of the L signals that are implemented in the SOM R SOIMM slot. Signal Name Pin # I/O escription VOUT0 O VOUT O VOUT 7 O VOUT 70 O VOUT 7 O VOUT 7 O VOUT 78 O VOUT7 8 O VOUT8 O VOUT9 8 O VOUT0 8 O VOUT 88 O VOUT 90 O VOUT 80 O VOUT 9 O VOUT 8 O VOUT 0 O VOUT7 98 O VOUT8 9 O VOUT9 9 O VOUT0 00 O VOUT 0 O VOUT 08 O VOUT 0 O Table : L signal definition lue L data signal Green L data signal Red L data signal VHSYN O L Line Horizontal Sync VVSYN O L Frame Vertical Sync VEN 8 O L ata Enable VLK 0 O L lock 0

38 SOM R SOIMM Slot VOUT:0] LT RS SOM-X80 Edge finger VEN VHSYN VSYN VLK LT LT LT LT R L connector L panel Figure 8: L routing topology.. L Layout and Routing Recommendations RG data signal traces should be designed to be as short as possible. In order to maximize the noise rejection characteristics of the RG video outputs, it is then recommended to route the RG video outputs on the top layer over a solid ground plane. The routing for the RG signals should be as similar as possible (i.e., same routing layer, same number of vias, same routing length and same bends). Route the RG data trace signals and two sync signals (VHSYN and VVSYN) as a single-ended signal with a trace impedance of Ω. Signal Group ata ontrol Signal Name VOUT[7:0] VOUT[:8] VOUT[:] VHSYN VVSYN Table : L trace properties Trace Impedance Trace (mil) (Width : Spacing) Trace Mismatch Spacing to Other Signal Ω ± 0% : 0 000mil 0mil Ω ± 0% : 0 000mil 0mil lock VLK Ω ± 0% : - - Signal Group Signal Name Signal Type Topology Reference Plane VOUT[7:0] ata VOUT[:8] Single-ended Point-to-Point Ground/Power VOUT[:] ontrol VHSYN VVSYN Single-ended Point-to-Point Ground/Power lock VLK Single-ended Point-to-Point Ground/Power Table : L signal type, topology and reference plane

39 Signal Group Signal Name Routing Layer ata ontrol VOUT[7:0] VOUT[:8] VOUT[:] VHSYN VVSYN Table : L layout guidelines Length ifference (mil) To lock In Group Top/ottom <00 <000 Top/ottom <00 <000 ccumulated Trace Length (LT) Route to Minimum (or <") Route to Minimum (or <") lock VLK Top/ottom L Reference Schematics Figure 9: L reference circuitry

40 . Touch Panel Interface The SOM-X80 module features a touch panel interface for capacitive touch screens. It allows the integration of the touch screen solution on the carrier board. The touch panel interface is an interface connection between the SOM R SOIMM slot, capacitive touch sensor controller, and touch panel connector. The touch panel interface supports -wire and -wire capacitive touch screens... Touch Panel Signal efinition The following table provides the definition of the touch panel signals. From SOM R SOIMM Slot to apacitive Touch Sensor ontroller Signal Name Pin # I/O escription GPIO 7 O TP reset signal GPIO 7 O TP interrupt signal IS O TP I² ata ISL 8 O TP I² lock From apacitive Touch Sensor ontroller to Touch Panel onnector Signal Name Pin # I/O escription RIVE00 O apacitive touch I drive line-0 RIVE0 O apacitive touch I drive line- RIVE0 O apacitive touch I drive line- RIVE0 O apacitive touch I drive line- RIVE0 O apacitive touch I drive line- RIVE0 7 O apacitive touch I drive line- RIVE0 8 O apacitive touch I drive line- RIVE07 9 O apacitive touch I drive line-7 RIVE08 9 O apacitive touch I drive line-8 RIVE09 8 O apacitive touch I drive line-9 RIVE0 7 O apacitive touch I drive line-0 RIVE O apacitive touch I drive line- RIVE O apacitive touch I drive line- RIVE O apacitive touch I drive line- RIVE O apacitive touch I drive line- RIVE O apacitive touch I drive line- SENSE00 I apacitive touch I sense line-0 SENSE0 I apacitive touch I sense line- SENSE0 I apacitive touch I sense line- SENSE0 I apacitive touch I sense line- SENSE0 I apacitive touch I sense line- SENSE0 I apacitive touch I sense line- SENSE0 7 I apacitive touch I sense line- SENSE07 8 I apacitive touch I sense line-7 SENSE08 9 I apacitive touch I sense line-8 SENSE09 0 I apacitive touch I sense line-9 Table : Touch panel signal definition

41 SOM R SOIMM Slot SOM-X80 Edge finger GPIO GPIO ISL IS L L L L RS TP_RESET TP_INT TP_SL TP_S apaci ve Touch Sensor ontroller L L RIVE[:00] SENSE[09:00] Touch Panel onnector apaci ve Touch screen Figure 0: Touch panel routing topology.. Touch Panel Layout and Routing Recommendations Keep trace lengths as short as possible. It is recommended to route the traces on the top layer. The amount of vias and corners used for the touch panel signal layout should be minimized. Interface SOM R SOIMM slot to Touch Screen ontroller Touch screen controller to Touch panel connector Table : Touch panel trace properties Signal Name GPIO GPIO ISL IS RIVE[:00] SENSE[09:00] Trace Impedance Trace (mil) (Width : Spacing) Trace Mismatch Spacing to Other Signal Ω ± 0% : 0mil mil Ω ± 0% : 0mil mil Interface Signal Name Signal Type Topology Reference Plane SOM R SOIMM slot to Touch screen controller Touch screen controller to Touch panel connector GPIO GPIO ISL IS RIVE[:00] SENSE[09:00] Table 7: Touch panel signal type, routing topology and reference plane Single-ended Point-to-Point Ground/Power Single-ended Point-to-Point Ground/Power Interface SOM R SOIMM slot to Touch Screen ontroller Touch screen controller to Touch panel connector Signal Name GPIO GPIO ISL IS RIVE[:00] SENSE[09:00] Routing Layer Length ifference (mil) ccumulated Trace Length (L + L = LT) Top/ottom - " Top/ottom 00mil " Table 8: Touch panel layout guidelines

42 .. Touch Panel Reference Schematics Figure : Touch panel reference circuitry

43 .7 GPIO Interface The SOM-X80 module features a General Purpose Input and Output (GPIO) interface..7. GPIO Signal efinition The following table provides the definition of the GPIO signals that are implemented in the SOM R SOIMM slot. Signal Name Pin # I/O escription GPIO0 8 IO GPIO IO GPIO 70 IO GPIO 7 IO GPIO 7 IO GPIO 78 IO GPIO 7 IO GPIO7 8 IO GPIO9 80 IO Table 9: GPIO signal definition.7. GPIO Layout and Routing Recommendation Table 0: GPIO trace properties General Purpose GPIO SUS_GPIO0 0 IO General Purpose GPIO for Suspend Power omain SUS_GPIO 79 IO Signal Group Signal Name Trace Impedance ata GPIO[7:0] GPIO9 SUS_GPIO0 SUS_GPIO Trace (mil) (Width : Spacing) Spacing to Other Signal Ω : mil Ω : mil Signal Group Signal Name Signal Type Topology Reference Plane ata GPIO[7:0] GPIO9 SUS_GPIO0 SUS_GPIO Table : GPIO signal type, topology and layout guidelines ccumulated Trace Length Single-ended Point-to-Point Ground/Power " Single-ended Point-to-Point Ground/Power "

44 .8 I² Interface The SOM-X80 module features an I² interface that can support up to three I² devices..8. I² Signal efinition The following table provides the definition of the I² signals that are implemented in the SOM R SOIMM slot. Signal Name Pin # I/O escription I0S 8 IO I² serial data I0SL 0 IO I² serial clock IS IO I² serial data ISL IO I² serial clock IS IO I² serial data ISL 8 IO I² serial clock Table : I² signal definition.8. I² Layout and Routing Recommendation Signal Group Signal Name Trace Impedance Table : I² trace properties Trace (mil) (Width : Spacing) Spacing to Other Signal ata I[:0]S Ω : mil lock I[:0]SL Ω : mil Signal Group Signal Name Signal Type Topology Reference Plane Table : I² signal type, topology and layout guidelines ccumulated Trace Length ata I[:0]S Single-ended aisy chain Ground/Power <" lock I[:0]SL Single-ended aisy chain Ground/Power <" 7

45 .9 SPI Interface The SOM-X80 module features two SPI interfaces. Each SPI interface can support one master and one slave..9. SPI Signal efinition The following table provides the definition of the SPI signals that are implemented in the SOM R SOIMM slot. Signal Name Pin # I/O escription SPI0MISO 9 I Master Input 0, Slave Output 0 SPI0MOSI O Master Output 0, Slave Input 0 SPI0LK O Serial lock 0 SPI0SS0- O Slave Select 0 SPIMOSI O Master Output, Slave Input SPIMISO I Master Input, Slave Output SPILK 0 O Serial lock SPISS0- O Slave Select Table : SPI signal definition.9. SPI Layout and Routing Recommendation Signal Group Signal Name Trace Impedance ata Table : SPI trace properties SPI[:0]MISO SPI[:0]MOSI Trace (mil) (Width : Spacing) Spacing to Other Signal Ω : mil lock SPI[:0]LK Ω : 0 mil Signal Group Signal Name Signal Type Topology Reference Plane ata SPI[:0]MISO SPI[:0]MOSI SPI[:0]SS0- SPI[:0]SS0- Table 7: SPI signal type, topology and layout guidelines ccumulated Trace Length Single-ended aisy chain Ground/Power <0" lock SPI[:0]LK Single-ended Rs = Ω Ground/Power <0" 8

46 .0 udio Interface The SOM-X80 module features an audio interface for audio connectors such as two Line-in, headphone, mono speaker out, right and left channel speakers, and microphone..0. udio Signal efinition The following table provides the definition of the audio signals that are implemented in the SOM R SOIMM slot. Signal Name Pin # I/O escription HPOUTR O Headphone right channel output HPOUTL 7 O Headphone left channel output OUT O udio mono output LINPUT 7 I LINPUT I LINPUT I RINPUT I RINPUT I Table 8: udio signal definition.0. udio Layout and Routing Recommendations Route the analog and digital trace signals as far as possible from each other to prevent noise. Route the clock trace away from any analog input and voltage reference pins. Isolate the codec or put away from any major current path or ground bounce. Fill with copper the regions between the analog traces and attached it to the analog ground. Fill with copper the regions between the digital traces and attached it to the digital ground. Keep trace lengths as short as possible. Left channel single-ended Mic input/left channel negative differential Mic input Left channel line input/left channel positive differential Mic input Left channel line input/left channel positive differential Mic input/jack detect input pin Right channel single-ended Mic input/right channel negative differential Mic input Right channel line input/right channel positive differential Mic input SPK_OUT_R+ O Right speaker positive output SPK_OUT_R- O Right speaker negative output SPK_OUT_L+ 9 O Left speaker positive output SPK_OUT_L- 7 O Left speaker negative output Signal Name HPOUTR HPOUTL Table 9: udio trace properties Trace Impedance Trace (mil) (Width : Spacing) Spacing to Other Signal Ω ± 0% 8 : mil OUT Ω ± 0% 8 : mil LINPUT[:] RINPUT[:] SPK_OUT_R[+/-] SPK_OUT_L[+/-] Ω ± 0% 8 : mil Ω ± 0% 8 : mil 9

47 Signal Name Signal Type Topology Reference Plane HPOUTR HPOUTL Table 0: udio signal type, topology and layout guidelines.0. udio Interface Reference Schematics ccumulated Trace Length Single-ended Point-to-Point Ground <0" OUT Single-ended Point-to-Point Ground <0" LINPUT[:] RINPUT[:] SPK_OUT_R[+/-] SPK_OUT_L[+/-] Single-ended Point-to-Point Ground <0" Single-ended Point-to-Point Ground <0" Figure : Line-in & reference circuitry Figure : Headphone reference circuitry Figure : Mono speaker out reference circuitry 0

48 Figure : Right channel speaker reference circuitry Figure : Left channel speaker reference circuitry Figure 7: Onboard microphone reference circuitry

49 . S Interface The SOM-X80 module features an S interface for S storage... S Signal efinition The following table provides the definition of the S signals that are implemented in the SOM R SOIMM slot. Signal Name Pin # I/O escription S0T0 IO ata signal 0, used for S interface S0T IO ata signal, used for S interface S0T 9 IO ata signal, used for S interface S0T IO ata signal, used for S interface S0M 7 IO ommand signal, add external pull-up resistor S0LK 9 O S0 bus clock S0 I S0 ommand S0PWRSW O S0 Power switch S0WP I S0 write protect Table : S signal definition SOM R SOIMM Slot ES S0T[:0] L L ES SOM-X80 Edge finger S0 S0LK S0PWRSW L L L V_S0 L L L S slot R S0M L L S0WP R Figure 8: S routing topology.. S Layout and Routing Recommendations Signal traces should be above a solid and continuous ground plane along the path from SOM R SOIMM slot to S slot. S0M trace signal must have pull-up resistor of.7kω. S0WP trace signal must have pull-down resistor of KΩ to the ground. The ES protection of trace signal S0PWRSW must be placed near the S slot.

50 Signal Group Signal Name Trace Impedance Table : S trace properties Trace (mil) (Width : Spacing) Spacing to Other Signal ata S0T[:0] Ω ± % : mil ontrol S0M S0 S0WP S0PWRSW Ω ± % : mil lock S0LK Ω ± % : mil Signal Group Signal Name Signal Type Topology Reference Plane Table : S signal type, topology and layout guidelines.. S Interface Reference Schematics ccumulated Trace Length (L + L = LT) ata S0T[:0] Single-ended Point-to-Point Ground/Power <8" ontrol S0M S0 S0WP S0PWRSW Single-ended Point-to-Point Ground/Power <8" lock S0LK Single-ended Point-to-Point Ground/Power <8" Figure 9: S reference circuitry

51 ppendix. SOM arrier oard Reference Schematics The SOM is the evaluation carrier board for SOM-X80 module. The schematics of the SOM carrier board can be used as an example of how to design a carrier board that provides optimal performance when used with the SOM-X80 module. The reference designs are only for referencing and not to be copied.

52 lock iagram Optional 7" L 0*00 VO USH0 US H/ ap-type TouchPanel GPIO Header pin I GPIO SOM OR WM880 Processor M R 8G emm K SPI Flash VT0 odec USH USH SPK US Host onnector US Host onnector Speaker onnector WonderMedia Technologies, Inc. Title lock iagram Size ocument Number Rev ustom SOM ate: Wednesday, ugust 08, 08 Sheet o f

53 SOM OR IN V,00m MP0N V VIN(V) WM880 Processor M R 8G emm K SPI Flash VT0 odec V EUP70OIR VGH(8V) VGL(-V) VOM(.9V) L+TP Module SY700 voltage can be adjusted VLE(9.V) SY80 Power Switch VUS(V) US Host WonderMedia Technologies, Inc. Title Size ocument Number Rev ustom SOM over Page ate: Wednesday, ugust 08, 08 Sheet o f

54 WM880 SOM IO Test oard VTS8 Power Tree: ONN V, MP0N VIN_RT TITLE over Page PGE 0 VIN_RT EMP87 V_WG HT8F00 lock iagram GPIO/I List Table R SOIMM GF US I/F 0 PM8K-TRL VIN VIN_EN 0. 80m EMP87 V_WiFI PWRENV PWRENV PWRENV SY80 SY80 GN0 V_HMI US Host x US Host x HMI ONN SIO WiFi RS- Output onn HMI Ethernet Micro S SIO WiFi ebug Port & IR SPI & I GPIO_PWM SPK & MI m PWRENV GPIO GN0 V_SPK GN0 L_V NS8 L IS Voltage L backlight L PWR L I/F P Touch - GSL80 GM70_Video_ecoder IR amera m EMP87 VM_PMU GM70 -IN & WT N 0 00m SY808 V_URT PWRENV SP N N Version History RT attery. R SOIMM GF V Micro S ebug ONN SPI ONN GPIO ONN GSL80 Illustration: LO Switch to Source Load Title over Page Size ocument Number Rev SOM ustom ate: Wednesday, ugust 08, 08 Sheet o f

55 lock iagram PTER V/ Micro S 7" 0*00 GSL80 P Mul-Touch to FR9888 V/. Reserved Header Reserved Header Reserved Header Reserved Header Watchog HT8F00 utton VIN SPI I PWM GPIO GPIO KEY SIO0 RG WM880 SOM I SIO USH0 USH USH WiFi P0 US Host/ evice US Host US Host US ONN US ONN US ONN IR Receive ebug Port IR URT0 udio VIN OM OM OM OM HMI PHY HMI ONN MI in Line in Speaker out Earphone out amera ONN Video ecoder GM70 VS RS REEIVER OM/ RS REEIVER OM/ TRNSFORMER RJ Title lock iagram Size ocument Number Rev SOM ustom ate: Wednesday, ugust 08, 08 Sheet o f

56 GPIO/I List Table [GPIO/EXTINT SSIGNMEMT] GPIO# I/O GPIO0 I GPIO O GPIO O GPIO O GPIO I GPIO I GPIO7 O GPIO8 O GPIO9 O GPIO GPIO Function WiFi Host Wake T WiFi REG ON ontrol L Power TP Reset TP Interrupt WiFi Wake Host T RST N Mute NS8 Speaker amera PN System normal boot GM70 PN [WKEUP(INT) SSIGNMEMT] WKEUP# I/O Function WKEUP0 WKEUP WKEUP WKEUP [SUSPEN GPIO SSIGNMEMT] SUSGPIO# I/O Function SUSGPIO0 PU_TIVE SUSGPIO Low battery lert(reserved) SUSGPIO SUSGPIO USSW0 USO# PIN Shared N/ PIN Shared [S ard Power ontrol] NME I/O Function S0PWRSW SPWRSW SPWRSW SPWRSW PIN Shared I us SSIGNMEMT I# Function evice ddress Module Max.Freq(KHz) I0 I I I (Suspend) GM70 amera TP-GSL80 Note: Non-EITE GPIO LIST (Refer WM880 atasheet for detail) Title GPIO/I List Table Size ocument Number Rev SOM ustom ate: Wednesday, ugust 08, 08 Sheet o f

57 R SOIMM Golden finger TP TP TestPoint_mm TestPoint_mm SPWRSW SWP NET_RX- NET_RX+ SPI0MISO SPI0MOSI SPI0LK SPI0SS0- S0LK S0T S0WP S0T0 S0M S0T S0T S0PWRSW S0 0 M0_LINK 0 M0_SPEE,7 PWMOUT0, PWMOUT USTT0 USI0 USSW0 NET_TX- NET_TX+ 09 nhmihp 09 nhmie 09 nhmis 09 nhmisl USTT0 USI0 USSW0 S0LK S0T S0WP S0T0 S0M S0T S0T S0PWRSW S0 M0_LINK M0_SPEE PWMOUT0 PWMOUT NET_RX- NET_RX+ nush+ nush- NET_TX- NET_TX+ nhmihp nhmie nhmis nhmisl J VREFQ GN GN QM0 GN 7 9 GN GN 9 QS# QS GN GN 7 GN 7 QS# 9 QS GN GN 9 GN QM 7 GN GN GN GN 8 0 QS0# QS0 GN 8 7 GN 0 GN 8 QM 0 RESET# GN GN GN QM GN 8 0 GN GN 0 QS# QS GN GN 7 nush+ nush- nush0+ nush0- URT_TS URT_RTS URT_RX URT_TX URT_TS URT_RTS URT_RX URT_TX URT_RTS URT_RX URT_TX URT_TS URT_RTS URT_TS URT_TX URT_RX nush+ 7 nush- 7 nush+ 7 nush- 7 nush0+ 7 nush0-7 URT_TS 8 URT_RTS 8 URT_RX 8 URT_TX 8 URT_TS 8 URT_RTS 8 URT_RX 8 URT_TX 8 URT_RTS 8 URT_RX 8 URT_TX 8 URT_TS 8 URT_RTS 8 URT_TS 8 URT_TX 8 URT_RX 8 VHSYN 8 VVSYN 8 VEN 8 VLK 8 VOUT0 8 VOUT8 8 VOUT 8 VOUT0 8 VOUT 8 VOUT 8 U7 07Z8 U8 07Z8 VSUS V-T V V Input 0uF 8 0uF 8 uf 80 0uF VIN V TestPoint_mm V7 TestPoint_mm uf 8 0.uF V TestPoint_mm 8 uf uf 8 0.uF 0.uF , 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, VIN0 VIN VIN VIN VIN VLK VIN MOUT VIN VIN7 VVSYN VHSYN GPIO GPIO HPOUTR OUT HPOUTL MIIS nhmi+ nhmi- nhmi0+ nhmi0- SPK_OUT_L- SPK_OUT_L+ SPK_OUT_R- SPK_OUT_R+ nhmi+ nhmi- nhmilk+ nhmilk- WKEUP 7,8,09,,,,0 PWRENV WKEUP IRIN PWRENMEM PWRENV, SUS_GPIO GN, PWRTN- TestPoint_mm, RSMRST- PWMOUT PWMOUT PWREN_MIN LINPUT LINPUT LINPUT RINPUT RINPUT VLK MOUT VIN VIN7 VVSYN VHSYN SPILK SPISS0- SPIMISO GPIO GPIO0 GPIO GPIO GPIO GPIO GPIO GPIO9 GPIO7 SPK_OUT_R- SPK_OUT_R+ WKEUP PWRENV WKEUP IRIN PWRENMEM PWRENV SUS_GPIO PWRTN- RSMRST- PWMOUT PWMOUT PWREN_MIN SPK_OUT_L- SPK_OUT_L+ HPOUTR OUT HPOUTL LINPUT LINPUT LINPUT RINPUT RINPUT V-T VIN P THIKNESS.0mm KE0 KE 7 77 V V N V V 8 8 /# V V V7 V V9 V0 0 0 K0 K 0 0 K0# K# 0 07 V V /P 0 0 RS# V V WE# S0# 7 S# OT0 8 9 V V 0 OT S# N V7 V8 VREF 7 TEST 9 GN GN GN GN 7 QS# QM QS GN GN 8 9 GN 7 GN GF-R_SOIMM_0P GN 0 GN QS# QM QS 7 GN GN GN GN GN GN QS# QM QS GN GN GN GN GN GN QS7# QM7 QS7 9 GN GN GN GN S0 EVENT# S 00 0 VSP 0 0 S SL 0 VTT VTT VOUT SM SLK ST0 ST ST ST SPWRSW SWP I0S I0SL ISL IS IS ISL SUS_GPIO0 PWRG WKEUP0 SPIMOSI VSUS V VOUT 8 VOUT 8 VOUT 8 VOUT 8 VOUT9 8 VOUT7 8 VOUT 8 VOUT 8 VOUT 8 VOUT9 8 VOUT 8 VOUT8 8 VOUT7 8 VOUT0 8 VOUT 8 VOUT 8 VOUT 8 VOUT 8 URTRX URTTX URT0RX URT0TX SM SLK ST0 ST ST ST I0S,0 I0SL,0 ISL, IS, IS,9 ISL,9 SUS_GPIO0, PWRG WKEUP0, SPIMOSI SPILK SPISS0- SPIMISO GPIO, GPIO0,, GPIO, GPIO,7 GPIO,9 GPIO,9 GPIO, GPIO9, GPIO7, URT0 and from WM8880 I Signal need external pull high Title R SOIMM Golden Finger Size ocument Number Rev SOM ustom ate: Wednesday, ugust 08, 08 Sheet o f

58 US VIN 0uF urrent Limit:.0 Ilim()=800/Rset(ohm) 800/800= U SY80 IN EN OUT GN SET 0uF 7 0uF 8 0uF 9 0uF +E 00uF VUS0 +E 00uF V8 TestPoint_mm 0 000pF ES S080M,8,09,,,,0 PWRENV R K Rset R.8K_% o-lay J VUS0 USH- USH+ nush- nush+ nush- nush+ L M0E-900-P-T00 ES S080S USH- USH+ ES S080S M M nush- nush+ L M0E-900-P-T00 nush- nush+ USH- USH+ M J VUS0 USH- USH+ ES S080S ES S080S M USSW0 R8 VIN 0uF K Ilim()=800/Rset(ohm) 800/0000=0.8 U IN EN OUT SY80 GN SET Rset R7 0K_% US_VUS 0uF 000pF ES S080M US_VUS R 0K USTT0 USI0 USI0 HOST evice R 0K USI0 0 V VSUS nush0- nush0+ US_VUS USH0- USH0+ USI0 nush0- nush0+ L M0E-900-P-T00 ES7 S080S USH0- USH0+ ES8 S080S 0uF V9 TestPoint_mm R9 0K 0/X 0 R R ES9 S080M VUS - + I GN G GN G GN G GN G GN J7 TH-00-08L US PORT 0 onfiguration Table Title US I/F Size ocument Number Rev SOM ustom ate: Wednesday, ugust 08, 08 Sheet 7 o f

59 V_URT URT URT_TX URT_RTS URT_RX URT_TS 0.uF + 0.uF uF - URT_TX URT_RTS 0 IN IN URT_RX URT_TS 9 ROUT ROUT V GN U SPEEY-L V+ 7 0.uF V- 8 0.uF OUT 7 OUT RIN 8 RIN OM_TX OM_RTS OM_RX OM_TS,7,09,,,,0 VIN 88 0uF PWRENV Vout=0.*(+R/R) 0.*(+K/00K)=.V U7 VIN VF SY808 LX GN EN R K or Higher L Z-0MES-RM R 00K R R R K_% R 00K_% 90 0pF 87 0uF.V V_URT 8 0uF V0 TestPoint_mm pF V_URT V_URT J8 HEER X URT_TX URT_RTS URT_RX URT_TS URT_TX URT_RTS URT_RX URT_TS URT_TX URT_RTS URT_RX URT_TS 0 0.uF + 0.uF uF - URT_TX URT_RTS 0 IN IN URT_RX URT_TS 9 ROUT ROUT V_URT V GN U SPEEY-L V_URT V+ 0.uF V- 0.uF OUT 7 OUT RIN 8 RIN OM_TX OM_RTS OM_RX OM_TS OM_RX OM_TX OM_TS OM_RTS OM_RX OM_TX OM_TS OM_RTS R0 R R R R R R R7 OM RX OM TX OM TS OM RTS OM RX OM TX OM TS OM RTS OM RX OM TX OM RTS OM TS ES0 S080M OM RX OM TX OM RTS OM TS ES S080M ES S080M ES S080M OM RX OM TX OM RTS OM TS OM RX OM TX OM RTS OM TS URT_TX URT_RTS URT_RX URT_TS 0.uF U SPEEY-L + 0.uF V+ 7 0.uF 8 - V- 0.uF 9 + OM_RX R8 0.uF OM_TX R9 OM_TS R0 - OM_RTS R URT_TX OM_TX URT_RTS 0 IN OUT 7 OM_RTS IN OUT URT_RX OM_RX URT_TS 9 ROUT RIN 8 OM_TS ROUT RIN GN OM RX OM TX OM TS OM RTS OM RX OM TX OM TS OM RTS ES0 S080M ES S080M OM RX OM TX OM RTS OM TS ES S080M ES S080M ES S080M ES7 S080M G G G G N J N J7 V ES8 S080M ES9 S080M G G N J8 V_URT V_URT J9 HEER X URT_TX URT_RTS URT_TX URT_RTS URT_RX 7 8 URT_RX URT_TS 9 0 URT_TS URT_TX URT_RTS URT_RX URT_TS 0.uF uF uF - URT_TX URT_RTS 0 IN IN URT_RX URT_TS 9 ROUT ROUT V_URT V GN U SPEEY-L V+ 0.uF V- 0.uF OUT 7 OUT RIN 8 RIN OM_TX OM_RTS OM_RX OM_TS OM_RX R OM_TX R OM_TS R OM_RTS R OM RX OM TX OM TS OM RTS OM RX OM TX OM TS OM RTS ES S080M ES S080M ES S080M ES S080M OM RX OM TX OM RTS OM TS G G N J9 Title RS- Output onn Size ocument Number Rev SOM ustom ate: Wednesday, ugust 08, 08 Sheet 8 o f

60 HMI nhmilk- nhmilk+ nhmi0- nhmi0+ nhmi- nhmi+ nhmi- nhmi+ nhmi_ein nhmisl nhmis nhmihp nhmilk- nhmilk+ nhmi0- nhmi0+ nhmi- nhmi+ nhmi- nhmi+ nhmie,09 nhmisl,09 nhmis,09 nhmihp,09 For HMI Logo: Signal Name nhmi[:0]+/- HMI[:0]+/- nhmilk+/- HMILK+/- Length Mismatch (mils) In Pair Pair to Pair < < 00 Total Length (Width: Spacing) LT < " (:7:),7,8,,,,0 VIN uf For HMI Logo: PWRENV Q SM07PS-TRG R8 RV-0/X G K K S R 00K R7 K uf Q LMT90LTG V_HMI 7 uf V TestPoint_mm,09,09 nhmisl nhmis nhmisl nhmis V R9 K V S R K S V G V G V_HMI Q LN700LTG For HMI Logo: SPN700 change to FV0N V Q LN700LTG K RS-H R0 K R 00 R K RS-H R 00 HMISL HMIS L M0E-900-P-T00 nhmi+ HMI+ nhmi- HMI- L M0E-900-P-T00 nhmi+ HMI+ nhmi- nhmilk+ L M0E-900-P-T00 HMI0+ HMI0- HMI_EIN HMILK- HMI- L7 M0E-900-P-T00 HMILK+ nhmilk- HMILK- losed to HMI connector ES omponent can not be costdown! HMI_EIN HMIS HMISL HMILK- HMILK+ HMI0- HMI0+ HMI- HMI+ HMI- HMI+ ES8 S080M S080S 0 9 G 7 S080S 0 9 ES S080M 7 ES9 S080M ES7 S080M HMIHP 9 0.uF HMIS HMISL HMI0+ HMI- HMI+ HMI- nhmi0+ nhmi0- HMILK+ HMI0- HMI+ V_HMI HMI Port G G G G J0 H9F-00 K ES0 S080M 8 0.uF G,09 nhmie R 0K R 00 HMI_EIN Notice: ES components place near HMI connector. V V o not change. R7 M G,09 nhmihp nhmihp S HMIHP o not change. Q LN700LTG R8 7K Title HMI Size ocument Number Rev SOM ustom ate: Wednesday, ugust 08, 08 Sheet 09 o f

61 Ethernet V TU0V/X 7 TU0V/X NET_RX+ NET_TX+ R8 0/X 0.uF 9 0 T For SOM-X80 R8 Need to Mount (080) T RX+ T TX+ TS8LF T- R- T R+ RX- NET_RX- NET_RX+ NET_TX- NET_TX+ TX- RX- T T+ 8 7 RX+ TX+ R9 R 7_% 7_% 0 000pF MT R0 7 R 7 NET_TX- NET_RX- TX- RX- TX+ TX- RX+ 7 8 M G J MRJN-TRS G M Y G 9 0 V R 0 R 0 ctive M0_LINK M0_SPEE Speed M0_LINK M0_SPEE Title Ethernet Size ocument Number Rev SOM ustom ate: Wednesday, ugust 08, 08 Sheet 0 o f

62 Micro S V S0PWRSW R 0.uF G S low RS Q SM07PS-TRG uf V_S0 0.uF Please near S ard V TestPoint_mm S0T S0T S0M ES S080M S0LK S0T0 S0T S0 S0T S0T S0M S0LK S0T0 S0T S0 ES ES7 ES8 ES9 ES0 ES ES S080S S080S S080S S080S S080S S080S S080S J MR0-0 T /T M V LK 7 VSS 8 T0 9 T G R ETET G G G G G G G V_S0 S0M R.7K S0WP R7 K Title Micro S Size ocument Number Rev SOM ustom ate: Wednesday, ugust 08, 08 Sheet o f

63 VIN uf VOUT =[ (R + R)/ R ].07 [(7.K+.K)/.K]*.07=.V R7 0 R7 0/X U7 VIN VOUT GN EN F SGM09-JYNG/T R8 R9.K_% 7.K_% V_WIFI uf 8 K Wi-Fi RS-H 9 RS-H WL_WKE_HOST K WKE_HOST V PWRENV,7,8,09,,,0 V_WIFI V TestPoint_mm V_WIFI, WKEUP0 0 K R 00K/X RS-H T_WKE_HOST R0 00K Place close, route short. 7 8 pf pf OS GN MHz MHZ : +/-0 PPM 0PF ESR <0 OHM GN R 00 XTLM_O XTLM_I R 0/X uf uf 9.7uF XTLM_I XTLM_O T_WKE_HOST HOST_WKE_T WIFI_T_NT R 0 0pF/X TP78 TestPoint_mm J SM800M pF/X P8/P0 : OS MHz /.9pF R 00 ESP8089: OS 0MHz / pf R 0 mpak * Module V_WIFI R7 0K 7 0pF V_WIFI WL_REG_ON WL_WKE_HOST S_ S_ S_M S_LK S_0 S_ 8.7uF.uF : R 0.0 OHM I U8 P8/P0 WL_REG_ON XTL_OUT WL_HOST_WKE SIO_T_ SIO_T_ SIO_T_M SIO_T_LK SIO_T_0 SIO_T_ GN VIN_LO_OUT VIO L8 Z-0MES-R7N VIN_LO LPO XTL_IN 0 9 PM_OUT VT PM_LK T_VIO/N_HOST_WKE 8 7 PM_IN T_HOST_WKE 7 8 PM_SYN T_WKE 9 V_TXO N_WKE 0 TXO_IN FX_RX GN GN GPS_RF WL_T_NT GN GN N_VSWPIO N_VSWP_OUT N_VSWP_IN 7 URT_TS_N URT_RX URT_TX URT_RTS_N TX TX N_REG_PU 8 N_I_SL GN N_I_S T_RST_N P8/P0 : 0pF ESP8089:.pF RTS TX RX TS R.7K GPIO9, o-lay esign 0.7uF 0pF K78HZ R9 0/X External K input OS E/ V GN.78KHz V_WIFI 0.uF R7 0 OUT K78HZ PWMOUT,,, GPIO0, GPIO, GPIO ST ST SM SLK ST0 ST URTRX URTTX HOST_WKE_T WKE_HOST P8/P0 : 0ohm ESP8089: 00ohm R0 0 R 0 R 0 R 0 R 0 R 0 R 0 R7 0 R8 0 R9 0 R70 0 WL_REG_ON S_ S_ S_M S_LK S_0 S_ TS RX TX RTS ESP8089(O):.GHz WiFi - default P8 :.GHz WiFi P0 : -in- combo.ghz/ghz WiFi+T+FM Title SIO WiFi Size ocument Number Rev SOM ustom ate: Wednesday, ugust 08, 08 Sheet o f

64 ebug Port and IR IRIN URT0TX URT0RX IRIN V J S-0G-K-F URT0RX URT0TX G J L V 0.uF Use the same direction connect wire G VSUS VSUS o-lay With IR. R7 0K/X IRIN uf IR FM-908LM-N V GN VOUT IRIN VSUS J HEER_X Title ebug Port and IR Size ocument Number Rev SOM ate: Wednesday, ugust 08, 08 Sheet o f

65 V J7 HEER X SPILK SPIMOSI SPIMISO SPISS0- SPI0LK SPI0MOSI SPI0MISO SPI0SS0- V SPI0LK SPI0MOSI SPI0MISO SPI0SS0- SPILK SPIMOSI SPIMISO SPISS0- V R7.K R7.K I0SL I0S V V V J8 HEER_X I0SL I0S,0 I0SL ISL IS I0S,0, ISL ISL 7 8 IS IS,,9 ISL 9 0 IS,9 ISL IS R7.K V R7.K R77.K R78.K ISL IS Title SPI & I Size ocument Number Rev SOM ate: Wednesday, ugust 08, 08 Sheet o f

66 ,7,8,09,,,0 PWREN_MIN PWRENV PWRENMEM PWRENV V PWREN_MIN PWRENV PWRENMEM PWRENV J9 HEER_X PWRG RSMRST- PWRTN- PWRG RSMRST-, PWRTN-,, SUS_GPIO0, SUS_GPIO,, GPIO0, GPIO, GPIO,9 GPIO SUS_GPIO0 SUS_GPIO GPIO0 GPIO GPIO GPIO V J0 HEER X GPIO GPIO GPIO GPIO7 GPIO9 GPIO,9 GPIO, GPIO,7 GPIO7, GPIO9,,7, PWMOUT0 PWMOUT PWMOUT PWMOUT V PWMOUT0 PWMOUT PWMOUT PWMOUT V J HEER X 7 8 WKEUP0 WKEUP 9 0 WKEUP WKEUP0, WKEUP WKEUP V V R8.K R8.K LE KPH-08Q- LE KPH-08Q- PWMOUT PWMOUT V V V R89.K R90.K R9.K LE KPH-08Q- LE KPH-08Q- LE KPH-08Q- WKEUP0 WKEUP WKEUP Title GPIO & PWM Size ocument Number Rev SOM ustom ate: Wednesday, ugust 08, 08 Sheet o f

67 R98 0 R97 0 R0 0 R0 0 F LMX0SN 000pF/X F 70 LMX0SN 000pF/X F LMX0SN 7 000pF/X F 78 LMX0SN 000pF/X 000pF/X 7 000pF/X SPKR_P 7 000pF SPKR_N 9 000pF SPKL_P 7 000pF SPKL_N pF G G G G J L J S-0G-F J8 J7 S-0G-F L, GPIO7 OUT R0 OUT J S-0G-F K Mute Speaker 8 V R0 00K 0.0uF R99 V_SPK R00 8K K NN Mode R0 K Q7 LMT90LTG 7 0.uF 77 uf U0 INN N ypass TRL NS8 SPK_OUT_R+ SPK_OUT_R- SPK_OUT_L+ SPK_OUT_L- VO- V GN 7 8 VO+ V_SPK F SPK_N LMX0SN 7 000pF F SPK_P LMX0SN 7 000pF Short connect i on, and shielding with GN SPK_P SPK_N lose to mplifi er SPK_P SPK_N J S-0G-F G G J L R0 0/X J9 PJ-S7-S VIN Q8 SM07PS-TRG S V_SPK HPOUTL LINPUT HPOUTR HPOUTL LINPUT HPOUTR E + 00uF E + 00uF R09 0/X R uF R08 00K 8 0.uF G 8 0uF 8 uf 8 0.uF J0 HEER_X HPOUTL LINPUT HPOUTR 8 0pF R0 0K 8 0pF R 0K ES S080M ES S080M ES S080M R K,7,8,09,,,0 PWRENV R K Q9 LMT90LTG J HEER_X LIN RIN R 0 F7 LMX0SN F8 LMX0SN ES S080M ES S080M 87 00pF 88 00pF LINPUT RINPUT LINPUT RINPUT Onboard MI MI PMO-0PN-8KQ MI 90 00pF 89.7uF R.K R 0K/X LINPUT MIIS 9.7uF J HEER_X LIN RIN R7 0 F9 LMX0SN F0 LMX0SN ES S080M ES S080M 9 00pF 9 00pF LINPUT RINPUT LINPUT RINPUT G G J L MI Title SPK & MI Size ocument Number Rev SOM ustom ate: Wednesday, ugust 08, 08 Sheet o f

68 L POWER V Replacement: U R98 9 uf/v/xr P00 9.uF P00 R9 00K VGH 97 uf/v/xr P00.V EUP70 00K_% VGL.V MT70 0K_%.V STI0 0K_% uf/v/xr P00 LTSLTG R8 K 9.uF P00 V TestPoint_mm K MMSZ8-TP V TestPoint_mm 98 LTSLTG 99.uF P00 R0 00_% RES00 R 0K RES00 00 uf/v/xr P00 MMVZGP K, GPIO VIN V 0 0uF R0 R K/X K R 0K Q0 SM07PS-TRG S 0 0.uF G R7 K Q LMT90LTG R8 L_V 0K 0 0uF V TestPoint_mm L9 Z-0MES-R7N R 00K 09 uf U IN EN GN SW F EUP70OIR R K_%/X RES00 Vout=.*(+R/R).*(+00/)=9.8V SSM88SGP R R K R 00K_% RES00 08 R K_% RES00 0.0uF/X P00 R 0K/X RES00 9.V V 0 0uF/V/XR P080 V TestPoint_mm 0 uf/v/xr P00 V.897V R9 = 0 ohms for LPT Panel R.K RES00 0 uf/v/xr P00 R 0 RES00 R9 80_% RES00 VOM V TestPoint_mm 07.uF P00 Replacement: L_LX L_F L_V U SW IN GN F EN L_EN EUP8OIR/X o-lay with U 0.V 0.V 0.V 0.V U up00mt XR SY700 EUP8 R87/R m 9.8m 9m 9m, PWMOUT0 L_V 0uF LE acklight river 0.uF R 0 RES00 L_EN R8 00K L0 Z-0MES-R7N L_LX U7 LX IN GN OVP EN F SY700 Vfb = 0.V L_F R. RES00 R7. RES00 9.V/0m PS SSM88SGP K V 0 0uF/V/XR P080 0.uF TestPoint_mm LM_LE 8 J HEER_X_.MM/X LM_LEK 8 V TestPoint_mm 0.0V MT78. 9.m Title L PWR Size ocument Number Rev SOM ustom ate: Wednesday, ugust 08, 08 Sheet 7 o f