15V Stereo Class-D Audio Power Amplifier. Description. Tracking Code Date Code

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1 15V Stereo Class-D Audio Power Amplifier Features Operate from 8~15V supply voltage Class-D power 15W/ch into 8Ω from 15V 10% THD+N for stereo 12W/ch into 6Ω from 12V 10% THD+N for stereo 29W/ch into 4Ω from 15V 10% THD+N for mono Output integrated noise 120uVrms from 12V GAIN=20dB Efficiency 89% 8Ω from 12V GAIN=20dB S/N ratio 97dB 8Ω from 12V GAIN=20dB Crosstalk 92dB 8Ω from 12V GAIN=20dB PSRR 68dB 8Ω from 12V GAIN=20dB Support single-ended or differential analog input Anti-pop design Over-temperature protection Over-current protection Clock output for synchronization with multiple Class-D devices Two volume control modes 31 step DC volume control 4 selectable, fixed gain setting 48-pin E-LQFP (7x7mm) package Applications TV audio Boom-Box Powered speaker Description The is a high efficiency stereo Class-D audio amplifier. Operating with 8~15V supply, it can deliver 12W/CH output power into 8 loudspeaker within 1% THD+N. The has two volume control modes by setting MODE0 pin. While MODE0 pin is set logic high, is in DC volume control mode with 31-step volume gain, adjusted by the DC voltage applied on GAIN0 pin. Otherwise, is the 4-step volume gain mode, selected by setting GAIN0 and GAIN1 pins. The two volume adjustment modes are designed to fit the different volume control requirements in various applications. The packaged as E-LQFP 48L (7x7mm) is a stereo audio amplifier with high efficiency and low thermal resistance which leads to no external heat sink requirement under 10W/ch output power. Ordering Information Product Number Package Comments -LEG 7x7 48L E-LQFP Pb-free Marking Information Line 1:LOGO Line 2:Product No Line 3:Tracking Code Line 4:Date Code Tracking Code Date Code Revision: 1.4 1/23

2 Pin Assignments RA RA RB RB AVCC SDN AGND AVDD MUTE LA LA LB LB ERR FAULT MODE1 SY M_S Pin Description PIN NAME TYP DESCRIPTION 1 MODE0 I Mode0 control terminal 2 RINN I Negative audio input for right channel (Biased at ½ AVDD) 3 RINP I Positive audio input for right channel (Biased at ½ AVDD) 4 VCM O Reference for internal amplifiers (Normally equal to ½ AVDD) 5 6 LINP I Positive audio input for left channel (Biased at ½ AVDD) 7 LINN I Negative audio input for left channel (Biased at ½ AVDD) 8 AGND P Analog ground GAIN0 I Gain select bit 0 12 GAIN1 I Gain select bit 1 13 M_S I Master/Slave select (HIGH=master mode; LOW=slave mode) 14 SY I/O Clock input/output for multiple chip synchronization Revision: 1.4 2/23

3 PIN NAME TYP DESCRIPTION MODE1 I Stereo/Mono switching function 17 FAULT O Over-current fault report signal (Active high) 18 ERR O Error report signal ( Active high) LB O Half-bridge output B for left channel 21 LB O Half-bridge output B for left channel LA O Half-bridge output A for left channel 24 LA O Half-bridge output A for left channel PVCCL P Power supply for left channel H-bridge 27 PVCCL P Power supply for left channel H-bridge PGNDL P Power ground for left channel H-bridge 30 PGNDL P Power ground for left channel H-bridge 31 PGNDR P Power ground for right channel H-bridge 32 PGNDR P Power ground for right channel H-bridge PVCCR P Power supply for right channel H-bridge 35 PVCCR P Power supply for right channel H-bridge RA O Half-bridge output A for right channel 38 RA O Half-bridge output A for right channel RB O Half-bridge output B for right channel 41 RB O Half-bridge output B for right channel AVCC P High voltage analog power supply 44 SDN I Shutdown signal (Active low) 45 AGND P Analog ground 46 AVDD O Regulated output for use by internal cells 47 MUTE I Mute signal (Active high) 48 Thermal Pad - Must be soldered to PCB s ground plane Revision: 1.4 3/23

4 Functional Block Diagram AVCC Regulator AVDD PVCCR RINP RINN Gain Class D Modulator Level Shifter Output stage RA RB SDN MUTE FAULT ERR GAIN0 GAIN1 M_S SY Control Triangular Wave Generator Thermal Protection Over Current Protection PGNDR MODE0 MODE1 PVCCL LINP LINN Gain Class D Modulator Level Shifter Output stage LA LB VCM PGNDL AGND Available Package Package Type Device No. θ ja ( /W) Ψ jt ( /W) θ jc ( /W) Exposed Thermal Pad 7x7 48L E-LQFP Yes (Note 1) Note1: The thermal pad is at the bottom of package. To optimize the performance of thermal dissipation, solder the thermal pad to PCB s ground plane is suggested. Absolute Maximum Ratings SYMBOL PARAMETER MIN MAX UNIT AVCC, PVCC High voltage analog power supply V Vi Input Voltage SDN -0.3 AVCC+0.3 V Others -0.3 AVDD+0.3 V T stg Storage temperature o C T a Ambient operating temperature 0 70 o C Recommended Operating Conditions SYMBOL PARAMETER MIN TYP MAX UNIT AVCC, PVCC High voltage analog power supply V f OSC Oscillator frequency KHz T a Ambient Operating Temperature 0 70 o C Revision: 1.4 4/23

5 DC Characteristics AVCC=PVCC=12V, T A =25 C (unless otherwise noted) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT AVDD Regulated output V VCM Reference for internal amplifier 0.45*AVDD 0.5*AVDD 0.55*AVDD V V IH High-level input voltage 2 V V IL Low-level input voltage 0.8 V V OH High-level output voltage I OH =1mA AVDD-0.6 V V OL Low-level output voltage I OL =1mA 0.4 V ICC Quiescent current (Class-D mode) SDN=2V, MUTE=0V, No load 25 ma Quiescent current (Mute) SDN=2V, MUTE=2V, No load 10 ma Quiescent current (Shutdown) SDN=0.8V, No load 1 10 ua R DS (ON) Drain-source on-state resistance High side, I O =0.5A 0.30 Low side, I O =0.5A 0.28 V OS Class-D output offset voltage INP and INN connected together, 60 mv Gain=36dB Gain Class-D Gain MODE0=L, GAIN1=L, GAIN0=L db MODE0=L, GAIN1=L, GAIN0=H db MODE0=L, GAIN1=H, GAIN0=L db MODE0=L, GAIN1=H, GAIN0=H db Gain matching Between channel 2 % I OC Over current detection 3.3 A Thermal trip point 150 Thermal hysteresis 30 o C o C t ON Turn-on time C (VCM) =1uF, SDN=2V 500 ms Revision: 1.4 5/23

6 AVCC=PVCC=15V, T A =25 C (unless otherwise noted) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT AVDD Regulated output V VCM Reference for internal amplifier 0.45*AVDD 0.5*AVDD 0.55*AVDD V V IH High-level input voltage 2 V V IL Low-level input voltage 0.8 V V OH High-level output voltage I OH =1mA AVDD-0.6 V V OL Low-level output voltage I OL =1mA 0.4 V ICC Quiescent current (Class-D mode) SDN=2V, MUTE=0V, No load 33 ma Quiescent current (Mute) SDN=2V, MUTE=2V, No load 12 ma Quiescent current (Shutdown) SDN=0.8V, No load 1 10 ua R DS (ON) Drain-source on-state resistance High side, I O =0.5A 0.29 Low side, I O =0.5A 0.27 V OS Class-D output offset voltage INP and INN connected together, 60 mv Gain=36dB Gain Class-D Gain MODE0=L, GAIN1=L, GAIN0=L db MODE0=L, GAIN1=L, GAIN0=H db MODE0=L, GAIN1=H, GAIN0=L db MODE0=L, GAIN1=H, GAIN0=H db Gain matching Between channel 2 % I OC Over current detection 3.7 A Thermal trip point 150 Thermal hysteresis 30 o C o C t ON Turn-on time C (VCM) =1uF, SDN=2V 500 ms Revision: 1.4 6/23

7 AC Characteristics for Class-D Output AVCC=PVCC=12V, Load=8 Gain=20dB, T A =25 C (unless otherwise noted) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT P O RMS output power THD+N=10%, R L =8 Stereo 9.5 W THD+N=1%, R L =8 Stereo 7.6 W THD+N=10%, R L =6 Stereo 12.0 W THD+N=1%, R L =6 Stereo 9.7 W THD+N=10%, R L =4 Mono) 18.7 W THD+N=1%, R L =4 Mono) 14.9 W THD+N Total harmonic distortion + noise R L =8 Stereo Half power (5W) 0.07 % R L =6 Stereo, Half power (6W) 0.07 % R L =4 Mono, Output power (9.5W) 0.07 % Vn Output integrated noise 20Hz-20KHz, A-weighted, 120 uv Crosstalk Po=1W Gain=20dB -92 db PSRR Power supply reject ratio Gain=20dB, 200mV, 1KHz -68 db SNR Signal-to-noise ratio Maximum output at THD+N <1%, 97 db DR Dynamic range THD+N performance at -60dBFS, 103 db Efficiency 2 x Po (THD+N=10%) 90 % Po (THD+N=10%), R L =4 Mono) 89 % AVCC=PVCC=15V, Load=8 Gain=20dB T A =25 C (unless otherwise noted) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT P O RMS output power THD+N=10%,R L =8 Stereo 14.8 W THD+N=1%,R L =8 Stereo 11.9 W THD+N=10%, R L =6 Stereo 18.9 W THD+N=1%, R L =6 Stereo 15.2 W THD+N=10%, R L =4 Mono) 28.9 W THD+N=1%, R L =4 Mono) 23.4 W THD+N Total harmonic distortion + noise R L =8 Stereo Half power (7.5W) 0.07 % R L =6 Stereo, Half power (9W) 0.07 R L =4 Mono, Output power (14W) 0.07 % Vn Output integrated noise 20Hz-20KHz, A-weighted, 125 uv Crosstalk P O =1W, Gain=20dB -92 db PSRR Power supply reject ratio Gain=20dB, 200mV, 1KHz -65 db SNR Signal-to-noise ratio Maximum output at THD+N <1%, 100 db DR Dynamic range THD+N performance at -60dBFS, 104 db Efficiency 2 x Po (THD+N=10%) 89 % Po (THD+N=10%), R L =4 Mono 89 % Revision: 1.4 7/23

8 TABLE OF SPEAKER GRAPHS Item Condition Figure THD+N (Total harmonic distortion + noise) vs Frequency 1,2 THD+N (Total harmonic distortion + noise) vs Output Power 3,4 Close loop response vs Frequency 5,6 Efficiency vs power 7 Crosstalk vs Frequency 8,9 Revision: 1.4 8/23

9 Figure 1 Figure 2 Revision: 1.4 9/23

10 Figure 3 Figure 4 Revision: /23

11 Figure 5 Figure 6 Revision: /23

12 Figure 7 Revision: /23

13 Figure 8 Figure 9 Revision: /23

14 Operation Descriptions Analog Audio input To use with a differential source, connect the positive lead of the audio source to INP input and connect the negative lead of the audio source to the INN input. To use with a single-ended source, AC ground the INP or INN input through a capacitor which is equal to the input capacitor on INN or INP input and apply the audio source to either input. Volume control has built-in DC volume control and 4-step volume gain control, selected by MODE0 pin. While MODE0 pin is high, is in DC volume control mode. Otherwise, is in 4-step volume gain control mode. More detailed descriptions of each volume control mode are following. (i) 4-step volume gain control When MODE0 is low, the volume gain is set by GAIN0 and GAIN1. By varying input resistance in, the various volume gains are achieved. The respective volume gain and input resistance are listed in Table 1. But, there is 20% variation in input resistance from 20% process variation in actual resistance of the input resistors. Table 1. Volume gain and input impedance GAIN1 GAIN0 Volume Gain (db) Class-D Input Resistance, R in (k ) H H H L L H L L (ii) DC volume control When MODE0 is high, the volume gain is set by DC voltage on GAIN0. The input range applied on GAIN0 is from AGND to AVDD. To avoid volume gain oscillation from one to another, the hysteresis voltage between one volume gain to another is designed in. For example, the volume gain changes from -15dB to -13dB when DC voltage applied on G0 increases to 17.4% of AVDD. And the volume gain drops from -13dB to -15dB when DC voltage applied on G0 decreases to 15.8% of AVDD. More volume gain setting and its corresponding DC voltage applied on G0, including volume up and down, are listed in Table 2. Revision: /23

15 Table 2. DC voltage on Gain0 vs. corresponding volume gain Level Volume up Volume down Volume gain (db) (% of AVDD on Gain0) (% of AVDD on Gain0) Class-D 30 >66.9 > Revision: /23

16 Master/Slave Mode and SY The M_S and SY pins can be used to synchronize the frequency of the Class-D output switching to avoid any beat frequencies that occurs in the audio band when two or more Class-D amplifiers in the same system are switching at slightly different frequencies. When M_S pin is high, the output switching frequency is determined by the internal sync frequency. The SY pin becomes an output in this mode. When M_S pin is low, the output switching frequency is determined by the incoming square wave on the SY pin. The SY pin becomes an input in this mode. If connecting to an external GPIO, recommended frequencies are 200kHz to 300kHz for proper device operation. Stereo/Mono Switching Function The MODE1 pin can be use to switch stereo and mono mode. When mode1 pin is high, mono mode is selected. With the mono mode, parallel operation can be realized by connecting LA to RA and connecting LB to RB. For details of connections, see Mono; LC Filter (Page 19 and 20) in the Application Circuit Example. Self-protection circuits (Typical values are used below.) has built-in over-temperature, over-current protection. (i) If the internal junction temperature is higher than 150 o C, the outputs of loudspeaker drivers will be disabled and at low state. The temperature hysteresis for to return to normal operation is about 30 o C. The variation of protected temperature is around 10%. (ii) protects for short circuit fault conditions across the output to GND, VCC, or the other output. When over-current is detected on the output, the outputs are disable immediately. This is a latched fault and must be reset by cycling the voltage on the SDN pin or MUTE pin. MUTE The MUTE pin is an input for muting the device. A logic high on this pin will disable the outputs. has built-in volume fade-in/fade-out design for MUTE function. Shutdown Pulling SDN pin low will disable the outputs and cause the amplifier to enter a low-current state. has built-in volume fade-in/fade-out design for shutdown function. Revision: /23

17 Error reporting The ERR and FAULT outputs indicate the following conditions in the as shown in the following table: ERR FAULT Condition L L Normal operation L H Illegal state H L Over-temperature H H Over-current (latch) Revision: /23

18 Application information Input capacitors (C in ) The performance at low frequency (bass) is affected by the corner frequency (f c ) of the high-pass filter composed of input resistors (R in ) and input capacitors (C in ), determined in equation (a). And, the resistance of input resistors is different at different volume gain. The minimum R in is 12K shown in Table1. But there is 20% variation in input resistance from 20% process variation in actual resistance of the input resistors. Typically, a 1 F ceramic capacitor is suggested. f c 1 2 R C in in Hz a In differential audio signal application, the input capacitors (C in ), for DC decoupling, are not required. But, the input capacitors (C in ) are required if single-ended audio source is used. Internal bias voltage VCM The internal bias generator (VCM) provides the internal bias for the amplifier. The external input capacitors and this internal reference allow the inputs to be bias within the optimal common-mode range of the preamplifiers. During the startup state, the VCM capacitor is charged by device utilizing a smooth ramp up curve to minimize the pop noise. The overall sequence may take about 500ms before the output turn on. A value of 1uF is recommended for VCM capacitor. Decoupling capacitor (Cs) Because of the power loss on the trace, which is between the device and decoupling capacitor, the decoupling capacitor should be placed as close as to the device PVCCL (PVCCR) and PGNDL (PGNDR) to reduce any parasitic resistor or inductor between them. And, a low ESR ceramic capacitor, typically 1 F, is suggested for high frequency transients. For filtering audio band noise signal, a 220 F or greater capacitor (tantalum or electrolytic type) is suggested, but it is not required for most applications because of the high PSRR of this device. Internal Regulated Supply AVDD The AVDD pin is the output of an internal regulated supply. It requires two capacitors 0.1uF and 10uF (or 4.7uF) to be placed close to the pin. The regulated voltage is used for the amplifier, and should not be used to drive external circuitry. Revision: /23

19 Application Circuit Example RA RA RB RB SDN MUTE LA LA LB LB ERR FAULT MODE1 SY M_S Stereo; LC filter Revision: /23

20 Mono; LC Filter Revision: /23

21 Package Outline Drawing LQFP-48(E) (7x7 mm) Symbol Dimension in mm Exposed pad Min Max Dimension in mm A Min Max A D b E c D D E E e 0.50 BSC L Revision: /23

22 Revision History Revision Date Description Original Update measurement data 2. Schematic change 3. Modified package outline drawing 1. Changing output component 2. Updating performance 3. Cancelling Stereo 4. Ferrite bead filter 1. Modify Mode0 condition 2. Modify DC voltage on Gain0 vs. corresponding volume gain 1.Modify Oscillator frequency 2. package outline format Revision: /23

23 Important Notice All rights reserved. No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Revision: /23

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