HSMP-381x, 481x Surface Mount RF PIN Low Distortion Attenuator Diodes

Transcription

1 HSMP-81x, 481x Surface Mount RF PIN Low istortion Attenuator iodes ata Sheet escription/applications The HSMP-81x series is specifically designed for low distortion attenuator applications. The HSMP-481x products feature ultra low parasitic inductance in the SOT-2 and SOT-2 packages. They are specifically designed for use at frequencies which are much higher than the upper limit for conventional diodes. A SPI model is not available for PIN diodes as SPI does not provide for a key PIN diode characteristic, carrier lifetime. Features iodes Optimized for: Low istortion Attenuating Microwave Frequency Operation Surface Mount Packages Single and ual Versions Tape and Reel Options Available Low Failure in Time (FIT) Rate [1] Lead free Note: 1. For more information see the Surface Mount PIN Reliability ata Sheet. Package Lead ode Identification, SOT-2 (Top View) Package Lead ode Identification, SOT-2 (Top View) SINGL SRIS SINGL SRIS #0 #2 OMMON ANO OMMON ATHO OMMON ANO OMMON ATHO # #4 F RVRS SRIS UAL ATHO UAL ATHO #

2 Absolute Ratings [1] T = +25 Symbol Parameter Unit SOT-2 SOT-2 I f Forward urrent (1 μs Pulse) Amp 1 1 P IV Peak Inverse Voltage V Same as V R Same as V R T j Junction Temperature T stg Storage Temperature -65 to to 150 jc Thermal [2] /W Notes: 1. Operation in excess of any one of these conditions may result in permanent damage to the device. 2. T = +25, where T is defined to be the temperature at the package pins where contact is made to the circuit board. lectrical Specifications T = +25 (ach iode) onventional iodes Part Number HSMP- Package Marking ode Lead ode onfiguration Single Series 81 ommon Anode ommon athode Reverse Series 81 0 Single 81 2 Series 81 ommon Anode 81F 4 F ommon athode Test onditions Minimum reakdown Voltage V R (V) apacitance T (pf) Minimum at = 0.01mA, RH (Ω) at = 20mA, R L (Ω) at = 100mA, RT (Ω) at = 1mA, R M (Ω) to 70 = V R Measure I R 10uA = 50V f = 1MHz = 0.01mA = 20mA = 100mA = 1mA High Frequency (Low Inductance, 500 MHz GHz) PIN iodes Part Number HSMP- Package Marking ode Lead ode onfiguration 4810 ual athode 481 ual athode Test onditions Minimum reakdown Voltage V R (V) Series R S (Ω) Series = 1mA, R M (Ω) Typical apacitance T (pf) apacitance T (pf) Typical Inductance L T (nh) = V R Measure I R 10μA = 100mA f = 100MHz = 1mA = 50V f = 1MHz = 50V f = 1MHz f = 500MHz - GHz 2

3 Typical Parameters at T = 25 Part Number Series arrier Lifetime Reverse Recovery Time apacitance HSMP- R S (Ω) (ns) T rr (ns) T (pf) 81x V Test onditions = 1 ma f = 100 MHz = 50 ma I R = 250 ma = 10 V = 20 ma 90% Recovery f = 1 MHz Typical Parameters at T = 25 (unless otherwise noted), Single iode TOTAL APAITAN (pf) MHz 0 MHz frequency>100 MHz RVRS VOLTAG (V) Figure 1. RF apacitance vs. Reverse ias. RF RSISTAN (OHMS) T A = +85 T A = +25 T A = FORWAR IAS URRNT (ma) Figure 2. RF vs. Forward ias urrent, INPUT INTRPT POINT (dm) 120 iode Mounted as a 110 Series Attenuator in a 50 Ohm Microstrip 100 and Tested at 12 MHz IO RF RSISTAN (OHMS) Figure. 2nd Harmonic Input Intercept Point vs. iode RF. FORWAR URRNT (ma) V F FORWAR VOLTAG (ma) Figure 4. Forward urrent vs. Forward Voltage. Typical Applications for Multiple iode Products INPUT VARIAL IAS FIX IAS VOLTAG RF IN/OUT Figure 5. Four iode π Attenuator. See Application Note 1048 for etails. Notes:. Typical values were derived using limited samples during initial product characterization and may not be representative of the overall distribution.

4 Typical Applications for HSMP-481x Low Inductance Series Microstrip Series onnection for HSMP-481x Series In order to take full advantage of the low inductance of the HSMP-481x series when using them in series applications, both lead 1 and lead 2 should be connected together, as shown in Figure 7. HSMP-481x Figure 6. Internal onnections. Figure 7. ircuit Layout. Microstrip Shunt onnections for HSMP-481x Series In Figure 8, the center conductor of the microstrip line is interrupted and leads 1 and 2 of the HSMP-481x series diode are placed across the resulting gap. This forces the 1.5 nh lead inductance of leads 1 and 2 to appear as part of a low pass filter, reducing the shunt parasitic inductance and increasing the maximum available attenuation. The 0. nhof shunt inductance external to the diode is created by the via holes, and is a good estimate for 0.02" thick material. 1.5 nh 1.5 nh 50 OHM MIROSTRIP LINS R j 0. pf 0. nh PA ONNT TO GROUN Y TWO VIA HOLS R j I b nh Figure 8. ircuit Layout. Figure 9. quivalent ircuit. 4

5 Typical Applications for HSMP-481x Low Inductance Series (continued) o-planar Waveguide Shunt onnection for HSMP-481x Series o-planar waveguide, with ground on the top side of the printed circuit board, is shown in Figure 10. Since it eliminates the need for via holes to ground, it offers lower shunt parasitic inductance and higher maximum attenuation when compared to microstrip circuit. quivalent ircuit Model HSMP-81x hip* R s 2.5 Ω R j j o-planar Waveguide Groundplane enter onductor Groundplane R T = R j T = P + j R j = 80 I 0.9 Ω 0.18 pf* * Measured at -20 V I = Forward ias urrent in ma *See AN1124 for package models. Figure 10. ircuit Layout. R j 0. pf 0.75 nh Figure 11. quivalent ircuit. 5

6 Assembly Information SOT-2 P Footprint A recommended P pad layout for the miniature SOT-2 (S-70) package is shown in Figure 12 (dimensions are in inches). This layout provides ample allowance for package placement by automated assembly equipment without adding parasitics that could impair the performance imensions in inches Figure 12. Recommended P Pad Layout for Avago s S70 L/SOT-2 Products. SOT-2 P Footprint SMT Assembly Reliable assembly of surface mount components is a complex process that involves many material, process, and equipment factors, including: method of heating (e.g., IR or vapor phase reflow, wave soldering, etc.) circuit board material, conductor thickness and pattern, type of solder alloy, and the thermal conductivity and thermal mass of components. omponents with a low mass, such as the SOT-2/-2 package, will reach solder reflow temperatures faster than those with a greater mass. After ramping up from room temperature, the circuit board with components attached to it (held in place with solder paste) passes through one or more preheat zones. The preheat zones increase the temperature of the board and components to prevent thermal shock and begin evaporating solvents from the solder paste. The reflow zone briefly elevates the temperature sufficiently to produce a reflow of the solder. The rates of change of temperature for the ramp-up and cool-down zones are chosen to be low enough to not cause deformation of the board or damage to components due to thermal shock. The maximum temperature in the reflow zone (T MAX ) should not exceed 260. These parameters are typical for a surface mount assembly process for Avago diodes. As a general guideline, the circuit board and components should be exposed only to the minimum temperatures and times necessary to achieve a uniform reflow of solder imensions in inches mm Figure 1. Recommended P Pad Layout for Avago s SOT-2 Products. 6

7 Package imensions Outline 2 (SOT-2) e2 Outline SOT-2 (S-70) e1 e1 XXX 1 XXX 1 e L e L A1 Notes: XXX-package marking rawings are not to scale A SYMOL A A1 1 e e1 e2 L IMNSIONS (mm) MIN MAX A1 Notes: XXX-package marking rawings are not to scale A SYMOL A A1 1 e e1 L IMNSIONS (mm) MIN MAX typical 1.0 typical Package haracteristics Lead Material... opper (SOT-2); Alloy 42 (SOT-2) Lead Finish... Tin 100% (Lead-free option) Soldering Temperature for 5 seconds Minimum Lead Strength... 2 pounds pull Typical Package Inductance... 2 nh Typical Package apacitance pf (opposite leads) Ordering Information Specify part number followed by option. For example: HSMP - 81x - XXX ulk or Tape and Reel Option Part Number; x = Lead ode Surface Mount PIN Option escriptions -LKG = ulk, 100 pcs. per antistatic bag -TR1G = Tape and Reel, 000 devices per 7" reel -TR2G = Tape and Reel, 10,000 devices per 1" reel Tape and Reeling conforms to lectronic Industries RS-481, Taping of Surface Mounted omponents for Automated Placement. 7

8 evice Orientation For Outlines SOT-2/2 RL TOP VIW 4 mm N VIW ARRIR TAP 8 mm A A A A USR F IRTION OVR TAP Note: "A" represents package marking code. "" represents date code. Tape imensions and Product Orientation For Outline SOT-2 P P 2 P 0 F W t1 1 9 MAX Ko 8 MAX 1.5 MAX A 0 0 AVITY PRFORATION SRIPTION SYMOL SIZ (mm) SIZ (INHS) LNGTH WITH PTH PITH OTTOM HOL IAMTR IAMTR PITH POSITION A 0 0 K 0 P 1 P 0.15 ± ± ± ± ± ± ± ± ± ± ± ± ± ARRIR TAP WITH THIKNSS W t ± ± ISTAN TWN NTRLIN AVITY TO PRFORATION (WITH IRTION) AVITY TO PRFORATION (LNGTH IRTION) F P 2.50 ± ± ± ±

9 Tape imensions and Product Orientation For Outline SOT-2 P P 2 P 0 F W t 1 (ARRIR TAP THIKNSS) 1 T t (OVR TAP THIKNSS) An K 0 An A 0 0 AVITY PRFORATION SRIPTION SYMOL SIZ (mm) SIZ (INHS) LNGTH WITH PTH PITH OTTOM HOL IAMTR IAMTR PITH POSITION A 0 0 K 0 P 1 P ± ± ± ± ± ± ± ± ± ± ± ± ± ± ARRIR TAP OVR TAP ISTAN ANGL WITH THIKNSS WITH TAP THIKNSS AVITY TO PRFORATION (WITH IRTION) AVITY TO PRFORATION (LNGTH IRTION) W 8.00 ± 0.0 t ± ± 0.10 T t ± F.50 ± 0.05 P ± 0.05 FOR SOT-2 (S70- LA) An 8 MAX FOR SOT-6 (S70-6 LA) 10 MAX 0.15 ± ± ± ± ± ± For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. ata subject to change. opyright Avago Technologies. All rights reserved. Obsoletes AV01-078N AV N - ecember 22, 2009