6. Design implementation

Transcription

1 6. Design implementation 6.1 Introduction Each process in IC-technology usually comes with documentation on paper about all process details and the contents of the libraries. For all the types of transistors available in the process, standard cells with specific design optimisations (size, current) are given in the libraries. Based on SPICE models, the I-V characteristics of the transistors are given. This helps start the design. For the transistors however, the design parameters need to be worked out, based on the requirements of the specification. This chapter is divided in two sections. First the high-voltage, analogue part of the chip is described. In this section the anode switches, cathode switches, discharge unit and current source design will be given. In the digital section the control logic of these units is described. 6.2 Analogue part overview Before designing the switches that are involved in stimulation, first the potentials in the channel are considered. Because one of the specifications is that is should be able to run with a supply voltage of (only) 15 V, it is important to watch the voltage drop over the electrodes, switches and current source. The several voltage drops are given in Fig. 14. V swa V swd V DR V e V swc V CS Fig. 14: Voltage drop over several parts in a stimulation channel. 37

2 When the channel is stimulated the cathode switch and anode switch are closed and the current source operates. The electrode impedance in series with the cable resistance is at minimum of 350 ma this gives a voltage (V e ) of 11.2 V. This gives 3.8 V left for two switches, the current source and the capacitor. The switches should be able to drop only 500 mv (V a and V c ). The current source should operate with a saturation voltage of 1 V (V CS ). Finally the blocking capacitor may build up a voltage of 1.8 V. This is the same as the maximal voltage across the capacitor in the Mark-5 stimulator. However now the current has a value of 32 ma, so the capacitor value needs to be increased (to > 21! cathode switches and curr ent sources In the Design specification the cathode switches and current sources are put in a separate box, this is not essential: the cathode switches could be designed as switched current sources. In theory the following option are available, where - means that the switch acts as an current source: Cathode switch Current source Comment BJT BJT Switching characteristics are non-linear, in current source base current effects BJT FET Switching characteristics are non-linear, simple current source implementation BJT - Base current effects and control lines for current setting to all channels FET BJT Switching characteristics are linear, in current source base current effects FET FET Switching characteristics are linear, simple current source implementation FET - Control lines for current setting to all channels Based on the comments written in the table, the FET-FET option would probably be chosen, however it should be noticed that there is a size-difference between an MOSFET and a bipolar transistor for high currents and high supply voltages. This difference is about 10 times for a current of 32 ma and a saturation voltage of 0.5 V in this process 6. To compare the real sizes: a bipolar transistor (cell HNHP350A from library) needs mm 2, the FET (FND W=10mm) mm 2 and finally the round FET type (FNDR W=10mm) needs mm 2. This disadvantage of the MOSFET s leads us to the solution of a BJT as switch, because the total area occupied by them is 14 times less! For the current source three options are still available. The choice for current source design is now an optimisation on: total chip area minimal voltage supply to operate (less than 1 V in total) other characteristics (like speed, accuracy) 6 In the previous chapter the process 'Alcatel-Mietec 2µ HBIMOS HV' has been chosen. In this chapter all calculations apply to this process. 38

3 For one channel, based on the cells that are available in this process library, the choices are given in Fig. 15 (option A), Fig. 16 (option B) and Fig. 17 (option C). 2mA out stimulation 1x 2x 4x 8x 16x I=2mA I=4mA I=8mA I=16mA I=32mA Fig. 15: One stimulation channel with the use of an adjustable bipolar current-mirror as current source used for all channels and a bipolar transistor switching the cathode during stimulation. 2mA out stimulation 1x 2x 4x 8x 16x I=2mA I=4mA I=8mA I=16mA I=32mA Fig. 16: One stimulation channel with the use of an adjustable FET-based current-mirror as current source for all channels and a bipolar transistor switching the cathode during stimulating.. 39

4 2mA out 1x 2x 4x 8x 16x stimulation I=2mA I=4mA I=8mA I=16mA I=32mA Fig. 17: One stimulation channel with the use of an adjustable bipolar current-mirror as current source for each channel that also is switched during stimulation Anode and discharge swit ches The same size considerations as for the cathode switches apply to the anode switches. This means that a bipolar transistor is preferable to an FET. Since a bipolar transistor is a threeterminal device, which requires a base current to turn it on, the use of a PNP version has the advantage over the NPN version, that the current through the collector, that is determined by the current source in the system, will not be affected by any base current. The use of an NPN would it make harder for the current source to keep the current on the required value, since the base current is added to the emitter current. The size of one PNP transistor in this process is mm 2, a little larger than a NPN transistor with the same current flow. The discharge switch with resistor can be implemented by using a FET. Alternatively resitivity sheets are available in this process, but their value can not be designed accurately. To remove for example 99% of the charge from the capacitor (and electrode capacitance) through the electrode impedance and discharge resistor (FET) the later should have a value of 600 "#%$ & ' (*)+, & ()'-/. -/()-021(43 $ )65 7%#8190;: <9">=? -3 mm 2. 40

5 6.3 Digital part switches control The working of the shift register (SR) that act as a de-multiplexer for the signal data2 with the use of data1 to indicate the start with stimulation of channel 1, has already been described in the Introduction of the Design specification (par. 5.1). To prevent the system from improper use (the second objective in the research definition), between the SR-cells AND-gates are placed. As soon as data1 becomes high the inverter makes the input for all AND-gates low and all SR-cells will "clock in" a low, except the first SR-cell. Therefore it will not occur that more than one channel is being stimulated. Actually, in the real design, the AND-gates are replaced by NOR-gates, since the later are standard digital cells. This adjustment in design will be done with finally no effect in the operation of the de-multiplexer, as described above. sw A ch1 sw B ch1 sw A ch2 sw B ch2 sw A ch3 sw B ch3 data2 clock data1 D D D D Fig. 18: de-multiplexer logic to control anode, cathode and discharge switches and to turn on the current sources. Each cell of the shift register in Fig. 18 has two outputs. The first output (A) becomes high as soon as a channel is going to be stimulated. This output can be used for example to close already the anode switch, disable the discharge unit and activate the current source. The second output (B) will become high at least 30 µs after output A and extent exactly the intended stimulation pulse duration (see Fig. 19). This signal can be used to close the cathode switch. 41

6 1 2 3 Clock Data1 Data2 SW A ch1 SW B ch1 SW A ch2 SW B ch2 Fig. 19: Input and output lines of de-multiplexer logic, example for two channels, during normal operation Current change control In the change mode of the chip, that is when the input signal change_mode has been pulled high, the current setting can be changed by a special input sequence. Generally a maximum of 14 channels is stimulated and then "channel one" is used again by the data1 input signal becoming high. If for example a virtual 15 th channel would be stimulated before starting with channel one again, there is a gab of 15 cells between the one in the first SR-cell and the one in the 16 th SR-cell. (There is no obstruction of an AND-gate for the SR-cells 15 till 34.) This gap can be detected as soon as the one has propagated to the 31 th SR-cell, see Fig. 23. At that moment the other one has arrived in the 15 th SR-cell. Internal signal B becomes high. 42

7 data2 clock data A B C D E Fig. 20: Extended shiftregister to detect special word for change current setting. Virtually stimulating more than 14 channels will be detected as a special meaning. Also a gap of 16, 17 or 18 can be generated, which will be detected and respectively outputs C, D, and E become high. To avoid current change by any mistake in the program or hardware failure, the following special sequence should be used: B-B-E C-C-E D-D-E reset both current source settings to initial value. Initial value is set external by a resistor change the current setting of current source A to the next higher level change the current setting of current source B to the next higher level The detection of these internal signal sequence can be carried out by the design showed in Fig. 21. The unit has an input signal (B, C, or D) corresponding to the purpose of it: reset, change CS A or change CS B. The input signal will be clocked in into a three cell long shift register, as soon as an one arives in the 15 th SR-cell. B, C, or D clock A E Change_mode Reset, change CS A, or change CS B Fig. 21: Detection of special sequence of internal signals for changing the current setting. clock Data A Fig. 22: Normal operation, signal A becomes high every 15 cycles. Other internal data lines remain low. 43

8 Data1 A B E Fig. 23: Timingsdiagram for internal data lines A, B and E. It can be seen that B becomes 2 times high, before E becomes high and both signals can be clocked in by signal A current sources control The current sources are controlled by five switches, for the corresponding 2, 4, 8, 16 and 32 ma, so only one switch will be closed at a time. The logic in this section will control those switches. The initial current setting will be set by reading the internal data lines that come from the box initial current setting. Basically this device is transparent for these internal data signals, when no information is provided by the change current detect segment indicates to change the current. D 4 D 3 D 2 D 1 D 0 Serial in S/L clk Fig. 24: Circulating shiftregister to control current source. The output controls the switches that sets the current source to the corresponding binary value. Parallel input for initial current setting and serial loading for changing the current setting to the next higher level. Fig. 24 gives one of the two basic components that this segment contains. It acts as an ordinary shift register that latches the input to the output when S/L_ is low and CLK remains low. These input signals come from the change current detect segment and the output lines lead to the current sources. The input line S/L_ signal is based on the chip s input change_mode and the initial resetline in the change current detect segment. This means that when this signal is made high it is possible to change the current setting. The shift register will than operate in serial mode and the contents of the five SR-cells will shift up. This means that the one that is present in one of the five SR-cells will move to the next output and will therefore operate the switch in the current source that sets the next higher current (or goes back to 2 ma, after it reached 32 ma). Reset to the initial current value is done be loading (latching) the input. 44