Low-Power Design. Prof. Dr. Marcel Jacomet Bern University of Applied Sciences Bfh-Ti HuCE-microLab, Biel/Bienne.

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1 Prof. Dr. Marcel Jacomet Bern University of Applied Sciences Bfh-Ti HuCE-microLab, Biel/Bienne HuCE.ch/microLab February 10, /24

2 Outline 2/24

3 Low-Power Circuit Design Importance electronic devices have greatly reduced in size and mass over past decades Cmos technology has exponential growth energy storage technology has grown at a slow rate strong need for low power designs 3/24

Low-Power Application Areas portable computing, communication and

.. remote sensing devices long-term environmental monitoring in wilderness

.. implantable biomedical devices pacemakers, defribillators, muscle

4 Low-Power Application Areas portable computing, communication and multimedia devices laptops, cell phones, cameras, watches,... remote sensing devices long-term environmental monitoring in wilderness ares, mobile robots, satellites,... implantable biomedical devices pacemakers, defribillators, muscle stimulations, neuroprosthetic devices (cochlear implants to restore hearing loss, retinal and cortical stimulators to restore vision loss...) 4/24

5 Power Sources for Low-Power Devices batteries are most common power source for portable devices convert chemical energy into electrical energy energy harvesting convert various energy forms into electrical energy (solar, wind, water, thermo, vibration,...) medical: solar cells under skin, fluid turbins in blood vessels, mechanical movement of heart,... inductive coupled power link: RFID used in medical implants, smart cards, mobiles, LiyC Li1-xCoO2 electrolyte anode cathode 5/24

6 Power Sources for Low-Power Devices batteries are most common power source for portable devices convert chemical energy into electrical energy energy harvesting convert various energy forms into electrical energy (solar, wind, water, thermo, vibration,...) medical: solar cells under skin, fluid turbins in blood vessels, mechanical movement of heart,... inductive coupled power link: RFID used in medical implants, smart cards, mobiles,... current flow charger cathode: LiCoO 2 Li 1 x CoO 2 +xli + +xe - e- + anode: C+xLi + +xe LiyC Li1-xCoO2 Li x C Li+ Li+ overal: Li+ e- e- LiCoO 2 +C Li x C+Li 1 x CoO 2 electrolyte anode cathode charging 5/24

7 Power Sources for Low-Power Devices batteries are most common power source for portable devices convert chemical energy into electrical energy energy harvesting convert various energy forms into electrical energy (solar, wind, water, thermo, vibration,...) medical: solar cells under skin, fluid turbins in blood vessels, mechanical movement of heart,... inductive coupled power link: RFID used in medical implants, smart cards, mobiles,... current flow cathode: LiCoO 2 Li 1 x CoO 2 +xli + +xe - + anode: C+xLi + +xe LiyC Li1-xCoO2 Li x C Li+ Li+ overal: Li+ e- e- LiCoO 2 +C Li x C+Li 1 x CoO 2 electrolyte anode cathode load e- discharging 5/24

8 : Non-Rechargeable open energy cost applications type circuit density and notes voltage [mwh/cm 3 ] Zinc-Carbon 1.5 V lowest sloping discharge curve older technology Alkaline 1.5 V low sloping discharge curve most common battery Mercury 1.35 V 450 high low current only Zinc-Air 1.5 V 1050 moderate consumes O 2 from air highest density Silver-Oxide 1.55 V high low current only flat discharge curve Lithium-SVO V 500 high low current only very low self-discharge Lithium 3.0 V high very long shelf live flat discharge curve 1 Lithium Silver-Vanadium-Oxide 6/24

9 : Applications of Non-Rechargeable application Alkaline Zink-Air Li-SVO Li Silver Mercury consumer electronics x film cameras x x smoke detector x x Cmos Ram backup x wristwatch x medical implants x x x 7/24

10 : Rechargeable open energy cost applications type circuit density and notes voltage [mwh/g] Ni-Cd 1.35 V 450 high cycles flat discharge curve NiMH 1.5 V 1050 moderate 500 cycles flat discharge curve Li-Ion V high cycles flat discharge curve Lead Acid V high high current possible 8/24

11 : Applications of Rechargeable application NiCd NiMH Li-Ion Lead-Acid consumer electronics x x cell phones x x laptops x x video cameras x palmtops x gasoline cars x electro hybrid cars x x x 9/24

12 ITRS : Battery Capacity battery capacity [Wh] Scaling of battery capacity for mobiles year source: /24

13 Power Density History 10 3 Power Density rocket nozzle power density W/cm nuclear reactor hot plate year source: Intel, R. Chau 11/24

14 ITRS : Gate Scaling gate length [nm] Gate length scaling for microprocessors year source: /24

15 Supply Voltage History supply voltage [V] Voltage Scaling year source: Intel and others 13/24

16 ITRS : Supply Voltage Vdd [V] Supply voltage scaling for high/low performance 0.5 medical device chip at HuCE year source: /24

17 power consumption per operation is low, compared to other technologies gate length down-scaling increases power dissipation density with respect to chip area power dissipation produces heat on the chip, which has to be carried off through the chip socket power dissipation is one of the limiting factors in todays Cmos Vlsi chips low power application is a speciality of our silicon lake area 15/24

18 Sources of Power Dissipation 16/24

19 Sources of Power Dissipation 16/24

20 Power Dissipation there is always one Fet block off, so only leakage current is flowing 3 to 5 molecules of SiO2 dielectric ± 1 molecule makes the difference 17/24

21 Power Dissipation Eqn two technology controlled leakage currents: reverse-bias diode leakage current at the Fet drains one Fet turned-off, the other turned-on Fet charges ( ) I leak-rbd = I S e V dd V T 1, reverse saturation current I S subthreshold current through turned-off Fet channels one Fet turned-on, the other turned-off Fet being in subthreshold ( ) I leak-sub = Ke (Vgs V th)/nv T 1 e V ds V T n-fet p-fet p+ n+ n+ p+ p+ n+ n- p- 18/24

22 Power Dissipation Eqn two technology controlled leakage currents: reverse-bias diode leakage current at the Fet drains one Fet turned-off, the other turned-on Fet charges ( ) I leak-rbd = I S e V dd V T 1, reverse saturation current I S subthreshold current through turned-off Fet channels one Fet turned-on, the other turned-off Fet being in subthreshold ( ) I leak-sub = Ke (Vgs V th)/nv T 1 e V ds V T 18/24

23 Power Dissipation Eqn two technology controlled leakage currents: reverse-bias diode leakage current at the Fet drains one Fet turned-off, the other turned-on Fet charges ( ) I leak-rbd = I S e V dd V T 1, reverse saturation current I S subthreshold current through turned-off Fet channels one Fet turned-on, the other turned-off Fet being in subthreshold ( ) I leak-sub = Ke (Vgs V th)/nv T 1 e V ds V T n-fet p-fet p+ n+ n+ p+ p+ n+ n- p- 18/24

24 Power Dissipation Eqn two technology controlled leakage currents: reverse-bias diode leakage current at the Fet drains one Fet turned-off, the other turned-on Fet charges ( ) I leak-rbd = I S e V dd V T 1, reverse saturation current I S subthreshold current through turned-off Fet channels one Fet turned-on, the other turned-off Fet being in subthreshold ( ) I leak-sub = Ke (Vgs V th)/nv T 1 e V ds V T n-fet (on) Vdd CL Vout=0 p-fet (off) Vdd Vdd p+ n+ n+ p+ p+ n+ subthreshold leakage n- p- 18/24

25 Power Dissipation dissipation is caused by charging and discharging the load and internal capacitantes switching activity factor N respects that not every node is switched in every clock cycle average dynamic power for switching a square-wave input with a repetition frequency f = 1/t is: P sw = 1 t t/2 0 i n(t)v outdt + 1 t t t/2 i p(t)(v dd V out)dt with i n(t) = C L dv out/dt we get V dd 0 P sw = C L f V outdv out +C L f (V dd V out)d(v dd V out) 0 V dd Dynamic Dissipation Psw Switching using switching activity N, resulting in: P sw = NC L V 2 ddf I sw off C load 19/24

26 Power Dissipation dissipation is caused by charging and discharging the load and internal capacitantes switching activity factor N respects that not every node is switched in every clock cycle average dynamic power for switching a square-wave input with a repetition frequency f = 1/t is: P sw = 1 t t/2 0 i n(t)v outdt + 1 t t t/2 i p(t)(v dd V out)dt with i n(t) = C L dv out/dt we get V dd 0 P sw = C L f V outdv out +C L f (V dd V out)d(v dd V out) 0 V dd Dynamic Dissipation Psw off Switching using switching activity N, resulting in: P sw = NC L V 2 ddf I sw C load 19/24

27 Power Dissipation dissipation is caused by charging and discharging the load and internal capacitantes switching activity factor N respects that not every node is switched in every clock cycle average dynamic power for switching a square-wave input with a repetition frequency f = 1/t is: P sw = 1 t t/2 0 i n(t)v outdt + 1 t t t/2 i p(t)(v dd V out)dt with i n(t) = C L dv out/dt we get V dd 0 P sw = C L f V outdv out +C L f (V dd V out)d(v dd V out) 0 V dd Dynamic Dissipation Psw off Switching using switching activity N, resulting in: P sw = NC L V 2 ddf I sw C load 19/24

28 Power Dissipation dissipation is caused by charging and discharging the load and internal capacitantes switching activity factor N respects that not every node is switched in every clock cycle average dynamic power for switching a square-wave input with a repetition frequency f = 1/t is: P sw = 1 t t/2 0 i n(t)v outdt + 1 t t t/2 i p(t)(v dd V out)dt with i n(t) = C L dv out/dt we get V dd 0 P sw = C L f V outdv out +C L f (V dd V out)d(v dd V out) 0 V dd Dynamic Dissipation Psw off Switching using switching activity N, resulting in: P sw = NC L V 2 ddf I sw C load 19/24

29 Dynamic Short Circuit Power Dissipation average dynamic power dissipation for switching square-wave input short circuit current through n-fet and p-fet when switching, with some calculations we can find: Psh = β 12 trf t tp (V dd 2V t) 3 Vdd Psh lin Vtn tp Imax off C load Imin 20/24

30 Dynamic Short Circuit Power Dissipation average dynamic power dissipation for switching square-wave input short circuit current through n-fet and p-fet when switching, with some calculations we can find: Psh = β 12 trf t tp (V dd 2V t) 3 20/24

31 Dynamic Short Circuit Power Dissipation average dynamic power dissipation for switching square-wave input short circuit current through n-fet and p-fet when switching, with some calculations we can find: Psh = β 12 trf t tp (V dd 2V t) 3 Vdd tr Psh sat Vtn I sh tp Imax sat C load Imin t1t2 20/24

32 Dynamic Short Circuit Power Dissipation average dynamic power dissipation for switching square-wave input short circuit current through n-fet and p-fet when switching, with some calculations we can find: Psh = β 12 trf t tp (V dd 2V t) 3 Vdd Vdd+Vtp tr Psh off Vtn I sh tp Imax lin C load Imin t1t2t3 20/24

33 Dynamic Short Circuit Power Dissipation average dynamic power dissipation for switching square-wave input short circuit current through n-fet and p-fet when switching, with some calculations we can find: Psh = β 12 trf t tp (V dd 2V t) 3 Vdd Vdd+Vtp tr Psh off Vtn I sh tp Imax lin C load Imin t1t2t3 20/24

34 Dynamic Short Circuit Power Dissipation average dynamic power dissipation for switching square-wave input short circuit current through n-fet and p-fet when switching, with some calculations we can find: Psh = β 12 trf t tp (V dd 2V t) 3 Vdd Vdd+Vtp tr Psh off Vtn I sh tp Imax lin C load Imin t1t2t3 20/24

35 Dynamic Short Circuit Power Dissipation average dynamic power dissipation for switching square-wave input short circuit current through n-fet and p-fet when switching, with some calculations we can find: Psh = β 12 trf t tp (V dd 2V t) 3 Vdd Vdd+Vtp tr tf Psh on Vtn I sh tp Imax off C load Imin t1t2t3 20/24

36 Dynamic Short Circuit Power Dissipation average dynamic power dissipation for switching square-wave input short circuit current through n-fet and p-fet when switching, with some calculations we can find: Psh = β 12 trf t tp (V dd 2V t) 3 Vdd Vdd+Vtp tr tf Psh on Vtn I sh tp Imax off C load Imin t1t2t3 20/24

37 Power Saving we will observe a shift in the power consumption saving potential at various design phases in technologies > 25nm the highest saving potential is in the physical design level in technologies < 16nm the highest saving potential is in the behavioral design level 5% 10% 15% 20% 25% 30% 35% 40% 45% 50% 55% 60% 65% 70% 75% 80% 85% 90% 95% 100% power minimization 2011 behavioral level 30% architectural level 20% RTL level 10% physical level 40% power minimization 2013 behavioral level 40% architectural level 30% RTL level 10% physical level 20% power minimization 2015 behavioral level 50% architectural level 30% RTL level 10% physical level 10% Evolving role of design phases in overal system power minimization 21/24

Power Saving Methods clock gating voltage scaling (multi Vdd) frequency scaling multi-threshold logic low-power logic styles pass transistor logic dynamic logic, domino logic charge recovery and

38 Power Saving Methods clock gating voltage scaling (multi Vdd) frequency scaling multi-threshold logic low-power logic styles pass transistor logic dynamic logic, domino logic charge recovery and adiabatic logic subthreshold source-coupled circuits asynchronous logic low-power architectural styles logarithmic number system, residue number systems factorized canonic signed digit number coding (F-CSD) low-power behavioral styles algorithmic level transforms operation reduction, substitution precomputation based optimisation 22/24

39 clk en date stored mux REG data in FSM out en D Q clk out clk clk 23/24

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45 Conclusion power consumption is a major challenge in chip design more complexe and calculation intensive designs increase power consumption technology scaling increases low-power design challenge battery technologies improve too slow low-power techniques will be key issue in consumer products for biomedical applications low-power techniques are crucial low-power design techniques require design flow modifications new low-power design techniques and process technolologies are needed 24/24

Low Power Design Part I Introduction and VHDL design. Ricardo Santos LSCAD/FACOM/UFMS

Low Power Design Part I Introduction and VHDL design Ricardo Santos ricardo@facom.ufms.br LSCAD/FACOM/UFMS Motivation for Low Power Design Low power design is important from three different reasons Device