PADI, a new ASIC for RPC's RPC's and other timing detectors Mircea Ciobanu

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1 PADI, a new ASIC for RPC's RPC's and other timing detectors Mircea Ciobanu NoRDHia Meeting August 30-1 September 2006 GSI-Darmstadt

2 Outline Introduction to timing measurements Simulations Integrated circuits(fee3) vs Custom chip(nino2) DESIGN of PADI ASIC, starting from NINO1 Comparison: PADI versus NINO1 a) Time over Threshold behavior b) Timing performance Summary and Outlook

3 Basic components of a timing measurement Typical Errors if σ n ~ Nd*BW dv/dt ~ As/t r t r =0.35/BW then σ t ~ Nd / As BW " WALK " " JITTER"

4 "Walk" and Sigma versus: UINP, Amplifier BW, Detector Rise Time Detector signal is Step with variable Rise Time, Noise=3uV, THR=100mV Amplifier BW "WALK" [ns] Blue 35MHz Green 350MHz Red 3.5GHz Black 35GHz UINP [mv] SIGMA [ps] Detector signal Rise Time UINP [mv] Triangle 10ns Diamond 1ns Square 100ps Circle 10ps

5 "Walk" and Sigma versus: UINP, Amplifier BW, Detector Rise Time Detector signal is Step with variable Rise Time "WALK" [ns] Detector signal Rise Time Circle 10ps Square 100ps Diamond 1ns Triangle 10ns UINP [mv] SIGMA [ps] UINP [mv] Amplifier BW Blue 35MHz Green 350MHz Red 3.5GHz Black 35GHz

6 UINP [mv] UINP [mv] Sigma versus UINP and THRESHOLD for two Noise values SIGMA [ns] INPUT NOISE=24uV SIGMA [ps] INPUT NOISE=3uV THRESHOLD -20mV -40mV -60mV -80mV -100mV

7 Comparative Dependence to BW and Signal Rise Time for : Resistive Plate Chamber, PC and SC Diamonds SIGMA [ps] Signal: Triangle, TR=TF SIGMA [ps] Signal: Triangle, TF=1ns SIGMA [ps] Signal: Trapez, 4ns, TR=TF 100 UINP=2mV UTHR=60mV Signal : TR 30ps 100ps 300ps 1ns C F [pf] 1 1 C F [pf] CF [pf]

8 Simulations with CADENCE for FEE-gain dependence GAIN=200 GAIN=100 GAIN=50 INPUT NOISE =24uV GAIN= RPC RPC RPC RPC Upper limit for FEE SIGMA [ps] FOPI-threshold FOPI-combined "noise level" U n ~50-60 mv 1 THRESHOLD -100mV -80mV -60mV -40mV -20mV 100 UINP [mv] UINP [m V] UINP [mv] UINP [mv] Operating gain for FOPI

9 FOPI Experimental Results MRPC 19b 90cm-8Gaps-16Strips Efficiency (%) σ t (ps) Timing & Efficiency for four gain settings (77,130,160,220) of FEE3 with FOPI MMRPCs. U thr ~80 mv 20 Single Hits E-Field (kv/cm) FEE-Gain 220 FEE-Gain 160 FEE-Gain 130 FEE-Gain Balance between electronic gain, detector gain and threshold.

-OR output - Gain ~160 strong non-linear (stabilized LVDR).

10 FEE3 FEE-NINO - 16 channels with discreet IC. - Single ended 50 Ohms inputs, differential Time and Amplitude outputs. -OR output - Gain ~160 strong non-linear (stabilized LVDR). - External: Threshold voltage, TEST E/D, LATCH E/D - 16 channels with two NINO2 IC. - Differential 100 Ohms inputs, differential Time outputs with Time over-threshold modulation - OR input and output - External: Threshold voltage, TEST E/D

11 Combined Time Resolution of two channels: Input signal is ~1.67mV or ~42fC FEE-NINO + Tacquila2 t ~ 81ps Daten: Count1_Count Modell: Gauss Gleichung: y=y0 + (A/(w*sqrt(PI/2)))*exp(-2*((x-xc)/w)^2) Gewicht: y Keine Gewichtung. Chi^2/DoF = R^2 = y ± xc ± w ± A ± Inputsignal: 500mV, 49.5dB attenuation FEE3 + Tacquila2 t ~34,3ps Daten: Count1_Count Modell: Gauss Gleichung: y=y0 + (A/(w*sqrt(PI/2)))*exp(-2*((x-xc)/w)^2) Gewicht: y Keine Gewichtung. Chi^2/DoF = R^2 = y ± xc ± w ± A ± C ount s 300 C ount s 600 Inputsignal: 500mV, 49.5dB attenuation Time-Bins Time-Bins

12 Combined Timing Resolution with TACQUILA 2 60 Comparison FEE_NINO versus FEE3 One channel Timing Resolution FOPI 8-gap counters 50 Ω ALICE 10-gap counters 100 Ω FEE_NINO,No.1,Ch1+Ch3+Taquila2 FEE3,No4,Ch1+Ch3+Taquila2,THR=61mV Sigma [ps] UINPUT [mv]

United Microelectronics Corp. ) Development of a Front-End ASIC for TEGS TPC G.

13 About Technology: CMOS : AMS 0.35um or UMC 0.18um? D ( AMS Austria Mikro Systeme International,, UMC United Microelectronics Corp. United Microelectronics Corp. ) Development of a Front-End ASIC for TEGS TPC G.De Geronimo, Paul O'Connor, Veljko Radeka, Bo Yu Vth International Meeting on FEE, 2003 Low noise charge amplifiers in submicron CMOS P.O'Connor, J.-F.Pratte, G.De Geronimo Vth International Meeting on FEE, 2003

14 NINO2 structure IBM CMOS 0.25 um technology F.Anghenolfi and al, NINO: an ultra-fast and low-power front-end amplifier/discriminator ASIC designed for the multigap resistive plate chamber, Nuclear Instruments and Methods in Physics Research A 533 (2004)

15 PADI block diagram +1.8V 0V VDD VSS Rext Rext + Rext - Bias Buffer Eout+ Ch 1-4 Iext Bias Tout Eout- Input+ Tout+ Ch 1-4 PA DI Ch 1-4 Input- Tout- THR+ THR- Hys Threshold Voltage Hyssteresis En/Dis

16 Preamplifier: AC equivalent diagram

17 Discriminator: AC equivalent diagram Hyssteresis Enable/Disable TA4 Cp1 R1 Cp2 R2 Cp3 R3 R4 Cp4 TA1 TA2 TA3 TA5 Rl Cl Signal Input Cp1 R1 Cp2 R2 Cp3 R3 Output R4 Cp4

18 AC simulations PADI sch. PADI sch. with NINO1 sch. Cp.layout Gain BW Gain BW Gain BW [db] [MHz] [db] [MHz] [db] [MHz] Preamplifier Low pass corner PA Out Buffer Eout Discriminator TOut, Hys=off Noise on PADI Preamplifier: sch. sch.whith Cp. layout Simulation BW [MHz] Noise PA Out [mv RMS] Noise on NINO1 Preamplifier sch. Simulation BW [MHz] Noise PA Out [mv RMS]

19 Comparison on Delay Times NINO versus PADI NINO Delay Time Tr 8 NINO Delay Time Tf 8 NINO Time over Threshold 1.1 PADI Delay Time Tr 5 PADI Delay Time Tf 5 PADI Time over Threshold Threshold Voltage -32mV -64mV -128mV -256mV -512mV 3 Tr [ns] 1 Tf [ns] ToT [ns] 4 Tr [ns] 0.7 Tf [ns] 3 ToT [ns] QIN [fc] QIN [fc] QIN [fc] QIN [fc] QIN [fc] QIN [fc]

20 Comparison on Time Resolution: NINO versus PADI NINO Time Resolution PADI Time Resolution 0 0 Time Resolution [ns] 0 Time Resolution [ns] 0-32mV -64mV -128mV -256mV -512mV -32mV -54mV -128mV -256mV -512mV QINP [fc] QIN [fc]

21 Time Resolution [ns] Comparison Time Resolution PADI versus NINO NINO -32mV NINO -64mV NINO -128mV NINO -256mV NINO -512mV PADI -32mV PADI -64mV PADI -128mV PADI -256mV PADI -512mV QINP [fc]

22 PADI The Layout parasitic capacitance increase the Time Resolution 0 PADI The influence of Layout parasitic capacitances on Time Resolution loss: ~30% Time Resolution [ns] mV -64mV -128mV -256mV -512mV -32mV; Cp -64mV; Cp -128mV; Cp -256mV; Cp -512mV; Cp QIN [fc]

23 WALK Correction: Time over Threshold or Q measurement? PADI PADI EOut Peack Amplitudes (ref: midpoint 0 V) EOut Peack Amplitudes (ref: baseline) PADI Time over Threshold Threshold Voltage -32mV -64mV -128mV -256mV -512mV Vpk [mv] Vpk [mv] ToT [ns] Baseline Voltage -21mV mV -84mV -164mV mV QIN [fc] QIN [fc] QIN [fc]

24 WALK Correction:... or Integrated Q measurement? 2000 Integral for fixed time (15 ns) Baseline correction before Integral for fixed time (15ns) INT. EOut [pvs] QIN [fc] QIN [fc]

25 PADI!NEW ASIC! the prototype has only 3 channels Preamplifier & Discriminator in 0.18µm CMOS technology 1.5x1.5mm2

26 Summary FEE3 vs FEE-NINO Due to the full differential structure, FEE-NINO has a lower sensitivity to pick-up of parasitic signals. To use all benefits of this design, the detector must be differential too. Outlook We wait for first PADI chips for tests. The increase of PADI preamp/discriminator actual bandwidth is a hard task, but we will try to evaluate the limit of the used architecture. ture. We will investigate the possibility to change the biasing type, from voltage to current, to decrease the crosstalk inside the PADI chip.

27 We acknowledge the support of the European Community- Research Infrastructure Activity under the FP6 "Structuring the European Research Area" programme (HadronPhysics, contract number RII3-CT ).

28 Time over Threshold tests for FEE-NINO 30 FEE_NINO : Time over Threshold Width of the output pulse, Input pulse is short triangle (1.8ns). FEE_NINO : Time over Threshold Width of the output pulse, Input pulse is step type. OUTPULSE [ns] UINP [mv] NINO2,Ch11 NINO2,Ch12 NINO2,Ch14 NINO2,Ch15 NINO1,Ch1 NINO1,Ch2 NINO1,Ch3 NINO1,Ch4 NINO1,Ch5 NINO1,Ch6 NINO1,Ch7 NINO1,Ch8 A) short pulse 1.9 ns at FWHM OUTPULSE [ns] NINO2,Ch11 NINO2,Ch12 NINO2,Ch14 NINO2,Ch15 NINO1,Ch1 NINO1,Ch2 NINO1,Ch3 NINO1,Ch4 NINO1,Ch5 NINO1,Ch6 NINO1,Ch7 NINO1,Ch UINP [mv] B) step pulse

29 Time Resolution measured with TDS 7104 Oscilloscope 1.3 GHz Comparison FEE_NINO versus FEE3 Timing Resolution FEE3, No4, Ch1, THR=116mV FEE3, No4, Ch1, THR=45mV FEE_NINO, No.2, 4 channels FEE_NINO, No.1, 8 channels Preliminary results Sigma [ps] UINPUT [mv]

Progress in RPC- FEE development

FEE Progress in RPC- FEE development FEE2 Mircea Ciobanu First FAIR FEE Workshop October -,, 2005 GSI,Darmstadt FEE status (March 2005) ( CBM collaboration meeting March 9-2, 9 2005 ). For the actual design,