DESIGN FOR MOSIS EDUCATIONAL RESEARCH PROGRAM REPORT CMOS MAGNETIC FIELD STRUCTURES AND READ-OUT CIRCUIT. Prepared By: B.

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1 Grupo de Microsensores y Circuitos Integrados DESIGN FOR MOSIS EDUCATIONAL RESEARCH PROGRAM REPORT CMOS MAGNETIC FIELD STRUCTURES AND READ-OUT CIRCUIT Prepared By: B. Susana Soto Cruz Senior Research Institution: Benemérita Universidad Autónoma de Puebla Centro de Investigación en Dispositivos Semiconductores Date of Submission: 1/08/09

2 Abstract The CMOS Magnetic Field Structures and Read-Out Circuit project was implemented on AMI C5F process in an area of 1.69 mm x 1.69 mm area with 24 pads. The submitted design comprises Hall structures, interface and bias circuits. The principal aim was to estimate the Hall sensor sensitivity in order to obtain the specifications for biological applications. Special care must be had to minimize the noise and the temperature variations. Report of the Project 1. Chip dimensions a) The circuits and Hall structures, fabricated in 0.5 um CMOS process, are listed below. - Hall structures with 3 different geometries - CMOS gain amplifier - Current source Monitoring device Measured size (W*H) µm Calculated area(mm 2 ) Layout area (mm 2 ) Hall structures 1 80 * Gain amplifier 180 * Current source 110 * The following figures show the photographs to the devices on the chip. The chip was placed on a microscope stage (Axiotech, Ziess HAL 100). At a magnification of 20-fold (and 5-fold) were recorded on photographs. 75µm 75µm The whole read-out block contain an amplifier which utilizes 180µm X 100µm of die area, instead the current source circuit cover a quarter of the space of the read-out block. 2. Simulation and Measurements Results Chip simulation, verification and comparison Resistance behavior of Hall structures Using the N-well layer from 0.5-micron technology, the N-type silicon-doped film is used for the Hall structures. The layout of the 6 contact microstructure is shown in the next figure. 1 only are listed for Hall structure for 6 contacts

3 The structure dimensions and transport properties of the film were used for the analytical simulations, which were carried out in order to visualize the behaviour versus different parameters (as geometry and Hall voltage V Hall ). The results exhibit a typical behavior and a strong dependence of temperature over a temperature range of K (not showed in the plot). R W 20µm W 25µm W 30µm From the basic equation to Hall plate theory, for very long L >> W and that sense contacts S1, S2 are very small, the corresponding boundary conditions impose that the current density J is collinear with the current axis (Popovic, 2004). Then, if we know the device current I, we can find the Voltage changes from the resistivity changes of the structure. This changing voltage is the Hall voltage that is considered as the output signal from the sensor. The outputs signal we can to pass from the read-out circuit to output pad-chip. In the other hand, it is normal to be expected that a structure with an intermediate geometry (as our geometries) has external characteristics that are somewhere between those of a very long and a very short device. This no-ideal device turns out the Hall voltage as a geometrial correction factor, G err. Geometric correction factor from Hall structures Devices L (m) S (m) G err ( ) Hall 1 50µ 1.8µ 0.92 Hall 2 80µ 1.8µ 0.95 The results of the comparison between Keithley measurements and simulations are showed in the next plot. The dashed line corresponds to Keithley measurements.

4 Gerr Hall 1 Hall For the Hall structure we have three W dimensions (variation of length and control contact was selected to obtain a maximum G err ). Measurements for Hall 1 and Hall 2 presents lowest geometric factor (almost 5% below of the simulation rank). Critical difference between measurements is often for upper width. Therefore, the geometrical factor became worst because the non-perfect current confinement in a finite length Hall device, which is worse for wide devices. The additional structures (not showed in these results) were designed in order to evaluate the complete variations of L/W and S/W. Hall voltage mode of operation The electrical characteristics of a Hall structure operated in the conventional way as the device is exposed to a perpendicular magnetic field (through permanent magnet), is biased via its two sense contacts and the Hall voltage occurs between the control contacts (also named Hall voltage mode) as is showed in the Figure. The symbolic representation of the Hall structure as an electrical equivalent circuit (multiplier type) indicates that the Hall voltage is proportional to the product of current and magnetic induction, (Popovic, 2004). The output voltage of a Hall device is the differential voltage appearing between the sense terminals of the structure. Basic characteristics of the Hall structure, which characterize its performance as a magnetic field to voltage transducer, are: sensitivity, non-linearity, etc. The results of the absolute sensitivity of a Hall 1 structure are showed in the Figure.

5 Voltage over 200mV Linear region Sensitivity We obtain a linear region between 1mT and 3mT over range of Hall voltage between 720mV and 870mV. In particular, the Hall 1 structure was designed for detect an induction field approximated of 1mT. Consideration of real material properties and fabrication technology of the Hall structures, give us a non-idealities in the structure due mainly, to device shape and parasitic effects. CMOS read-out circuit In order to testing the performance of the Hall structures, the integrated circuit is mounted on the side-brazed ceramic package commonly known as a DIP. DIP consists of two rows of leads brazed onto the sides of the ceramic and 24 pins pad. The wire interconnections were made by using a bonding machine. The following figure had shown a detail of the interconnection. Additional design for the sensing circuits was configured as a Wheatstone bridge which is made up to four balanced microstructures. The four microstructures configurated as Wheatstone bridge are connected to two-stage op amp circuit as can seen below (layout and microphotograph at 10-fold of magnification).

6 v i - v i + v i - v i + v out v out Because, the Wheatstone bridge transducers generally produce very small differential output signals, it is often desirable to include the amplification circuitry in the same assembled mechanical package of the Wheatstone bridge circuit. In our case, the differential output signals are connected to the amplification stage in order to provide output signals at useable amplitudes (more than 30 times) through a line connection of a few microns. The solution gives it an improved performance and lower cost to the design. The whole project includes 8 Hall structures and two Wheatstone bridge transducers which have a read-out circuit for each one. The next figure shows the Hall structures interconnected to op amp circuit.

7 The design of read-out circuit includes a current source, which is a cascode current type; and two stages op amp, which has a differential amplifier, source follower circuit and bias polarization.the signal was driven through the op amp s output to off-chip load (an oscilloscope probe). The Lecroy oscilloscope inputs have an input resistance of 10MΩ and an input capacitance of 9.5pF. In addition, DIP packaging and cables add additional capacitance: the packaging alone will add 1-4pF to any on-chip node connected to a pin, and so on. In order to decrease the loading effect, we are used the 10X probe, which increases the input resistance oscilloscope by a factor of 10 gain to 10 attenuation range given by AP033 probe. The main result exhibits an open-loop gain of 50dB. To collect this hard data and to verify the behaviour, we evaluate the test equipment in a crude open-loop measurement system using an interface-bus GPIB Keithley IEEE-48 interfacing card, the digital oscilloscope Lecroy Waverunner, and an arbitrary function generator Agilent (David Hunter, 2007). The functional model of the test system is shown in the next figure. PC GPIB FUNCTION GENERATION TEST CHIP DIGITAL OSCILLOSCOPE Test and characterization equipment 1. Microprobe station J. Micro Technology, model JR-2727 with automatic positioner KRN Lecroy Digital Oscilloscope with 1 GHz with sample at 5GS/s. 3. Arbitrary function generator Agilent 3220A. 4. DC source Agilent E3620A. 5. Programable source Keithley model 2400 with the voltage range of +- uv to 20V, and with 10pA resolution. 6. Gaussimeter lake shore 475 (for Hall structures measurements) The results were the following: Supply voltage Temperature range Input bias current CMRR BW PM SL Output swing 2.5 V - 25 to 80 o C 100µA 80 db 4MHz 45 o 15V/µs 1.5 V p-p Fabrication Specifications The proposed read-out circuit was designed in AMI 0.5µm C5F process, and a 24 pins pad was considered. CMOS read-out circuit will be measured and characterized with a microprobe station. The chip must be mounted in a side-brazed ceramic package DIF. References Popovic, R. S., Hall Effect Devices, Second Edition. Institute of Physics Series in Sensors. IoP Cadence, David Hunter, Ask The Applications Engineer :