Progress in RPC- FEE development

Transcription

1 FEE Progress in RPC- FEE development FEE2 Mircea Ciobanu First FAIR FEE Workshop October -,, 2005 GSI,Darmstadt

2 FEE status (March 2005) ( CBM collaboration meeting March 9-2, ). For the actual design, the connection with the RPC detector is a critical point. The 6 coaxial lines must be impedance matched to detector and FEE ends to prevent reflections. 2. With detector (2 channels) or 2 detectors (64 channels) the beam tests have confirmed a stable and reliable work of the whole system. With 5 detectors (60 channels), the November 2004 FOPI beam tests have shown a system instability and now we work to fix this problem. CAN BE USED A PRIVATE CHIP?.The actual level of performances is obtained with discrete elements and the critical parts are IC top on the Market: MAXIM960(500ps comp),gali -S66(Advanced Silicon Techn.), DC-GHz Amp., 2.7dB NF, 20dB Gain. 4. It is very promising the DIFFERENTIAL pick-up of the signal and the use of an 0 Ohms cheap flat cable Major Changes in Input stage of FEE. 5. Very attractive and effective: The test of NINO chip for ToF-ALICE.

3 FEE status (October 2005). The tests of 60 channels ( RPC super module) during a FOPI beam test in August 2005 have shown that the system stability has been improved. 2. The "crash" in two FEE-plates, caused by a HV sparks in the detector, which destroyed all "first cell amplifiers" (2 pcs) ) imposes a special attention for the improvement of the input protection efficiency. ficiency.. A new RPC-FEE PCB has been designed, around the NINO chip, for comparative tests with our actual solution. 4.. In simulations we try to predict the dependence of time resolution on different detector parameters (signal amplitude,rise time, fall time) or FEE parameters (noise, amplifier bandwidth, gain, threshold level). l).

4 RPC RPC-FEE_NINO FEE_NINO D D C C B B A A IN8+ IN8- IN+ IN- +2V5 OU8+ OU- +2V5 +2V5 BiasN8 BiasN7 BiasN6 BiasN5 BiasN6 BiasN8 BiasN7 ORON +2V5 +2V5 OROP ORP ORN ORP ORN OROP ORON InP8 InP7 InP6 InP5 InP4 InP InP2 InP InN8 InN7 InN6 InN5 InN4 InN InN2 InN InP InP InP5 InN InN InN5 InP7 InN7 InP8 InP6 InP4 InP2 InN2 InN4 InN6 InN8 ORON IN8- IN8+ IN8+ OU8+ OU- IN- IN- IN+ IP6 IN6 IP5 IN5 IP7 IN7 IP8 IN8 IN2 IP2 IP IN IP IN IP4 IN4 +2V5 OutP8 OutN8 OutP7 OutN7 OutP6 OutN6 OutP5 OutN5 OutP4 OutN4 OutP OutN OutP2 OutN2 OutP OutN OR2P OR2N THMinus THPlus OROUTN OROUTP ORINP ORINN GSI Design: Modified: Size: / Page: Designer: Layouter: Gesellschaft für Schwerionenforschung mbh Planckstrasse D-6429 Darmstadt GERMANY RPC - FRONT END ELECTRONICS 4 A4 K:\GSIJOB\RPC-FEE-NINO\RPC-FEE-NINO\RPC-FEE-NINO.DSN <M.Ciobanu> <M.Ciobanu> Thursday, September 22, 2005 GSI Design: Modified: Size: / Page: Designer: Layouter: Gesellschaft für Schwerionenforschung mbh Planckstrasse D-6429 Darmstadt GERMANY RPC - FRONT END ELECTRONICS 4 A4 K:\GSIJOB\RPC-FEE-NINO\RPC-FEE-NINO\RPC-FEE-NINO.DSN <M.Ciobanu> <M.Ciobanu> Thursday, September 22, 2005 GSI Design: Modified: Size: / Page: Designer: Layouter: Gesellschaft für Schwerionenforschung mbh Planckstrasse D-6429 Darmstadt GERMANY RPC - FRONT END ELECTRONICS 4 A4 K:\GSIJOB\RPC-FEE-NINO\RPC-FEE-NINO\RPC-FEE-NINO.DSN <M.Ciobanu> <M.Ciobanu> Thursday, September 22, 2005 LVDS-Receiver C406 0n C406 0n R79 R79 D9 D9 R409 R409 D7 D7 C429 C429 R9 R9 C40 C40 C47 0n C47 0n R57 0R R57 0R R408 R408 D2 D2 C428 0n C428 0n D6 D6 C4 C4 R68 R68 C40 C40 R70 R70 C427 C427 R80 R80 R40 R40 R425 R425 R82 R82 R47 k R47 k R85 R85 C42 C42 J0 Testpin-060 J0 Testpin-060 C422 C422 D D C48 C48 R400 R400 R424 R424 R42 R42 R407 R407 C4 C4 C45 C45 C4 C4 R87 R87 D5 D5 R402 0R R402 0R R94 R94 R95 R95 R42 R42 R62 R62 R20 R20 C42 C42 R64 R64 C42 C42 SUB NC A6 NC B8 NC A2 NC B2 NC A5 NC A4 NC B6 NC A4 NC A42 NC B2 VSSA B VSSA B VSSA B9 VSSA B8 VSSA B7 VSSA B5 VSSA B4 VSSA B VDDA B0 VDDA B29 VDDA B5 VDDA B4 VDD B26 VDD B24 VDD B22 VDD B20 VDD B6 VSS B9 VSS B2 VSS B2 VSS B25 VSS B28 U94B NINOASIC8 U94B NINOASIC8 InP B InN B2 InP2 A44 InN2 A InP4 A4 InN4 A5 InP A2 InN A InP8 B0 InN8 B InP7 A2 InN7 A InP6 A0 InN6 A InP5 A8 InN5 A9 OutP8 B7 OutN8 A22 OutP7 A2 OutN7 A24 OutP6 A25 OutN6 A26 OutP5 A27 OutN5 A28 OutP4 A29 OutN4 A0 OutP A OutN A2 OutP2 A OutN2 A4 OutP A5 OutN B27 THPlus A4 THMinus A40 WOP A9 WON A20 StchOFF A7 HystOFF A6 REXTP A6 REXTN A7 BIASN5 A8 BIASN6 A7 BIASN7 A9 BIASN8 A8 U94A NINOASIC8 U94A NINOASIC8 R404 0R R404 0R C402 u C402 u R9 R9 D0 D0 C44 C44 R4 00k R4 00k R422 R422 D6 D6 Q8 BFR92A Q8 BFR92A R406 R406 C40 0n C40 0n D D D4 D4 C40 C40 R86 R86 R58 5R R58 5R C7 C7 R90 27R R90 27R C409 u C409 u R405 R405 D D R8 R8 R96 R96 R77 R77 D7 D7 R40 k R40 k R74 5.k R74 5.k R69 R69 R4 220R R4 220R R72 00R R72 00R C49 C49 D4 D4 R89 R89 R66 5.k R66 5.k R56 5R R56 5R R67 R67 R8 R8 C405 C405 C46 C46 C424 C424 R6 220R R6 220R D8 D8 R98 R98 C420 C420 D5 D5 Q0 BFR92A Q0 BFR92A R92 R92 R97 R97 R420 R420 R45 200R R45 200R R55 5R R55 5R C408 0n C408 0n R78 R78 R65 220R R65 220R Q BFR92A Q BFR92A C42 0n C42 0n C425 C425 R7 50R R7 50R 2 D2 D2 R88 R88 R49 R49 Q9 BFR92A Q9 BFR92A R40 R40 R42 220R R42 220R C407 C407 C404 C404 R44 00k R44 00k R6 R6 R60 50R R60 50R R59 R59 R46 k R46 k R84 R84 C426 C426 R48 R48 R99 R99 R2 R2 D8 D8

5 RPC-FEE_NINO

6 Basic components of a Timing Channel Typical Errors " WALK " " JITTER" has a minimum for t c = t ra

7 Simulation set-up

8 Noise File Noise Evaluation 000 Noise [uv r.m.s.] 00 Noise at INPUT Noise after First Cell Noise after Second Cell Evaluation Time [ns]

9 "Walk" and Sigma versus: UINP, Amplifier BW, Detector Rise Time Detector signal is Step with variable Rise Time, Noise=uV, THR=00mV Amplifier BW "WALK" [ns] Blue 5MHz Green 50MHz Red.5GHz Black 5GHz SIGMA [ps] Detector signal Rise Time Triangle 0ns Diamond ns Square 00ps Circle 0ps

10 "Walk" and Sigma versus: UINP, Amplifier BW, Noise=uV Detector Rise Time Detector signal is Step with variable Rise Time "WALK" [ns] Detector signal Rise Time Circle 0ps Square 00ps Diamond ns Triangle 0ns SIGMA [ps] Amplifier BW Blue 5MHz Green 50MHz Red.5GHz Black 5GHz

11 "Walk" and Sigma versus: UINP, Amplifier BW, Detector Rise Time "WALK" [ns] Amplifier BW SIGMA [ps] Detector signal Rise Time Blue 5MHz Green 50MHz Red.5GHz Black 5GHz Triangle 0ns Diamond ns Square 00ps Circle 0ps

12 Sigma depend linear to Noise SIGMA versus RN SIGMA [ps] RN [Ohms]

13 Sigma versus UINP and THRESHOLD for two Noise values SIGMA [ns] INPUT NOISE=24uV SIGMA [ps] INPUT NOISE=uV THRESHOLD -20mV -40mV -60mV -80mV -00mV

14 FEE TIME RESOLUTION Low Gain, different Thresholds

15 FEE2 TIME RESOLUTION different Thresholds

16 Sigma versus UINP, THRESHOLD and GAIN GAIN=200 GAIN=00 GAIN=50 INPUT NOISE =24uV GAIN= SIGMA [ps] THRESHOLD -00mV -80mV -60mV -40mV -20mV

17 Sigma versus UINP, THRESHOLD and GAIN SIGMA [ps], FEE Ch MAXIMUM SLOPE [V/ns] SIGMA EVALUATION [ps] THRESHOLD Circle 2mV Square 25mV Diamond 50mV Triangle 00mV 00 BLACK Low GAINl RED High GAIN 00 SQRT(SQR(0.5/SLmax)+SQR()) SQRT(SQR(5/SLmax)+SQR()) 00

18 Dependence to BW and Signal Rise Time "WALK" [ns] SIGMA [ps] 00 0 Signal Rise Time 00 ps 00 ps ns CF [pf] CF [pf]

19 Measurements Charge (p C) FOPI - AvsQ4 2005/05/ Amplitude (mv) Charge (p C) FOPI - AvsQ6 2005/05/ Amplitude (mv) F a ll Time(ps) F a ll Time(ps) Amplitude(mV) Amplitude(mV) F a ll Time ( ps) F a ll Time ( ps) Charge (pc) Charge (pc) A nzahl E le ktronen A nzahl Ele ktronen Ladung (pc) Ladung (pc)

20 Comparative Dependence to BW and Signal Rise Time for : Resistive Plate Chamber, PC and SC Diamonds SIGMA [ps] Signal: Triangle, TR=TF SIGMA [ps] Signal: Triangle, TF=ns SIGMA [ps] Signal: Trapez, 4ns, TR=TF 00 UINP=2mV UTHR=60mV Signal : TR 0ps 00ps 00ps ns C F [pf] C F [pf] CF [pf]

21 We acknowledge the support of the European Community-Research Infrastructure Activity under the FP6 "Structuring the European n Research Area" programme (HadronPhysics,contract number RII-CT CT ).