VLSI LAB MANUAL (15ECL77) PESU-Electronic city VLSI LAB MANUAL 2018

Transcription

1 PESU-Electronic city Department of Electronics and Communication 1 km before Electronic City, Hosur road, Bangalore VLSI LAB MANUAL (15ECL77) 1 Dept. Electronics and Communication, PESU- Electronic city,

2 I. VLSI DESIGN FLOW AND THE TOOLS USED IN CADENCE II. III. PART A: Digital Simulation PROCEDURE FOR CREATING DIGITAL SIMULATION USING VERILOG AND CADENCE DIGITAL TOOL. Experiment1: Inverter Experiment2: Buffer Experiment3: Transmission Gates(TG) Experiment4: Logic Gates AND,OR,NAND,NOR,XOR,XNOR Experiment5: Flip Flops JK,MS,SR,D,T Experiment6: Synchronous Counter Experiment7: Asynchronous Counter Experiment8: Parallel Adder Experiment 9: Serial Adder PART B: Analog Design PART B[1] : Schematic Simulation PROCEDURE FOR CREATING THE SCHEMATIC SIMULATION Experiment 1(a): Experiment 2(a): Experiment 3(a): Experiment 4(a): Experiment 5(a): Experiment 6(a): Inverter Schematic and test Cell View Common Source Amplifier Schematic and test Cell View Common Drain Amplifier Schematic and test Cell View Differential Amplifier Schematic and test Cell View Operational Amplifier Schematic and test Cell View R-2R DAC Schematic and test Cell View PART B[1] : Layout Simulation Layout Design Rules PROCEDURE FOR CREATING THE LAYOUT AND SIMULATING Experiment 1(b): Inverter Layout Design Experiment 2(b): Common Source Amplifier Layout Design Experiment 3(b): Common Drain Amplifier Layout Design Experiment 4(b): Differential Amplifier Layout Design Experiment 5(b): Operational Amplifier Layout Design IV. VLSI Viva Questions 2 Dept. Electronics and Communication, PESU- Electronic city,

3 1) VLSI DESIGN FLOW AND TOOLS USED IN CADENCE PDK stands for Process Design Kit. A PDK contains the process technology and needed information to do device-level design in the Cadence DFII environment. 3 Dept. Electronics and Communication, PESU- Electronic city,

4 PART - A 4 Dept. Electronics and Communication, PESU- Electronic city,

5 2) PART A: Digital Simulation PROCEDURE FOR CREATING DIGITAL SIMULATION USING VERILOG AND CADENCE DIGITAL TOOL. Open Terminal Window and use the following commands ü #csh ü #source cshrc ü #ls (ls can be skipped if you know which is the next directory to go)-this will list out the directories like Cadence_digital_labs cadence_analog_labs then ü #cd Cadence_digital_labs/Workarea ü Crate a directory for the experiment presently executed by using following command. mkdir directory name Ex: mkdir Inverter ü Create the module file/s(verilog module ): Vi modulename.v Ex: vi inverter.v The file name can be changes with respect to the experiments. ü A Text Editor window will open.to enter text in editor window PRESS I and then type the program and exit to terminal window by save and exit command --- Press Esc :wq! ü Repeat the steps for test bench by following above TWO steps with different file name. Ex: vi test_inverter.v ü Now to compile Ø Compile the module file/s with message option: ncvlog modulefilename.v-messages Ex: ncvloginverter.v messages (RTL code compilation) Ø Compile the test bench file with message option: ncvlog testbenchname.v-message 5 Dept. Electronics and Communication, PESU- Electronic city,

6 Ex: ncvlog inverter.v messages Note: Check out for error and warnings. If any then go back to text editor and edit and the compile ü Elaborate the top level design(test bench) Ø ncelab toplevelmodulename-access+rwc-message Top level module name to be elaborated is the name of test bench module ncelab inv_test access +rwc messages ü Simulate the top level design Ø Non GUI mode ncsim toplevelmodulename ncsim inv_test Ø In GUI Mode Ncsim toplevelmodulename-gui ncsim inv_test -gui Now a console and Design Browser windows of Simvision are opened. In the Design Browser Window,Select the toplevelmodulename scope(ex:inv_test) and select all the signals displayed and click on the waveform button in the toolbar. Waveform Window opens.press run to run the simulation for a time period specified in the time field. 6 Dept. Electronics and Communication, PESU- Electronic city,

7 Synthesize procedure using Cadence Tool ü # cd csh ü #source cshrc ü # cd Cadence_digital_labs/Workare ü #cd rclabs --- for digital synthesis enter into rclabs ü #cd rtl --- The verilog file to be sythesizd must be copied into this directory form the directory where the simulated code is present. i.e from your directory created under Workarea. ü cd Come back rclabs directory ü #cd work --- Get into work directory under rclabs to synthesize the hdl file present in rtl directory. ü #rc gui --- this would start a GUI window for synthesizing. ü rc:/>set_attr lib_search_path../library ü rc:/>set_attribute hdl_search_path../rtl ü rc:/>set_attr library slow_highvt.lib (if this step gives an error then close the rc window by closing the GUI window and then type the following) #cd / #cd root/cadence_digital_labs #tar -xzvf Cadence_digital_labs.tar.gz (this should work and then continue with RC labs again) ü rc:/>read_hdl {file_name.v} Ex:read_hdl {ff1.v} (ff1.v must be in rtl directory of rclabs) ü rc:/>read_sdc../constraints_filename.g (if any constraints file they must be read here) ü rc:/>elaborate ü rc:/>synthesize -to_mapped -effort medium ---now you must be able to see the schematic else go to file and click on update GUI in GUI window. ü rc:/>write > any_name.v ü rc:>report timing - This gives the timing reports like delay, propagation so on ü rc:/>report power - This gives the power dissipation report static and dynamic power dissipation ü rc:/>report area - This gives no of cell used and the area used for the calls. 7 Dept. Electronics and Communication, PESU- Electronic city,

8 1. INVERTER Step by step procedure to be followed for all the digital ASIC designs: Step 1: Write the RTL code (eg. inverter.v) and testbench code (eg. inverter_tb.v) in rtl directory: // Verilog Code: module inverter(b, a); input a; output b; assign b = ~a; endmodule //Test bench module inv_tb; wire b; reg a; inverter i1(b,a); initial begin a=1 b0; #10 a=1 b1; #10 a=1 b x; #10 a= 1 bz; end endmodule Step 2: Write the constraints in work directory. Constraints: set_input_delay -max 1.0 [get_ports "a"] set_output_delay -max 1.0 [get_ports "b"] Step 3: Simulation tool is invoked in rtl directory by the command : nclaunch -64 & Step 4: Once the tool is invoked, compile the rtl code and testbench code as shown in step 4 & step 5. Step 5: Compiling testbench code (eg. inverter_tb.v) 8 Dept. Electronics and Communication, PESU- Electronic city,

9 Step 6: Elaborate the RTL code. Step 7: Elaborate the testbench code Step 8: Simulate the testbench code. 9 Dept. Electronics and Communication, PESU- Electronic city,

10 Output Waveform: 2. BUFFER //Verilog code //Test bench module buffer(b,a,en); input a,en; output b; reg b; or en) begin if (en==1) b=a; else b=1 bz; end endmodule module buffertest; reg a,en; wire b; buffer b1(b,a,en); initial begin en=1 b1; a=1'b0; #10 a=1'b1; #10 a=1'b0; #10 a=1'bx; #10 a=1'bz; #10 a=1'b0; end 10 Dept. Electronics and Communication, PESU- Electronic city,

11 Constraints: set_input_delay -max 1.0 [get_ports "a"] set_input_delay -max 1.0 [get_ports "en"] set_output_delay -max 1.0 [get_ports "b"] endmodule Output Waveform: //Verilog code module trans(b, a, cntrl1, cntrl2); input a; input cntrl1,cntrl2; output b; reg b; (a or cntrl1 or cntrl2) begin if (cntrl1 = = cntrl2) b = 1 bx; else if (cntrl1 = = 0 & cntrl2 = = 1) b = a; 3. TRANSMISSION GATE //Test bench module trans_tb; wire b ; reg a ; reg cntrl1,cntrl2; trans t1(b, a, cntrl1, cntrl2); initial begin a= 1'b0 ; cntrl1 = 1'b0 ; cntrl2 = 1'b0 ; #10 a= 1'b0 ; cntrl1 = 1'b0 ; cntrl2 = 1'b1; #10 a= 1'b0 ; cntrl1 = 1'b1 ; cntrl2 = 1'b0; #10 a= 1'b0 ; cntrl1 = 1'b1 ; cntrl2 = 1'b1; 11 Dept. Electronics and Communication, PESU- Electronic city,

12 else end endmodule b = 1'bz; Constraints: set_input_delay -max 1.0 [get_ports "a"] set_input_delay -max 1.0 [get_ports "cntrl1"] set_input_delay -max 1.0 [get_ports "cntrl2"] set_output_delay -max 1.0 [get_ports "b"] #10 a= 1'b1 ; cntrl1 = 1'b0 ; cntrl2 = 1'b0; #10 a= 1'b1 ; cntrl1 = 1'b0 ; cntrl2 = 1'b1; #10 a= 1'b1 ; cntrl1 = 1'b1 ; cntrl2 = 1'b0; #10 a= 1'b1; cntrl1 = 1'b1 ; cntrl2 = 1'b1; end endmodule Output Waveform: 4. LOGIC GATES 12 Dept. Electronics and Communication, PESU- Electronic city,

13 //Verilog code module logic(f1,f2,f3,f4,f5,f6,a,b); input a,b; output f1,f2,f3,f4,f5,f6; assign f1=a&b; assign f2=a b; assign f3=~a; assign f4=~(a b); assign f5=~(a&b); assign f6=a^b; endmodule Constraints: set_input_delay -max 1.0 [get_ports "a"] set_input_delay -max 1.0 [get_ports "b"] set_output_delay -max 1.0 [get_ports "f1"] set_output_delay -max 1.0 [get_ports "f2"] set_output_delay -max 1.0 [get_ports "f3"] set_output_delay -max 1.0 [get_ports "f4"] set_output_delay -max 1.0 [get_ports "f5"] set_output_delay -max 1.0 [get_ports "f6"] //Test bench module logictest; reg a,b; wire f1,f2,f3,f4,f5,f6; logic l1(f1,f2,f3,f4,f5,f6,a,b); initial begin a=1'b0; b=1'b0; #10 b=1'b1; #10 a=1'b1; b=1'b0; #10 b=1'b1; #10; end endmodule 13 Dept. Electronics and Communication, PESU- Electronic city,

14 Output Waveform: a) SR FLIP-FLOP //Verilog code module srff(q,qb,s,r,clk,rst); input s,r,clk,rst; output q,qb; reg [1:0] sr; reg q,qb; clk) begin 5. FLIP-FLOPS //Test bench module srfftest; reg s,r,clk,rst; wire q,qb; srff s1(q,qb, s,r,clk,rst); initial clk=1'b0; always 14 Dept. Electronics and Communication, PESU- Electronic city,

15 if (rst ==1) q=1 b0; else sr={s,r}; case(sr) 2'b00:q=q; 2'b01:q=1'b0; 2'b10:q=1'b1; 2'b11:q=1'bx; endcase qb=~q; end endmodule create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"] set_clock_transition -rise 0.1 [get_clocks "clk"] set_clock_transition -fall 0.1 [get_clocks "clk"] set_input_delay -max 1.0 [get_ports "rst"] -clock [get_clocks "clk"] set_input_delay -max 1.0 [get_ports "s"] -clock [get_clocks "clk"] set_input_delay -max 1.0 [get_ports "r"] -clock [get_clocks "clk"] set_output_delay -max 1.0 [get_ports "q"] -clock [get_clocks "clk"] set_output_delay -max 1.0 [get_ports "qb"] -clock [get_clocks "clk"] Output Waveform: #5 clk=~clk; initial begin rst = 1 b1; #10 rst = 1 b0; s=1'b0;r=1'b1; #10 s=1'b1;r=1'b0; #15 s=1'b0;r=1'b0; #20 s=1'b1;r=1'b1; #20; end endmodule b) D FLIP-FLOP 15 Dept. Electronics and Communication, PESU- Electronic city,

16 Constraints: create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"] //Verilog code //Test bench module dff(d,clk,rst,q,qb); input d,clk,rst; output q,qb; reg q,qb; clk) begin if (rst ==1) q=1 b0; else q=d; qb=~d; end endmodule module dfftest; reg clk,d,rst; wire q,qb; dff d1(d,clk,rst,q,qb); initial clk = 1'b0; always #5clk=~clk; initial begin rst=1 b1; #10 rst = 1 b0;d=1'b0; #10d=1'b1; end endmodule set_clock_transition -rise 0.1 [get_clocks "clk"] set_clock_transition -fall 0.1 [get_clocks "clk"] set_input_delay -max 1.0 [get_ports "rst"] -clock [get_clocks "clk"] set_input_delay -max 1.0 [get_ports "d"] -clock [get_clocks "clk"] set_output_delay -max 1.0 [get_ports "q"] -clock [get_clocks "clk"] set_output_delay -max 1.0 [get_ports "qb"] -clock [get_clocks "clk"] Output Waveform: 16 Dept. Electronics and Communication, PESU- Electronic city,

17 c) JK FLIP-FLOP //Verilog code //Test bench module jkff(q,qbar,j.k,clk,rst); input j,k,clk,rst; output q,qbar; reg q,qbar; reg [1:0] jk; clk) begin if(rst) q = 1 b0; else jk = {j,k} case (jk) 2 b00: q=q; 2 b01: q=1 b0; 2 b10: q=1 b1; 2 b11: q=~q; endcase assign qbar =~q; end endmodule Constraints: create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"] set_clock_transition -rise 0.1 [get_clocks "clk"] set_clock_transition -fall 0.1 [get_clocks "clk"] set_input_delay -max 1.0 [get_ports "j"] -clock [get_clocks "clk"] set_input_delay -max 1.0 [get_ports "k"] -clock [get_clocks "clk"] module jkfftest; reg j,k,clk,rst; wire q,qbar; jkff jk1(q,qbar,j,k,clk,rst); initial clk=1'b0; always #5 clk=~clk; initial begin rst = 1 b1; #10 rst = 1 b0; j=1 b0;k=1 b0; #10 k=1 b1; #10 j=1 b1; k=1 b0; #10 k=1b1; end endmodule 17 Dept. Electronics and Communication, PESU- Electronic city,

18 set_input_delay -max 1.0 [get_ports "rst"] -clock [get_clocks "clk"] set_output_delay -max 1.0 [get_ports "q"] -clock [get_clocks "clk"] set_output_delay -max 1.0 [get_ports "qbar"] -clock [get_clocks "clk"] Output Waveform: d) Master Slave JK FLIP-FLOP //Verilog code module ms_jkff (qs,qsb,qm,qmb,j,k,clk,rst); output qs, qsb; inout qm,qmb; input j,k,clk,rst; wire clkbar; assign clkbar = ~ clk; jkff jk1 (qm,qmb,j,k,clk,rst); jkff jk2 (qs,qsb,qm,qmb,clkbar,rst); endmodule Constraints: create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"] set_clock_transition -rise 0.1 [get_clocks "clk"] set_clock_transition -fall 0.1 [get_clocks "clk"] set_input_delay -max 1.0 [get_ports rst"] -clock [get_clocks "clk"] set_input_delay -max 1.0 [get_ports "j"] -clock [get_clocks "clk"] //Test bench module ms_jkff_test; reg j,k,clk,rst; wire qs,qsb,qm,qmb; ms_jkff ms1(qs,qsb,qm,qmb,j,k,clk,rst); initial clk = 1 b0; always #10 clk = ~clk; initial begin rst = 1 b1; j = 1 b0; k= 1 b0; #15 rst = 1 b0; #25 k = 1 b1; #25 j = 1 b1; k= 1 b0; #25 k= 1 b1; end endmodule 18 Dept. Electronics and Communication, PESU- Electronic city,

19 set_input_delay -max 1.0 [get_ports "k"] -clock [get_clocks "clk"] set_output_delay -max 1.0 [get_ports "qs"] -clock [get_clocks "clk"] set_output_delay -max 1.0 [get_ports "qsb"] -clock [get_clocks "clk"] Output Waveform: e) T FLIP-FLOP //Verilog code //Test bench module tff(q,qb, rst,clk,t); input rst,clk,t; output q,qb; reg q,qb; clk) begin if (rst ==1) q=1 b0; else if (t==0) q=q; else q=~q; qb=~q; end endmodule Constraints module tfftest; reg rst,clk,t; wire q,qb; tff t1(q,qb,rst, clk,t); initial clk=1'b0; always #5 clk=~clk; initial begin rst = 1 b1; #10 rst = 1 b0;t=1'b0; #10 t=1'b1; end endmodule 19 Dept. Electronics and Communication, PESU- Electronic city,

20 create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"] set_clock_transition -rise 0.1 [get_clocks "clk"] set_clock_transition -fall 0.1 [get_clocks "clk"] set_input_delay -max 1.0 [get_ports "rst"] -clock [get_clocks "clk"] set_input_delay -max 1.0 [get_ports "t"] -clock [get_clocks "clk"] set_output_delay -max 1.0 [get_ports "q"] -clock [get_clocks "clk"] set_output_delay -max 1.0 [get_ports "qb"] -clock [get_clocks "clk"] Output Waveform: a) PARALLEL ADDER: 6. ADDERS 20 Dept. Electronics and Communication, PESU- Electronic city,

21 //Verilog code // Full Adder module fa(a,b,cin,sum,cout); input a,b,cin; output sum, cout; assign sum=(a^b)^cin; assign cout=((a&b) (b&cin) (cin&a)); endmodule // Parallel Adder module pa(a,b,cin,s,cout); input [3:0]a,b; input cin; output [3:0]s; output cout; wire [2:0]c; fa f1(a[0],b[0],cin,s[0],c[0]); fa f2(a[1],b[1],c[0],s[1],c[1]); fa f3(a[2],b[2],c[1],s[2],c[2]); fa f4(a[3],b[3],c[2],s[3],cout); endmodule //Test bench module patest; reg [3:0]a,b; reg cin=1'b0; wire cout; wire [3:0]s; pa p1(a,b,cin,s,cout); initial begin a=4'b0; b=4'b0; #10 a=4'd1;b=4'd2; #20 a=4'd9; b=4'd3; #10 a=4'd9; b=4'd7; #10; end endmodule Constraints: set_input_delay -max 1.0[get_ports "a"] set_input_delay -max 1.0[get_ports "b"] set_input_delay -max 1.0[get_ports "cin"] set_output_delay -max 1.0[get_ports "s"] set_output_delay -max 1.0[get_ports "cout"] Output Waveform: 21 Dept. Electronics and Communication, PESU- Electronic city,

22 b) SERIAL ADDER //Verilog code module serial_adder(sum,clk,load,a,b); input clk,load; input[3:0] a,b; output[4:0] sum; reg[3:0] ina,inb; reg [4:0] org; wire so,co; clk) begin if(load) begin ina=a; inb = b; org = 5 b0; end else begin ina = {1 b0,ina[3:1]}; inb = {1 b0,inb[3:1]}; org[4] = co; org[3:0] = {so,org [3:1]}; end end assign so = ina[0]^inb [0]^org[4]; assign co = (ina[0] & inb[0] ( inb[0] & org[4]) org[4] & ina[0]); assign sum = org; endmodule Constraints: create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"] set_clock_transition -rise 0.1 [get_clocks "clk"] set_clock_transition -fall 0.1 [get_clocks "clk"] set_clock_uncertainty 1.0 [get_ports "clk"] set_input_delay -max 1.0 [get_ports load"] -clock [get_clocks "clk"] set_input_delay -max 1.0 [get_ports "a"] -clock [get_clocks "clk"] set_input_delay -max 1.0 [get_ports "b"] -clock [get_clocks "clk"] set_output_delay -max 1.0 [get_ports "sum"] -clock [get_clocks "clk"] Output Waveform: //Test bench module serialtest; reg clk,load; reg[3:0] a,b; wire[4:0] sum; serial_adder s1(sum,clk,load,a,b); initial clk=1'b0; always #5 clk=~clk; initial begin load=1'b1; a = 4 d9; b = 4 d8; #10 load = 1 b0; #30 ; end endmodule 22 Dept. Electronics and Communication, PESU- Electronic city,

23 a) Asynchronous counter //Verilog code module async(clk,q); input clk; output q; reg [3:0]q; initial q=4'b1111; clk) q[0]=~q[0]; q[0]) q[1]=~q[1]; q[1]) q[2]=~q[2]; q[2]) q[3]=~q[3]; endmodule 7. COUNTERS //Test bench module asynctest; reg clk; wire [3:0]q; async a1(clk,q); initial begin clk=1'b0; end always #5 clk=~clk; endmodule Constraints: create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"] set_clock_transition -rise 0.1 [get_clocks "clk"] set_clock_transition -fall 0.1 [get_clocks "clk"] set_clock_uncertainty 1.0 [get_ports "clk"] set_output_delay -max 1.0 [get_ports "q"] -clock [get_clocks "clk"] Output Waveform: 23 Dept. Electronics and Communication, PESU- Electronic city,

24 b) SYNCHRONOUS COUNTER //Verilog code module sync(clk,reset,q); input clk,reset; output [3:0]q; reg [3:0]q; clk) if(reset) q=4'b0; else q=q+1; endmodule //Test bench module synctest; reg clk,reset; wire [3:0]q; sync sc1(clk,reset,q); initial begin clk=1'b0; end always #5 clk=~clk; initial begin reset=1'b1; #10 reset=1'b0; end endmodule Constraints: create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"] set_clock_transition -rise 0.1 [get_clocks "clk"] set_clock_transition -fall 0.1 [get_clocks "clk"] set_clock_uncertainty 1.0 [get_ports "clk"] set_input_delay -max 1.0 [get_ports "reset"] -clock [get_clocks "clk"] 24 Dept. Electronics and Communication, PESU- Electronic city,

25 set_output_delay -max 1.0 [get_ports "q"] -clock [get_clocks "clk"] Output Waveform: 25 Dept. Electronics and Communication, PESU- Electronic city,

26 PART B 26 Dept. Electronics and Communication, PESU- Electronic city,

27 3) PART B[1]: SCHEMATIC SIMULATION PROCEDURE FOR CREATING THE SCHEMATIC SIMULATION I. Commands to get into Cadence 1. Right Click and open the terminal window 2. Type the following commands as follows and press enter. i) csh ii) source cshrc iii) ls shows the directories check for existence of cadence_analog_labs_613.if not found inform the system admin else go to next step iv) cd cadence_analog_labs_613 v) virtuoso & II. Procedure for Schematic simulation using Cadence 1. Now two windows must open i)virtuoso/command interpreter window ii) Whats New 2. Close the 2 nd window 3. Use 1 st window i.e virtuoso window(ciw) for further processing. i) Create a New Library ii) Create Schematic Cell view. iii) Create the Symbol for schematic Cell view. iv) Create the test Cell view. v) Analog simulation by spectre i) Procedure for Creating New Library. a. File New Library b. Name : Give name for ur library Ex: VLSILAB c. Enable Attach to an existing technology library, Click OK d. Attach the library to the technology library gpdk180.click OK ii) Create Schematic Cell view. a. Go to 1 st window i.e virtuoso(ciw) b. File-New-Cell view 27 Dept. Electronics and Communication, PESU- Electronic city,

28 c. Setup the new file form Library: Select the one you a created. Cell : Give the experiment name Ex: Inverter View: Schematic Type: Schematic press OK d. Add the required components from the libraries and make the connections. 1. Go to instance fixed menu or use shortcut key I from keypad to go instances 2. Click on browse. This opens the library browser 3. Now select the appropriate library for components like Gpdk nmos, pmos Analog library Vdd, Gnd, Vcc, Vpulse, Vsin 4. Make the connections by using fixed narrow wire key 5. Click Check and Save button iii) Creating the Symbol for schematic Cell view a. In the schematic window, execute Crate Cell view From Cell view The cell view from cell view window appears Check Lib Name, Cell Name, From View name must be schematic Press ok b. Now Symbol generation form appears. Click Ok If No changes required c. A new window with with default symbol is created. d. Edit the symbol if you want to give actual symbol shape else continue. i. Execute Create-Cell view-from cell view ii. Library Name and Cell Name must be same which you have used for schematic. Press OK iii. Check for the position of pin side.prss OK iv. Edit for the shape by Create-Shape-Choose required options to edit. iv) Creating the new test cell view a. Go to CIW window, Execute File-New-Cell view b. Setup the new file form 28 Dept. Electronics and Communication, PESU- Electronic city,

29 Library: Select the one you a created. Cell: Cell name must be different from the name used in schematic cell view. Ex: Inverter_test View: Schematic Type: Schematic press OK c. Follow the step 3(ii) d to make the required connections v) Analog simulation by SPECTRE. a. In test cell view window Launch ADE L(Analog Design Environment) b. Execute Setup Simulation/directory/Host A new window opens c. Set the simulation window to spectre and click ok d. Execute Setup-Model Library. Anew window opens, Check of gpdk.scs as lib and section type as stat then press OK. e. Execute Analysis Choose. A window opens. f. Select the type and set the specifications and press OK g. Execute Output s to be plotted Select on Schematic h. Then Select the INPUT WIRE(Vin ) and OUTPUT WIRE(Vout) from your test Schematic using mouse i. Execute Simulation -- Net list and Run 29 Dept. Electronics and Communication, PESU- Electronic city,

30 Experiment 1(a): Inverter Schematic Cell View Specifications: nmos à NM0 à W=2u L=.180U & NM1à W=2U L=.180U Input Pins à Vdd,Vss,Vin,Vbias Output pin à Vout 30 Dept. Electronics and Communication, PESU- Electronic city,

31 Specifications: Vpulse à V1 = 0 Vdd = 1.8 V2 = 1 td = 0,tr=tf=1 n, ton= 10n,T=20n Simulation Settings Setup for transient analysis: 1. Stop time = Setup for D.C analysis 1. Component to be selected in schematic is for d.c analysis 2. Start = -5 Stop = 5 resp. Setup for A.C analysis 1. Turn on Frequency button 2. In sweep range section Start stop 3. Select point per decade = Check enables and apply Expected Waveform: Transient analysis 31 Dept. Electronics and Communication, PESU- Electronic city,

32 DC Analysis Experiment 2(a): Common source Amplifier schematic Cell view The common-source (CS) amplifier may be viewed as a transconductance amplifier or as a voltage amplifier. As a transconductance amplifier, the input voltage is seen as modulating the current going to the load. As a voltage amplifier, input voltage modulates the amount of current flowing through the FET, changing the voltage across the output resistance according to Ohm's law. The easiest way to tell if a FET is common source is to examine where the signal enters, and leaves. The remaining terminal is what is known as "common". In this example, the signal enters the gate, and exits the drain. The only terminal remaining is the source. This is a common-source FET circuit. 32 Dept. Electronics and Communication, PESU- Electronic city,

33 Specifications: nmos à PM0 à W=50u L=1U Pmos à NM0à W=10U L01U Input Pins à Vdd,Vss,Vin,Vbias Output pin à Vout Common source Amplifier schematic test Cellview Specifications: Vsin à a.c magnitude = 1 Vdd = 2.5 d.c voltage = 0 Vss = -2.5 offset voltage = 0 Vbias = 2.5 amplitude =5m frequency =1K 33 Dept. Electronics and Communication, PESU- Electronic city,

34 Simulation Settings Setup for transient analysis: 2. Stop time = 5m Setup for D.C analysis 3. Component to be selected in schematic is Vsin for d.c analysis 4. Start = -5 Stop = 5 resp. Setup for A.C analysis 4. Turn on Frequency button 5. In sweep range section Start 7 stop 150 to 100M 6. Select point per decade = 20 Check enables and apply 34 Dept. Electronics and Communication, PESU- Electronic city,

35 Expected Waveform: Transient analysis DC Analysis AC Analysis- Frequency 35 Dept. Electronics and Communication, PESU- Electronic city,

36 Experiment 3(a): Common drain amplifier schematic Cell view A common-drain amplifier, also known as a source follower, is one of three basic single-stage field effect transistor (FET) amplifier topologies, typically used as a voltage buffer. In this circuit the gate terminal of the transistor serves as the input, the source is the output, and the drain is common to both (input and output), hence its name. The analogous bipolar junction transistor circuit is the common-collector amplifier. In addition, this circuit is used to transform impedances. For example, the Thévenin resistance of a combination of a voltage follower driven by a voltage source with high Thévenin resistance is reduced to only the output resistance of the voltage follower, a small resistance. That resistance reduction makes the combination a more ideal voltage source. Conversely, a voltage follower inserted between a small load resistance and a driving stage presents an infinite load to the driving stage, an advantage in coupling a voltage signal to a small load. 36 Dept. Electronics and Communication, PESU- Electronic city,

37 Specifications: nmos à NM0 à W=50u L=1U & NM1à W=10U L=1U Input Pins à Vdd,Vss,Vin,Vbias Output pin à Vout Common drain amplifier test cellview Specifications: Vsin à a.c magnitude = 1 Vdd = 2.5 d.c voltage = 0 Vss = -2.5 offset voltage = 0 Vbias = 2.5 amplitude =5m frequency =1K 37 Dept. Electronics and Communication, PESU- Electronic city,

38 Simulation Settings Setup for transient analysis: 1. Stop time = 5m Setup for D.C analysis 1. Component to be selected in schematic is Vsin for d.c analysis 2. Start = -5 Stop = 5 resp. Setup for A.C analysis 1. Turn on Frequency button 2. In sweep range section Start 7 stop 150 to 100M 3. Select point per decade = 20 Check enables and apply 38 Dept. Electronics and Communication, PESU- Electronic city,

39 Expected Waveform: Transient analysis DC Analysis AC Analysis- Frequency 39 Dept. Electronics and Communication, PESU- Electronic city,

40 Experiment 4(a): Differential Amplifier schematic Cell view Specifications: nmos à NM0&NM1 à W=3u L=1U, NM2,NM3 à 4.5U L=1U Pmos à PM0 & PM1à W=15U L=1U Input Pins à V1,V2,Idc Output pin à Vout Bidrectional pins à Vdd,Vss Differential Amplifier schematic test Cellview 40 Dept. Electronics and Communication, PESU- Electronic city,

41 Specifications: Vsin à a.c magnitude = 1 Vdd = 2.5 amplitude =5m Vss = -2.5 frequency =1K Idc = d.c.current=30u Simulation Settings Setup for transient analysis: 3. Stop time = 5m Setup for D.C analysis 5. Component to be selected in schematic is for d.c analysis 6. Start = -5 Stop = 5 resp. Setup for A.C analysis 7. Turn on Frequency button 8. In sweep range section Start stop 9. Select point per decade = Check enables and apply Expected Waveform: 41 Dept. Electronics and Communication, PESU- Electronic city,

42 Experiment 5(a) : OPAMP schematic Cell view Specifications: Diff_Amplifier à From your library Cs_amplifier à From your library Input Pins à Vinv,Vnoninv,Id.c,Vdd,Vss 42 Dept. Electronics and Communication, PESU- Electronic city, \

43 Output pin à Vout OPAMP schematic test Cell view Specifications: Vsin à a.c magnitude = 1 Vdd = 5 d.c voltage = 0 Vss = -2.5 offset voltage = 0 Idc = d.c current=30 u amplitude =0.5m frequency =1K Simulation Settings Setup for transient analysis: 4. Stop time = Setup for D.C analysis 7. Component to be selected in schematic is for d.c analysis 8. Start = -5 Stop = 5 resp. Setup for A.C analysis 10. Turn on Frequency button 11. In sweep range section Start stop 12. Select point per decade = Check enables and apply Expected Waveform: 43 Dept. Electronics and Communication, PESU- Electronic city,

44 Experiment 6(a) : R-2R DAC schematic Cell view 44 Dept. Electronics and Communication, PESU- Electronic city,

45 Table for component building: Lib Name Cell Name Properties gpdk180 polymer R=2K and 1K analog lib Idc,gnd idc=30u My.Library op-amp symbol D0,D1,D2,D3 Input pins Vout-output pin Vdd and Gnd Input pins R-2R DAC Test Cellview 45 Dept. Electronics and Communication, PESU- Electronic city,

46 Table for component building: Lib Name Cell Name Properties analog lib Vpulse V0: V1=0V V2=2 Total period(t)=10n Pulse width(ton)=5n V1: V1=0V V2=2 Total period(t)=20n Pulse width(ton)=10n V2: V1=0V V2=2 Total period(t)=40n Pulse width(ton)=20n V3: V1=0V V2=2 Total period(t)=80n Pulse width(ton)=40n Vdc,gnd Vdd=2 Vss=-2 My.Library R-2R DAC symbol Simulation Settings Setup for transient analysis: 5. Stop time = Setup for D.C analysis 9. Component to be selected in schematic is for d.c analysis 10. Start = -5 Stop = 5 resp. Setup for A.C analysis 13. Turn on Frequency button 14. In sweep range section Start stop 15. Select point per decade = Check enables and apply 46 Dept. Electronics and Communication, PESU- Electronic city,

47 Output Waveform: 47 Dept. Electronics and Communication, PESU- Electronic city,

48 48 Dept. Electronics and Communication, PESU- Electronic city,

49 PART B[2]: LAYOUT DESIGNING I) Layout Design Rules 0A 0B 1A 1B 1C 1D 1E 1F 2A 2B 2C 2D 3A 3B 3C 3D 4A 4B 4C 4D 4E 5A 5B 5C 5D 5E Minimum NBURIED width 1.0um Minimum NBURIED space 1.0um Minimum NWELL width 1.0um Minimum NWELL space 1.0um Minimum NBURIED enclosure of NWELL 0.3um Minimum PWELL width 1.0um Minimum PWELL space 1.0um Minimum NBURIED enclosure of PWELL 0.3um Minimum OXIDE width 0.4um Minimum OXIDE space 0.3um Minimum NWELL enclosure of OXIDE 0.5um Minimum NWELL to OXIDE space 0.5um Minimum NIMP width 0.4um Minimum NIMP space 0.4um Minimum NIMP enclosure of OXIDE 0.2um Minimum NBURIED enclosure of NIMP 0.6um Minimum PIMP width 0.4um Minimum PIMP space 0.4um Minimum PIMP enclosure of OXIDE 0.2um Minimum NBURIED enclosure of PIMP 0.6um PIMP and NIMP cannot overlap Minimum POLY width 0.18um Minimum POLY space 0.3um Minimum POLY extension beyond OXIDE (poly endcap) 0.2um Minimum OXIDE extensions beyond gate POLY 0.4um Minimum Poly to OXIDE spacing 0.2um 49 Dept. Electronics and Communication, PESU- Electronic city,

50 6A 6B 6C 6D 6E 6F 6G 6H 7A 7B 7C 8A 8B 8C 9A 9B 9C 10A 10B 10C 11A 11B 11C 11D 12A 12B 12C 12D Minimum and maximum width of CONT 0.2um Minimum CONT space 0.2um Minimum OXIDE enclosure of CONT 0.2um Minimum POLY enclosure of CONT 0.2um Minimum POLY to CONT space 0.2um Minimum NIMP enclosure of CONT 0.2um Minimum PIMP enclosure of CONT 0.2um Minimum CONT to Oxide space 0.2um Minimum METAL1 width 0.3um Minimum METAL1 space 0.3um Minimum METAL1 enclosure of CONT 0.1um Minimum and maximum width of VIA1 0.2um Minimum VIA1 space 0.3um Minimum METAL1 enclosure of VIA1 0.1um Minimum METAL2 width 0.3um Minimum METAL2 space 0.3um Minimum METAL2 enclosure of VIA1 0.1um Minimum and maximum width of VIA2 0.2um Minimum VIA2 space 0.3um Minimum METAL2 enclosure of VIA2 0.1um Minimum METAL3 width 0.3um Minimum METAL3 space 0.3um Minimum METAL3 enclosure of VIA2 0.1um Minimum METAL3 enclosure of VIA2 for metal capacitor 0.1um Minimum CAPMETAL width 0.5um Minimum METAL2 enclosure of CAPMETAL 0.4um Minimum CAPMETAL enclosure of VIA2 0.2um Minimum CAPMETAL enclosure of METAL3 0.3um 50 Dept. Electronics and Communication, PESU- Electronic city,

51 13A 14A 14B 14C 15A 15B 15C 16A 16B 16C 17A 17B 17C 18A 18B 18C 19A 19B 19C 20A 20B 20C 20D 20E 20F 20G 20H Maximum distance from a source/drain OXIDE region to the nearest well tie 10um Minimum and maximum width of VIA3 0.2um Minimum VIA3 space 0.3um Minimum METAL3 enclosure of VIA3 0.1um Minimum METAL4 width 0.3um Minimum METAL4 space 0.3um Minimum METAL4 enclosure of VIA3 0.1um Minimum and maximum width of VIA4 0.2um Minimum VIA4 space 0.3um Minimum METAL4 enclosure of VIA4 0.1um Minimum METAL5 width 0.3um Minimum METAL5 space 0.3um Minimum METAL5 enclosure of VIA4 0.1um Minimum and maximum width of VIA5 0.2um Minimum VIA5 space 0.3um Minimum METAL5 enclosure of VIA5 0.1um Minimum METAL6 width 0.3um Minimum METAL6 space 0.3um Minimum METAL6 enclosure of VIA5 0.1um Minimum BONDPAD width 45.0um Minimum BONDPAD space 10.0um Minimum and Maximum METAL1 enclosure BONDPAD 3.0um Minimum and Maximum METAL2 enclosure BONDPAD 3.0um Minimum and Maximum METAL3 enclosure BONDPAD 3.0um Minimum and Maximum METAL4 enclosure BONDPAD 3.0um Minimum and Maximum METAL5 enclosure BONDPAD 3.0um Minimum and Maximum METAL6 enclosure BONDPAD 3.0um 51 Dept. Electronics and Communication, PESU- Electronic city,

52 Some of the important design rules mentioned above are pictorially represented in next page. N WELL RULE (p.t.o) OXIDE RULE 52 Dept. Electronics and Communication, PESU- Electronic city,

53 N imp/ P imp RULES 53 Dept. Electronics and Communication, PESU- Electronic city,

54 Poly RULE 54 Dept. Electronics and Communication, PESU- Electronic city,

55 PMOS LAYOUT: (W/L) = (2um /.18 um ) 55 Dept. Electronics and Communication, PESU- Electronic city,

56 The PMOS is designed with respect to the design rules mentioned. The PMOS is designed with a respect to the W/L ratio. W à Width of channel Nimp L à Width of POLY1 Layout of PMOS: ( W/L ) = (2um/.18um) 56 Dept. Electronics and Communication, PESU- Electronic city,

57 NMOS LAYOUT : (W/L) = (2um /.18 um ) 57 Dept. Electronics and Communication, PESU- Electronic city,

58 58 Dept. Electronics and Communication, PESU- Electronic city,

59 LAYOUT OF NMOS : (W/L) = ( 2um/.18um) 59 Dept. Electronics and Communication, PESU- Electronic city,

60 II ) LAYOUT GENERATION & TESTING PROCEDURE 1. Open the Inverter schematic window 2. Launch Lay out XL 3. A window opens, Enable create New option, A New cell view form open set the cell Name: Inverter ( Same as Schematic ) View Name : Layout and click OK. A LSW [ Layout schematic window] & blank Layout window opens. 4. In Layout window, Execute Connectivity Generate All from source. In the layout editor window, A Generate Layout form appears. In this form enable Labels options & Click OK. 5. Now, we can view the components and Area of silicon [boundary]. The Area defines that the required layout can be fitted in to that. There for try to restrict to this area. NOTE: As a beginner extend the height of area by maximum of 2 units. 6. Stretch the area by using stretch Key from edit window. 7. Move the components in to specified area and arrange them at required positions properly. 8. Press shift F to observe the internal view of the NMOS & PMOS. 9. Now Zoom the layout editor window and align the NMOS & PMOS exactly. [That is poly of both MOS must match to avoid the DRC errors]. 10. Make the required connections by selecting the required material from LSW window like poly, metal then create the required shapes by executing Create Shape Path / Rectangle 11. Once the required connection are made, the next step is to connect the required overlapping materials by using corresponding connectors (via)s Ex: The input A in inverter layout Input A - Contact made up of metal 1 Gate terminal shorted is poly. As input A is placed on poly, now these two different layers are connected by using corresponding connectors. 60 Dept. Electronics and Communication, PESU- Electronic city,

61 That is M1 POLY1 Via There for Execute Create Via In the Vias form, select the corresponding connector required and click Hide and the place on required position in layout by double click. 12. Finally save the layout. 13. Testing [Running DRC, ERC, LVS & RCX] A) Running DRC( Design Rule Checker) i) Execute Assura Run DRC. The DRC form opens Check: ii) Library:? Cell:? View:? [Layout]. This should be same what you have set iii) Technology gpdk 180. Then click OK. iv) A progress form appears.[don t click on OK] v) When DRC finishes, a dialog box appears asking you if you want to view your DRC results, and then click yes to view the results of this form. vi) If any DRC errors exist, a Error Layer window [ELW] appears. Open ELW window and rectify the errors by selecting the errors one by one. vii) Then follow step (i) to (v) mentioned above unit you get a message as No DRC errors found then clck on close to terminate the DRC run. B) Running LVS( Layout Vs Schematics). i) Assura LVS in Layout window ii) A Assura Run LVS window opens. Check: Schematic Design Source Lib: Cell: View: Layout Design Source Lib: Cell: View: iii) These should be have Schematic & Layout to be compared CLICK OK. The LVS begins and progress. Form appears. 61 Dept. Electronics and Communication, PESU- Electronic city,

62 iv) If schematic & Layout matches completely, you will get the form displaying Schematic and Layout Match If Not matching, a form informs LVS completed successfully and asks if you want view the results of this run. CLICK Yes in the form. v) The LVS debug form opens indicating the mismatches and you need to correct all these mismatches and Re run the LVS. C) Running RCX. i) Assura Run RCX. ii) Assura RCX form opens. Set the output type under setup tab as extracted View. [ It may be preset]. CLICK OK. Under filtering tab of the form, Enter Power Nets as Vdd!, Vss! And Enter ground nets as gnd! Then Click OK for the form. iii) RCX progress form appears, wait until it completes the process. iv) Whwn RXC complete, a dialog box appears, informs you that Assura RCX run Completed Successfully. v) Go to CIW (Virtuso window) File open av- extracted view form the corresponding library. Then, the av-extracted view window opens with parasitic components (RC). Observe the view by zooming III) Creating Configuration View i) Creating Config View a. Go to CIW window, Execute File-New-Cell view b. Setup the new file form Library: Select the one you a created. Cell: Cell name must be different from the name used in schematic cell view. Ex: Inverter_test View: Config Type: Schematic press OK A Hierarchy Editor window and New Configuration Form opens 62 Dept. Electronics and Communication, PESU- Electronic city,

63 c. In the New Configuration form, Click on Use Templates present at the bottom of form. A use Templates window opens. d. In Use Template form set Name: SPECTRE by scroll down button, then Click OK. e. Now,In the New Configuration window Change Top Cell View: Schematics and Set the Library Link: BLANK, Then CLICK OK in New Configuration window. Now, Hierarchy Editor Window Opens. f. In Hierarchy Editor Window, Press Table View tab and check cell building. g. In Hierarchy Editor Window, Press Tree View tab and check occurances. h. Press Recompute the Hierarchy icon i. Save the current configuration. j. Close the hierchy Editor window. Execute File Close Window IV) RUNNING circuit without parasites. a. Go to CIW window and open (Inverter_test) Config view, Top cell view form opens. b. Enable Yes and Yes in Top Cell View form c. Launch ADE L(Analog Design Environment) d. Execute Setup Simulation/directory/Host A new window opens e. Set the simulation window to spectre and click ok f. Execute Setup-Model Library. Anew window opens, Check of gpdk.scs as lib and section type as stat then press OK. g. Execute Analysis Choose. A window opens. h. Select the type and set the specifications and press OK i. Execute Output s to be plotted Select on Schematic j. Then Select the INPUT WIRE(Vin ) and OUTPUT WIRE(Vout) from your test Schematic using mouse k. Execute Simulation -- Net list and Run Propagation Delay Calculation After completing STEP (IV),A waveform window will be opened. a. In the waveform window execute Tool Calculator. A calculator window appears 63 Dept. Electronics and Communication, PESU- Electronic city,

64 b. Click on special function tab. A window with different functions open, In this select delay. c. A addition form for calculation will be present to select and the parameters for delay calculation. i. Place the curser in signal1 text box, Enable Wave button and enable the input Net(Vin) (Line) in the schematic window. ii. Repeat above step for Signal 2. iii. Set threshold values w.r.t experiment ( Ex: For Inverter ; Threshold Value 1 & Threshold Value 2 to 0.9,this directs the calculator to calculate the delay at 50% i.e at 0.9 volts( 1.8V/2) iv. Click OK and observe the expression created in the calculator buffer. d. Click on the Evaluate the buffer icon to perform the calculation and note down the valued returned after execution. e. Close the calculator window. IV) RUNNING circuit with parasites. a. Open the same hierarchy Editor window which is already set for config. b. Select the TREE VIEW tab,this will show the design hierarchy in tree format. c. CLICK right button on IO (lib name Inverter schematic) in TREE VIEW and Select set instances view as av_extracted view. d. Press Recompute the Hierarchy icon, the configuration is now updated from schematic to av_extracted view e. Then,go output waveform window( analog design environment) and click Netlist and RUN f. Observe the waveform with additional nets and parameters. g. Calculate the delay again and match with the previous one. Now you can conclude how much delay is introduced by parasites by comparing delay with and without parasites and based on this we need to optimize the parasitic effect and reduce the delay due to parasites. This finally leads to an optimized layout 64 Dept. Electronics and Communication, PESU- Electronic city,

65 LSW What is LSW? It is a layout Vs Schematic window which consists of different layers used for layout. The layers to drawn or traced has to be selected from the LSW window and the required type of shape has to be created by using the Create à Shape àselect the required shapes. The Shapes may be a Rectangle, Circle, Path so on. Rectangle: This shape is chosen when the shape to be drawn is rectangular and but the size is not defined. 65 Dept. Electronics and Communication, PESU- Electronic city,

66 Path: This shape is chosen when the path to be drawn is with predefined with. The drawn shapes must follow the design rules. Experiment 1(b): Inverter layout 66 Dept. Electronics and Communication, PESU- Electronic city,

67 67 Dept. Electronics and Communication, PESU- Electronic city,

68 Experiment 2(b): Common Source layout 68 Dept. Electronics and Communication, PESU- Electronic city,

69 69 Dept. Electronics and Communication, PESU- Electronic city,

70 Experiment 3(b): Common Drain layout 70 Dept. Electronics and Communication, PESU- Electronic city,

71 71 Dept. Electronics and Communication, PESU- Electronic city,

72 Experiment 4(b): Differential Amplifier layout 72 Dept. Electronics and Communication, PESU- Electronic city,

73 73 Dept. Electronics and Communication, PESU- Electronic city,

74 Experiment 5(b): Operational Amplifier layout 74 Dept. Electronics and Communication, PESU- Electronic city,

75 75 Dept. Electronics and Communication, PESU- Electronic city,

76 76 Dept. Electronics and Communication, PESU- Electronic city,

77 77 Dept. Electronics and Communication, PESU- Electronic city,

78 78 Dept. Electronics and Communication, PESU- Electronic city,