STATUS of the ELECTRONICS. Claudio Arnaboldi Gianluigi Pessina

Transcription

1 STATUS of the ELECTRONICS Claudio Arnaboldi Gianluigi Pessina 1

2 Scheduling The plans for this year are: Final selection and purchasing of the input transistor (JFET) of the very front-end for the room temperature preamplifier; Prototyping of the new, upgraded, version of the room temperature preamplifier (ten channels or so); Prototyping of the new mother board of the front-end (it will begin within this year); Test of the Cold stage prototype (under way). 2

3 Very front-end specifications The main sources of noise from the front-end are: Series noise of the front-end; Parallel noise of the front-end; Parallel noise of the load resistors. The relevance of each of the above parameters are visible in the real case. 3

4 Noise effect on the extreme bolometers of CUORICINO Detector name Static Impedanc e R B (MΩ) Dynamic Imp./ Static Imp. Z B /R B Energy Conv. Gain. μv/mev Resolution at 2615 ev FWHM B B B Load resistors parallel noise τfall 142 (54 GΩ, 300K) 355 (54 GΩ, 300K) 1988 (54 GΩ, 300K) 795 (54 GΩ, 300K) Preamplifi er parallel noise τfall 72 (1 pa) 145 (4 pa) 181 (1 pa) 362 (4 pa) 1015 (1 pa) 2030 (4 pa) 406 (1 pa) 812 (4 pa) Series noise of the preamplifi er τ fall 32 (3 nv/ Hz) 55 (5 nv/ Hz) 32 (3 nv/ Hz) 55 (5 nv/ Hz) 67 (3 nv/ Hz) 111 (5 nv/ Hz) 54 (3 nv/ Hz) 90 (5 nv/ Hz) 4

5 Summary of the noise weight The main source of noise is parallel and comes from the Load resistors. It can be lowered only if they are wormed at 100 K, or less, adopting the cold electronic. The series noise of the preamplifier has a negligible contribution. Parallel noise of the preamplifier still adds a marginal contribution to the energy resolution even when its total input current approaches 4 pa. 5

6 Considerations on the parallel noise of preamplifier In the previous table it was considered a change of a factor of 4 in the preamplifier input current, that corresponds to an environment temperature increase of about 20 C. This fact derives from the temperature dependence of the reverse current in a pn junction: I I G G0 ( ) 6667 T V,V e DG GS ΔT 20 C ΔI I In the selection of the JFET input transistor we have taken into account this. 4 6

7 I DS (ma) Pre-Production test at room temperature Drain current (Ids_vs_Vds N3a) Working point at 300 K =-0.05 =-0.10 =-0.15 =-0.20 =-0.25 =-0.30 =-0.35 =-0.40 =-0.45 =-0.50 Start= V Stop= -0.5 V Step= V OFF (V) Static characteristics fully match our requirements. 7

8 Pre-Production test at room temperature Gate leakage current (Ids_vs_Vgs_gate_current_3terminal N3a) =0.10 =0.37 =0.63 =0.90 I GS (pa) X: Y: Start= 0.1 V Stop= 0.9 V Step= 0.3 V Gate current at the operating point (V) The input gate current, per JFET, is about 0.45 pa at the operating point. The total input current of the differential stage is then 0.9 pa. Adequate for CUORE. 8

9 Pre-Production test at room temperature 3 There is a consideration that regards the Gate current. In the characterization of a batch received previously we have verified a gate current close to 0.1 pa: There is a remarkable difference between the two sets of JFET.. 9

10 Pre-Production test at room temperature 4 In the batch where the lower Gate current was verified the JFETs are assembled in a metallic package: The last pre-production received batch has the JFETs mounted in an SMD plastic package, which offers a reduction of space occupation, mainly in the vertical direction. SOIC8 If the larger leakage of the new batch were due to a parasitic resistance, its order of magnitude is >10 12 Ω. This parasitic resistance will not add shot noise, or its shot noise is equivalent to a junction reverse current of only 50 fa. 10

11 Pre-Production test at room temperature 5 However, we are going to investigate the origin of this behavior in 2 ways: Performing the measurements changing the temperature. We expect an exponential dependence in the gate current only in case the junction current is dominant. SOIC8 We have just asked for a few additional samples mounted in a metallic package to verify the gate current in this condition. If found lower, we will ask for a final packaging of this type: in the room temperature set-up the space occupation in the vertical direction may be larger. 11

12 I DS (ma) Cold stage 1 Drain current (Ids_vs_Vds azoto N3b) =0.30 =0.25 =0.20 =0.15 =0.10 =0.05 =-0.00 =-0.05 = Working Point at 80 K (V) Start= 0.3 V Stop= -0.1 V Step= V OFF 0.05 The behavior at 80 K of the JFET was fine. A possible working point is: I DS = 50 μa and =0.2 V. This means that the required power dissipation for 1000 cold differential channels is, in total, 20 mw!!!! 12

13 I GS (pa) Cold stage 2 Gate leakage current (Ids_vs_Vgs_gate_current_3terminal azoto N3b) 0 =0.10 =0.37 =0.63 =0.90 Start= 0.1 V Stop= 0.9 V Step= 0.3 V (V) The Gate current at cold is compatible with the instrument floor. 13

14 CONCLUSIONS and PERSPECTIVES A pre-production of the input transistor of the very front-end are under investigation. This pre-production has been found adequate for CUORE, at least with respect to the static characteristics and parallel noise, for what concern both the room temperature operated preamplifier and the cold set-up. We are verifying if there is still margin to improve the parallel noise. This will be verified soon. The series noise performances at 300 K, 80 K and 110 K, is going to be measured to fully qualify the JFETs. The following steps will be: Purchasing of the 1100 differential JFETs for CUORE; the realization of the new upgraded preamplifier; cold electronics tests. 14