Matched N-Channel JFET Pairs

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1 N59/59 Matched N-Channel JFET Pairs Part Number V GS(off) (V) V (BR)GSS Min (V) Min I G Typ (pa) V GS V GS Max (mv) N59 to N59 to Two-Chip Design High Slew Rate Low Offset/Drift Voltage Low Gate Leakage: pa Low Noise High CMRR: 5 db Minimum Parasitics Ensuring Maximum High-Frequency Performance Improved Op Amp Speed, Settling Time Accuracy Minimum Input Error/Trimming Requirement Insignificant Signal Loss/Error Voltage High System Sensitivity Minimum Error with Large Input Signal Wideband Differential Amps High-Speed, Temp-Compensated, Single-Ended Input Amps High Speed Comparators Impedance Converters The N59/59 are matched pairs of JFETs mounted in a TO-7 package. This two-chip design reduces parasitics and gives better performance at high frequencies while ensuring extremely tight matching. For similar products see the SO- packaged SST/SST, the TO-7 packaged U/U, the low-noise SST/U series, and the low-leakage U/ data sheets. The hermetically-sealed TO-7 package is available with full military screening per MIL-S-95 (see Military Information). TO-7 S G 7 D D G 5 S Case Top View Gate-Drain, Gate-Source Voltage V Gate-Gate Voltage V Gate Current ma Lead Temperature ( / from case for sec.) C Storage Temperature to C Operating Junction Temperature to 5 C For applications information see AN. Document Number: 755 S- Rev. D, -Jun- Power Dissipation : Per Side a mw Total b mw Notes a. Derate mw/ C above 5 C b. Derate mw/ C above 5 C -

2 N59/59 Static N59 Limits N59 Parameter Symbol Test Conditions Typ a Min Max Min Max Unit Gate-Source Breakdown Voltage V (BR)GSS I G = A, V DS = V Gate-Source Cutoff Voltage V GS(off) V DS = V, = na Saturation Drain Current b SS V DS = V, V GS = V ma V GS = 5 V, V DS = V pa Gate Reverse Current I GSS T A = 5 C 5 5 na V DG = V, = 5 ma pa Gate Operating Current I G T A = 5 C. na Gate-Source Voltage V GS V DG = V, I G = 5 ma.5.. Gate-Source Forward Voltage c V GS(F) I G = ma, V DS = V.7 Dynamic Forward Transconductance Output Conductance Forward Transconductance Output Conductance Input Capacitance Reverse Transfer Capacitance Equivalent Input Noise Voltage g os g os C iss C rss e n V DG = V, = 5 ma V DG = V, = 5 ma f = MHz V DG = V, = 5 ma f = MHz V DG = V, = 5 ma V 5 5 ms 7 S ms S Noise Figure NF R G = k. db Matching Differential Gate-Source Voltage Gate-Source Voltage Differential Change with Temperature V GS V GS V DG = V, = 5 ma 5 mv V GS V GS T V DG = V, = 5 ma T A = 55 to 5 C V pf nv Hz 5 V/ C Saturation Drain Current Ratio SS SS V DS = V, V GS = V Transconductance Ratio V DS = V, = 5 ma Differential Gate Current I G I G V DG = V, = 5 ma, T A = 5 C.5 na Common Mode Rejection Ratio c CMRR V DG = 5 to V, = 5 ma 5 db Notes a. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. NZF b. Pulse test: PW s duty cycle %. c. This parameter not registered with JEDEC. - Document Number: 755 S- Rev. D, -Jun-

3 N59/59 5 Drain Current and Transconductance vs. Gate-Source Cutoff Voltage na Gate Leakage Current SS Saturation Drain Current (ma) V DS = V, V GS = V DS = V, V GS = V SS Forward Transconductance I G Gate Leakage na na pa pa pa I T A = 5 C I 5 C T A = 5 C = ma ma ma ma I 5 C. pa V GS(off) Gate-Source Cutoff Voltage (V) V DG Drain-Gate Voltage (V) V GS(off) = V V GS = V.5 V V GS = V. V. V. V. V. V. V.5 V. V.5 V. V.5 V. V 5 5 V GS(off) = V V GS = V. V V GS = V. V. V. V. V. V 9. V. V.5 V.5 V.5 V. V.5 V Document Number: 755 S- Rev. D, -Jun- -

4 N59/59 Transfer Characteristics Transfer Characteristics V GS(off) = V V DS = V V DS = V 5 C 5 C 5 C 5 C Transconductance vs. Gate-Source Voltage Transconductance vs. Gate-Source Voltage Forward Transconductance A V Voltage Gain 5 V GS(off) = V 5 C.... A V R L R L g os Assume V DD = 5 V, V DS = 5 V R L V V GS(off) = V 5 C V DS = V Circuit Voltage Gain vs. Drain Current r DS(on) Drain-Source On-Resistance ( Ω ) Forward Transconductance 5 C V DS = V 5 C V GS(off) = V On-Resistance vs. Drain Current 5 V T A = 5 C 5. - Document Number: 755 S- Rev. D, -Jun-

5 N59/59 Ciss Input Capacitance (pf) Input Capacitance vs. Gate-Source Voltage f = MHz V DS = 5 V V V Crss Reverse Feedback Capacitance (pf) 5 Reverse Feedback Capacitance vs. Gate-Source Voltage f = MHz V DS = 5 V V V T A = 5 C V DS = V = ma Input Admittance T A = 5 C V DS = V = ma Forward Admittance g ig b is b fs g fg b ig b fg g is T A = 5 C V DS = V = ma Reverse Admittance T A = 5 C V DS = V = ma Output Admittance b rs b rg b og, b os. g rs g rg g rg g og, g os Document Number: 755 S- Rev. D, -Jun- -5

6 N59/59 en Noise Voltage nv / Hz 5 Equivalent Input Noise Voltage vs. Frequency V DS = V = ma ma g os Output Conductance (µs) 5 9 Output Conductance vs. Drain Current 5 C 5 C V DS = V k k k. f Frequency (Hz) On-Resistance and Output Conductance vs. Gate-Source Cutoff Voltage Forward Transconductance vs. Drain Current r DS(on) Drain-Source On-Resistance ( Ω ) r DS g os r = ma, V GS = V g V DS = V, V GS = V g os Output Conductance (µs) Forward Transconductance 5 C V DS = V 5 C. V GS(off) Gate-Source Cutoff Voltage (V) - Document Number: 755 S- Rev. D, -Jun-

Matched N-Channel JFET Pairs

U/ Matched N-Channel JFET Pairs Part Number V GS(off) (V) V (BR)GSS Min (V) Min I G Typ (pa) V GS V GS Max (mv) U to 5.5 U to 5.5 Two-Chip Design High Slew Rate Low Offset/Drift Voltage Low Gate Leakage: