P40-G Series TBU High-Speed Protectors

Transcription

1 *RoHS COMPLIAT eatures ormerly brand Extremely high speed performance Low impedance Two TBU protectors in one small package Very high bandwidth, GHz compatible Simple, superior circuit protection RoHS compliant*, UL Recognized Applications xsl (ASL, VSL, VSL2) High ata Rate Interface IC protection (LVS, HMI, etc.) Industrial sensors and controls General electronics P40-G Series TBU High-Speed Protectors Transient Blocking Units - TBU evices Agency Approval Bourns Model P40-G products are high-speed bidirectional protection components, constructed using MOSET semiconductor technology, designed to protect against faults caused by short circuits, AC power cross, induction and lightning surges. The TBU high-speed protector, triggering as a function of the MOSET, blocks surges and provides an effective barrier behind which sensitive electronics are not exposed to large voltages or currents during surge events. The TBU device is provided in a surface mount package and meets industry standard requirements such as RoHS and Pb ree solder refl ow profi les. UL recognized component ile # E Industry Standards escription Telcordia GR-089 ITU-T K.20, K.20E, K.2, K.2E, K.45 Model P40-G Absolute Maximum Ratings (T amb = 25 C) Symbol Parameter Value Unit V imp Maximum protection voltage for impulse faults with rise time µsec 40 V V rms Maximum protection voltage for continuous V rms faults 28 V T op Operating temperature range -40 to +85 C T stg Storage temperature range -65 to +50 C Electrical Characteristics (T amb = 25 C) Symbol Parameter Min. Typ. Max. Unit I op Maximum current through the device that will not cause current blocking 240 ma I trigger Typical current for the device to go from normal operating state to protected state 350 ma I out Maximum current through the device 480 ma R device Series resistance of the TBU device Ω R bal Line-to line series resistance difference between two TBU devices 5 % t block Maximum time for the device to go from normal operating state to protected state 0.2 µs I quiescent Current through the triggered TBU device with 40 Vdc circuit voltage 0.7 ma V reset Voltage below which the triggered TBU device will transition to normal operating state 7 V The P40-G Series TBU high-speed protector is bidirectional; specifi cations are valid in both directions. *RoHS irective 2002/95/EC Jan. 27, 2003 including annex and RoHS Recast 20/65/EU June 8, 20.

2 Typical Performance Characteristics V-I Characteristics Time to Block vs. ault Current +I Time to Block vs. ault Current I trigger 0. -V reset V reset +V Time to Block (sec) I trigger ault Current (A ) Trigger Current vs. Temperature % of Trigger Current Temperature ( C)

3 Operational Characteristics The graph below demonstrates the operational characteristics of the TBU device. In the graph below the fault voltage, protected side voltage, and current is presented. TEST COIGURATIO IAGRAM Line Line2 V P40-G Load P40-G Lightning Protection 40 V 3 0 V/div. 400 ma/div. µs/div. Ch V Ch3 Current

4 Product imensions A B PI C K TOP VIEW SIE VIEW BOTTOM VIEW Recommended Pad Layout 0.35 (.04) 0.90 (.035) (.02) +0.05/-0.00 ( /-.000) 2.60 (.02).45 (.057) G G J E Pad esignation Pad # Apply In 2 C 3 Out 4 Out2 5 C 6 In2 C = Solder to PCB; do not make electrical connection, do not connect to ground. K J H H M im. Min. Typ. Max. A B C E G H J K M 3.90 (.54) 3.90 (.54) 0.80 (.03) (.000) 2.55 (.00) 0.20 (.008) 0.75 (.030).40 (.055) 0.0 (.004) (.00) 0.55 (.022) 0.20 (.008) IMESIOS: Block iagram 4.00 (.57) 4.00 (.57) 0.85 (.033) (.00) 2.60 (.02) (.00) 0.80 (.03).45 (.057) 0.5 (.006) (.02) 0.60 (.024) (.00) MM (ICHES) 4.0 (.6) 4.0 (.6) 0.90 (.035) (.002) 2.65 (.04) (.02) 0.85 (.033) (.008) 0.35 (.04) 0.65 (.026) (.02) TBU devices have matte-tin termination fi nish. Suggested layout should use non-solder mask defi ne (SM). Recommended stencil thickness is mm ( in.) with stencil opening size mm (.000 in.) less than the device pad size. As when heat sinking any power device, it is recommended that, wherever possible, extra PCB copper area is allowed. or minimum parasitic capacitance, do not allow any signal, ground or power signals beneath any of the pads of the device TBU evice Thermal Resistances Thermal resistance using minimal pad size, where the power is the total power dissipated in the package. Additional copper pad area to be used for additional heatsinking is also recommended. Symbol Parameter Value Unit R th(j-a) Junction to Package Pads ( TBU of Pair) 250 C/W R th(j-a) Junction to Package Pads (2 TBUs of Equal Power) 80 C/W

5 Reflow Profile Profile eature Pb-ree Assembly Average Ramp-Up Rate (Tsmax to Tp) 3 C/sec. max. Preheat - Temperature Min. (Tsmin) - Temperature Max. (Tsmax) - Time (tsmin to tsmax) 50 C 200 C sec. Time maintained above: - Temperature (TL) - Time (tl) 27 C sec. Peak/Classifi cation Temperature (Tp) 260 C Time within 5 C of Actual Peak Temp. (tp) sec. Ramp-own Rate 6 C/sec. max. Time 25 C to Peak Temperature 8 min. max. How to Order orm actor P = Two TBU protectors in one device Impulse Voltage Rating 40 = 40 V irectional Indication G = Bidirectional Iop Indicator 240 = 240 ma P 40 - G WH Typical Part Marking MAUACTURER S TRAEMARK* MARKIG UMBER 04GC = P40-G240-WH PI MAUACTURIG ATE COE* - ST IGIT IICATES THE YEAR S 6-MOTH PERIO. - 2 IGIT IICATES THE WEEK UMBER I THE 6-MOTH PERIO. - 3R & 4TH IGITS IICATE SPECIIC LOT OR THE WEEK. 6-MOTH PERIO COES: A = JA-JU 2009 C = JA-JU 200 E = JA-JU 20 B = JUL-EC 2009 = JUL-EC 200 = JUL-EC 20 EXAMPLE: ARBC - ST IGIT A = JA-JU IGIT R = WEEK 8; WEEK O APRIL 27-3R & 4TH IGITS BC = LOT SPECIIC IORMATIO *TRASITIO ROM ULTEC TRAEMARK A LOT COE TO BOURS TRAEMARK A ATE COE I 2009.

6 Packaging Specifications (per EIA468-B) B t TOP COVER TAPE P 0 P 2 E A W C K 0 B 0 G (MEASURE AT HUB) A 0 P CETER LIES O CAVITY EMBOSSMET USER IRECTIO O EE QUATITY: 3000 PIECES PER REEL evice P40-G240 A B C G Min. Max. Min. Max. Min. Max. Min. Max. Ref. Ref. 326 (2.835) 33 (3.002) (.098) 2.8 (.504) 3.5 (.53) 20.2 (.795) (.488) 02 (4.06) evice P40-G240 evice P40-G240 A 0 B 0 E Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. max. 4.2 (.65) 4.4 (.73) 4.2 (.65) 4.4 (.73).5.6 (.063) (.065).85 (.073) 5.45 (.26) 5.55 (.29) K0 P P0 P 2 t W Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max..05 (.04).25 (.049) 7.9 (.3) 8. (.39) 3.9 (.59) 4. (.6).9 (.075) 2. (.083) (.00) 0.35 (.04).7 (.46) 2.3 (.484) IMESIOS: MM (ICHES)

7 Model P40-G P40-G Series Series TBU High-Speed - Protectors Surge Protectors Reference Application A cost-effective protection solution combines the Bourns TBU protection device with a diode bridge on the driver side of the transformer and GTs on the line side. The GT should have a minimum CB of 900 V and a maximum sparkover voltage of 600 V. The diagram below illustrates a common configuration of these components. The graph demonstrates the operational characteristics of the circuit. Ch Ch3 V CC P40 P40-G Common Confi guration iagram - xsl Protection V/div. 200 ma/div. µs/div. Ch V Ch3 Current 5000 V Lightning 2/0 μsec, 500 A Asia-Pacific: Tel: ax: Europe: Tel: ax: The Americas: Tel: ax: REV. 04/2 TBU is a registered trademark of Bourns, Inc. in the United States and other countries.