NCP700C. 200 ma, Ultra Low Noise, High PSRR, BiCMOS RF LDO Regulator

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1 NCP7C 2 ma, Ultra Low Noise, High PSRR, BiCMOS RF LDO Regulator Noise sensitive RF applications such as Power Amplifiers in cell phones and precision instrumentation require very clean power supplies. The NCP7C is 2 ma LDO that provides the engineer with a very stable, accurate voltage with ultra low noise and very high Power Supply Rejection Ratio (PSRR) suitable for RF applications. In order to optimize performance for battery operated portable applications, the NCP7C employs an advanced BiCMOS process to combine the benefits of low noise and superior dynamic performance of bipolar elements with very low ground current consumption at full loads offered by CMOS. Furthermore, in order to provide a small footprint for space constrained applications, the NCP7C is stable with small, low value capacitors and is available in a very small WDFN. mm x. mm. X M WDFN CASE BJ = Specific Device Code = Date Code = PbFree Package MARKING DIAGRAM X M Features Output Voltage Options:. V Contact Factory for Other Voltage Options Excellent Line and Load Regulation Ultra Low Noise (typ. Vrms) High PSRR (typ 7 khz) Stable with Ceramic Output Capacitors as low as F Very Low Ground Current (typ. 7 no load) Low Disable Mode Current (max. A) Current Limit Protection Thermal Shutdown Protection These Devices are PbFree, Halogen Free/BFR Free and are RoHS Compliant OUT GND BYP PIN CONNECTIONS 2 3 (Top View) ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. IN NC EN Applications Smartphones / PDAs / Palmtops / GPS Cellular Telephones (Power Amplifier) Noise Sensitive Applications (RF, Video, Audio) Analog Power Supplies Battery Supplied Devices V IN C IN F ON OFF IN EN NCP7C GND 2 OUT BYP 3 C NOISE nf C OUT F V OUT Figure. NCP7C Typical Application Semiconductor Components Industries, LLC, 2 August, 2 Rev. Publication Order Number: NCP7C/D

2 NCP7C IN OUT Bandgap Reference Voltage - + Current Limit BYP EN R PD GND Figure 2. Simplified Block Diagram PIN FUNCTION DESCRIPTION Pin No. Pin Name Description OUT Regulated Output Voltage 2 GND Power Supply Ground 3 BYP Noise reduction pin. (Connect nf or nf capacitor to GND) EN Enable pin: This pin allows on/off control of the regulator. To disable the device, connect to GND. If this function is not in use, connect to Vin. Internal M Pull Down resistor is connected between EN and GND. N/C Not connected IN Input Voltage MAXIMUM RATINGS Rating Symbol Value Unit Input Voltage IN.3 V to V V Chip Enable Voltage EN.3 V to V IN +.3 V Noise Reduction Voltage BYP.3 V to V IN +.3 V V Output Voltage OUT.3 V to V IN +.3 V V Output shortcircuit duration Maximum Junction Temperature T J(max) C Storage Temperature Range T STG to C Electrostatic Discharge (Note ) Human Body Model ESD 2 V Infinity Machine Model 2 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.. This device series contains ESD protection and exceeds the following tests: Human Body Model 2 V tested per MILSTD883, Method 3 Machine Model Method 2 V THERMAL CHARACTERISTICS Rating Symbol Value Unit Package Thermal Resistance, WDFN: (Note 2) JunctiontoAmbient (Note 3) Package Thermal Characterization Parameter, WDFN: JunctiontoLead (Pin 2) (Note 3) JunctiontoBoard (Note 3) JA JL2 JB 8 23 C/W 2. Refer to APPLICATION INFORMATION for Safe Operating Area 3. Single component mounted on oz, FR PCB with mm 2 Cu area. 2

3 NCP7C ELECTRICAL CHARACTERISTICS V IN = V OUT +. V or 2. V (whichever is greater), V EN =.2 V, C IN =, C NOISE = nf, I OUT = ma, T J = C to 2 C, unless otherwise specified (Note ) Parameter Test Conditions Symbol Min Typ Max Unit REGULATOR OUTPUT Input Voltage Range V IN 2.. V Output Voltage Accuracy T J = C to 2 C, V IN = (V OUT +. V) to. V I OUT = ma to 2 ma V OUT 2.% +2.% V Line Regulation V IN = (V OUT +. V) to. V, I OUT = ma V OUT / V IN 2 V/V Load Regulation I OUT = ma to 2 ma V OUT / I OUT. V/mA Dropout Voltage (Note ) I OUT = 2 ma V OUT(NOM) =. V V DO 8 mv Output Current Limit V OUT = V OUT(NOM). V I LIM ma Output Short Circuit Current V OUT = V I SC ma Ground Current I OUT = ma I OUT = 2 ma I GND A Disable Current V EN = V I DIS. A Power Supply Rejection Ratio Output Noise Voltage V IN = V OUT +. V, V OUT =. V, I OUT = ma f = Hz to khz, I OUT = ma, V OUT =. V f = Hz PSRR db f = khz 7 f = khz f = khz 37 f = MHz 2 C NOISE = nf C NOISE = nf V N 23 V RMS TurnOn Time (Note ) I OUT = ma, C NOISE = nf t ON s Enable Threshold Low High V th(en).2. V Enable Internal PullDown Resistance (Note 7) R PD 2. M Thermal Shutdown Shutdown, Temperature increasing T SDU C Reset, Temperature decreasing T SDD 3 C Operating Junction Temperature T J 2 C Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T J = T A = 2 C. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.. Measured when the output voltage falls mv below the nominal output voltage (nominal output voltage is the voltage at the output measured under the condition V IN = V OUT +. V). In the case of devices having the nominal output voltage V OUT =.8 V the minimum input to output voltage differential is given by the V IN(MIN) = 2. V.. The turnon time is the time from asserting the EN to the point where output voltage reaches 98% nominal voltage level. 7. Expected to disable the device when EN pin is floating. 3

4 NCP7C V OUT, OUTPUT VOLTAGE CHANGE (mv) T J = 2 C T J = C T J = 8 C V IN =. V C NOISE = nf 2 I OUT, LOAD CURRENT (ma) Figure 3. Load Regulation V OUT, OUTPUT VOLTAGE CHANGE (mv) V IN =. V C NOISE = nf 2 8 I OUT, LOAD CURRENT (ma) Figure. Load Regulation Under Light Loads V OUT, OUTPUT VOLTAGE CHANGE (%) T J = 2 C T J = C T J = 8 C I OUT = ma C NOISE = nf Figure. Line Regulation V OUT, OUTPUT VOLTAGE CHANGE (%) T J = 2 C T J = C I OUT = 2 ma C NOISE = nf T J = 8 C Figure. Line Regulation V OUT, OUTPUT VOLTAGE CHANGE (%) I OUT = ma I OUT = 2 ma.. 2. V IN =. V C NOISE = nf T J, JUNCTION TEMPERATURE ( C) Figure 7. Output Voltage vs. Temperature V DO, DROPOUT VOLTAGE (mv) 2 8 T J = 2 C T J = C 2 C NOISE = nf I OUT, OUTPUT CURRENT (ma) Figure 8. Dropout Voltage vs. Output Current

5 NCP7C V DO, DROPOUT VOLTAGE (mv) I GND, GROUND PIN CURRENT ( A) I OUT = 2 ma C NOISE = nf T J, JUNCTION TEMPERATURE ( C) Figure 9. Dropout Voltage vs. Temperature V IN =. V C NOISE = nf I OUT, OUTPUT CURRENT (ma) Figure. Ground Pin Current vs. Output Current I GND, GROUND PIN CURRENT ( A) I GND, GROUND PIN CURRENT ( A) C NOISE = nf I OUT = A I OUT = ma I OUT = 2 ma Figure. Ground Pin Current vs. Input Voltage I OUT = 2 ma 7 I OUT = ma 7 V IN =. V C NOISE = nf T J, JUNCTION TEMPERATURE ( C) Figure 2. Ground Pin Current vs. Temperature I DIS, DISABLE CURRENT ( A) V EN = V C NOISE = nf V IN = V V IN =. V T J, JUNCTION TEMPERATURE ( C) Figure 3. Disable Ground Pin Current vs. Temperature I LIM, OUTPUT CURRENT (ma) Short Circuit Limit Output Current Limit 2 V IN =. V C 2 NOISE = nf T J, JUNCTION TEMPERATURE ( C) Figure. Output Current Limit vs. Temperature

6 NCP7C ma 7 ma 2 ma C NOISE = nf k k k M M Figure. PSRR vs. Frequency, V IN V OUT =. V 2 ma 7 ma 2 ma C NOISE = nf k k k M M Figure. PSRR vs. Frequency, V IN V OUT =. V ma 7 ma 2 ma C NOISE = nf k k k M M Figure 7. PSRR vs. Frequency, V IN V OUT =.2 V 2 ma 2 ma C NOISE = nf k k k M M Figure 8. PSRR vs. Frequency, V IN V OUT =. V ma 2 ma C NOISE = nf k k k M M Figure 9. PSRR vs. Frequency, V IN V OUT =. V 2 ma 2 ma C NOISE = nf k k k M M Figure 2. PSRR vs. Frequency, V IN V OUT =.2 V

7 NCP7C ma 2 ma C NOISE = nf k k k M M Figure 2. PSRR vs. Frequency, V IN V OUT =. V 2 ma 2 ma C NOISE = nf k k k M M Figure 22. PSRR vs. Frequency, V IN V OUT =.2 V 8 7 khz khz 8 7 khz khz 3 MHz khz 3 khz MHz 2 I OUT = ma C NOISE = nf V IN V OUT, INPUT TO OUTPUT PIN VOLTAGE (V) Figure 23. PSRR vs. (V IN V OUT ) 2 I OUT = 7 ma C NOISE = nf V IN V OUT, INPUT TO OUTPUT PIN VOLTAGE (V) Figure 2. PSRR vs. (V IN V OUT ) khz khz khz MHz 2 I OUT = 2 ma C NOISE = nf V IN V OUT, INPUT TO OUTPUT PIN VOLTAGE (V) Figure 2. PSRR vs. (V IN V OUT ) Hz to khz RMS OUTPUT NOISE ( Vrms) Integral noise, C NOISE = nf: Hz khz: 32 Vrms Hz khz: 2 Vrms Integral noise, C NOISE = nf: Hz khz: Vrms Hz khz: Vrms C NOISE = nf C NOISE = nf V IN =. V I OUT = ma k k k M C NOISE, NOISE BYPASS CAPACITOR (nf) Figure 2. Output Noise vs. Noise Bypass Capacitor 7

8 NCP7C Hz to khz RMS OUTPUT NOISE ( Vrms) V IN =. V I OUT = 2 ma Hz to khz RMS OUTPUT NOISE ( Vrms) V IN =. V I OUT = 2 ma C NOISE = nf 2 3 C NOISE, NOISE BYPASS CAPACITOR (nf) Figure 27. Output Noise vs. Noise Bypass Capacitor C OUT, OUTPUT CAPACITOR ( F) Figure 28. Output Noise vs. Output Capacitor V OUT, OUTPUT VOLTAGE (V). V.7.. V I OUT = 3 ma.9.8 C NOISE = nf.8 dv IN /dt = V/ s t, TIME ( s) Figure 29. Line Transient Response V OUT, OUTPUT VOLTAGE (V)... ma.. V IN =. V.3.3 C NOISE = nf t, TIME ( s) ma Figure 3. Load Transient Response 3 2 I OUT, OUTPUT CURRENT (ma) 8

9 NCP7C V EN = V IN 2 I OUT =. ma C NOISE = nf 8 2 t, TIME ( s) V OUT, OUTPUT VOLTAGE (V) Figure 3. PowerUp V, VOLTAGE (V) 3 2 V OUT V EN = V IN I OUT = 2 ma C NOISE = nf V IN 2 3 t, TIME (ms) Figure 32. PowerUp / Down 9

10 NCP7C V OUT, OUTPUT VOLTAGE (V)... V C noise = 7 nf C noise = 22 nf C noise = nf C noise = nf T A = 2 C, V IN =. V,. I OUT = 3 ma t, TIME (ms) Figure 33. TurnOn Response 2 V EN, ENABLE VOLTAGE (V) V OUT, OUTPUT VOLTAGE (V) T A = 2 C,. C NOISE = nf, R LOAD = k Figure 3. Output Voltage vs. Input Voltage 8 I q, QUIESCENT CURRENT ( A) T A = 2 C, C noise = nf,. Figure 3. Quiescent Current vs. Input Voltage.8 JA, JUNCTIONTOAMBIENT THERMAL RESISTANCE ( C/W) JA, 2 oz CU Thickness JA, 2 oz CU Thickness P D(MAX), T A = 2 C 2 oz CU Thickness P D(MAX), T A = 2 C oz CU Thickness P D(MAX(, MAXIMUM POWER DISSIPATION (W) 2 3 PCB COPPER AREA (mm 2 ) 7 8 Figure 3. Thermal Resistance and Maximum Power Dissipation vc. Copper Area (WDFN)

11 NCP7C APPLICATIONS INFORMATION General The NCP7C is a high performance 2 ma low dropout linear regulator. This device delivers excellent noise and dynamic performance consuming only 7 A (typ) quiescent current at full load, with the PSRR of (typ) 82 db at khz. Excellent load transient performance and small package size makes the device ideal for portable applications. Logic EN input provides ON/OFF control of the output voltage. When the EN is low the device consumes as low as typically. A. Access to the major contributor of noise within the integrated circuit Bandgap Reference is provided through the BYP pin. This allows bypassing the source of noise by the noise reduction capacitor and reaching noise levels below V RMS. The device is fully protected in case of output short circuit condition and overheating assuring a very robust design. Input Capacitor Requirements (C IN ) It is recommended to connect a F ceramic capacitor between IN pin and GND pin of the device. This capacitor will provide a low impedance path for unwanted AC signals or noise present on the input voltage. The input capacitor will also limit the influence of input trace inductances and Power Supply resistance during sudden load current changes. Higher capacitances will improve the line transient response. Output Capacitor Requirements (C OUT ) The NCP7C has been designed to work with low ESR ceramic capacitors on the output. The device will also work with other types of capacitors until the minimum value of capacitance is assured and the capacitor ESR is within the specified range. Generally it is recommended to use F or larger XR or X7R ceramic capacitor on the output pin. Noise Bypass Capacitor Requirements (C NOISE ) The C NOISE capacitor is connected directly to the high impedance node. Any loading on this pin like the connection of oscilloscope probe, or the C NOISE capacitor leakage will cause a voltage drop in regulated output voltage. The minimum value of noise bypass capacitor is nf. Values below nf should be avoided due to possible TurnOn overshoot. Particular value should be chosen based on the output noise requirements. Larger values of C NOISE will improve the output noise and PSRR but will increase the regulator TurnOn time. Enable Operation The enable function is controlled by the logic pin EN. The voltage threshold of this pin is set between. V and.2 V. Voltage lower than. V guarantees the device is off. Voltage higher than.2 V guarantees the device is on. The NCP7C enters a sleep mode when in the off state drawing less than typically. A of quiescent current. The internal M pulldown resistor (R PD ) assures that the device is turned off when EN pin is not connected. The device can be used as a simple regulator without use of the chip enable feature by tying the EN to the IN pin. TurnOn Time The TurnOn time of the regulator is defined as the time needed to reach the output voltage which is 98% V OUT after assertion of the EN pin. This time is determined by the noise bypass capacitance C NOISE and nominal output voltage level V OUT according the following formula: V OUT [V] t ON [s] C NOISE [F] 8 [A] Example: Using C NOISE = nf, V OUT = 3 V,, (eq. ) t ON 9 3. ms 8 The TurnOn time is independent of the load current and output capacitor C OUT. To avoid output voltage overshoot during TurnOn please select C NOISE nf. Current Limit Output Current is internally limited within the IC to a typical 3 ma. The NCP7C will source this amount of current measured with a voltage mv lower than the typical operating output voltage. If the Output Voltage is directly shorted to ground (V OUT = V), the short circuit protection will limit the output current to 32 ma (typ). The current limit and short circuit protection will work properly up to V IN =. V at T A = 2 C. There is no limitation for the short circuit duration. Thermal Shutdown When the die temperature exceeds the Thermal Shutdown threshold (T SDU C typical), Thermal Shutdown event is detected and the output (V OUT ) is turned off. The IC will remain in this state until the die temperature decreases below the Thermal Shutdown Reset threshold (T SDU 3 C typical). Once the IC temperature falls below the 3 C the LDO is turnedon again. The thermal shutdown feature provides the protection from a catastrophic device failure due to accidental overheating. This protection is not intended to be used as a substitute for proper heat sinking. Reverse Current The PMOS pass transistor has an inherent body diode which will conduct the current in case that the V OUT > V IN. Such condition could exist in the case of pulling the V IN voltage to ground. Then the output capacitor voltage will be partially discharged through the PMOS body diode. It have been verified that the device will not be damaged if the output capacitance is less than 22 F. If however larger output capacitors are used or extended reverse current

12 NCP7C condition is anticipated the device may require additional external protection against the excessive reverse current. Output Noise If we neglect the noise coming from the (IN) input pin of the LDO, the main contributor of noise present on the output pin (OUT) is the internal bandgap reference. This is because any noise which is generated at this node will be subsequently amplified through the error amplifier and the PMOS pass device. Access to the bandgap reference node is supplied through the BYP pin. For the.8 V output voltage option Noise can be reduced from a typical value of Vrms by using nf to less than Vrms by using a nf from the BYP pin to ground. Minimum Load Current NCP7C does not require any minimum load current for stability. The minimum load current is assured by the internal circuitry. Power Dissipation For given ambient temperature T A and thermal resistance R JA the maximum device power dissipation can be calculated by: P D(MAX) 2 T A JA (eq. 2) For reliable operation junction temperature should be limited to +2 C. Load Regulation The NCP7C features very good load regulation of mv Max. in ma to 2 ma range. In order to achieve this very good load regulation a special attention to PCB design is necessary. The trace resistance from the OUT pin to the point of load can easily approach m which will cause 2 mv voltage drop at full load current, deteriorating the excellent load regulation. Power Supply Rejection Ratio The NCP7C features excellent Power Supply Rejection ratio. The PSRR can be tuned by selecting proper C NOISE and C OUT capacitors. In the frequency range from Hz up to about khz the larger noise bypass capacitor C NOISE will help to improve the PSRR. At the frequencies above khz the addition of higher C OUT output capacitor will result in improved PSRR. PCB Layout Recommendations Connect the input (C IN ), output (C OUT ) and noise bypass capacitors (C NOISE ) as close as possible to the device pins. The C NOISE capacitor is connected to high impedance BYP pin and thus the length of the trace between the capacitor and the pin should be as small as possible to avoid noise pickup. In order to minimize the solution size use 2 or 3 capacitors. To obtain small transient variations and good regulation characteristics place C IN and C OUT capacitors close to the device pins and make the PCB traces wide. Larger copper area connected to the pins will also improve the device thermal resistance. The actual power dissipation can be calculated by the formula: P D VIN V OUT IOUT V IN I GND (eq. 3) Line Regulation The NCP7C features very good line regulation of.mv/v (typ). Furthermore the detailed Output Voltage vs. Input Voltage characteristics show that up to V IN = V the Output Voltage deviation is typically less than 2 V for.8 V output voltage option and less than V for higher output voltage options. Above the V IN = V the output voltage falls rapidly which leads to the typical. mv/v. ORDERING INFORMATION Device Nominal Output Voltage Marking Package Shipping NCP7CMTTBG. V T WDFN (PbFree) 3 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8/D. 2

13 NCP7C PACKAGE DIMENSIONS WDFN.x.,.P CASE BJ ISSUE B 2X PIN ONE REFERENCE. C 2X. C NOTE. C. C D ÍÍÍ ÍÍÍ TOP VIEW DETAIL B SIDE VIEW A A3 A B E A EXPOSED Cu C SEATING PLANE L DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS ÉÉÉ MOLD CMPD L A DETAIL B ALTERNATE CONSTRUCTIONS A3 ÉÉÉ NOTES:. DIMENSIONING AND TOLERANCING PER ASME Y.M, CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN. AND.3mm FROM TERMINAL TIP.. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS DIM MIN MAX A.7.8 A.. A3.2 REF b.2.3 D. BSC E. BSC e. BSC L.. L ---. L2..7 RECOMMENDED MOUNTING FOOTPRINT* X X.3.73 DETAIL A 3 e X L.8 L2.83. PITCH DIMENSIONS: MILLIMETERS BOTTOM VIEW X b. C. C A B NOTE 3 *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 3, Denver, Colorado 827 USA Phone: or 8338 Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative NCP7C/D