MS Diploma and Semester Projects offered at the Microelectronic Systems Laboratory during the winter

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1 v1.1 as of MS Diploma and Semester Projects offered at the Microelectronic Systems Laboratory during the winter Students are asked to contact the project responsible to register. The majority of the projects are proposed as MS Diploma and Semester, and the amount of work will be adapted. Also, some projects can be carried out in groups of two students. Projects are proposed in six categories in the following pages. Analog and mixed-signal circuits Digital circuits and modeling Bio-electronic interfaces and biomedical applications Fabrication technologies Industrial projects / external projects (for MSc diploma) Application development (software development) 1/10

2 Analog and mixed-signal circuits A1 Exploring the Self-Heating Characteristics of Deep Sub-Micron Devices The self-heating behaviors of modern MOSFET devices will be investigated on TCAD tool of Synopsys. Different device geometries will be modeled by using the Structure Editor software. Their electo-thermal properties will be analyzed on SDevice tool. The main targets are - Observation and comparison the different self-heating rates and peak temperature values on different device geometries (bulk, FDSOI etc.) in DC and transient - Simulation of the thermal vias for decreasing the device peak temperatures - Transient simulation of differential pairs for observing the temperature induced input referred offset voltage The software tools and simulators are very well documented: Moreover, similar work has already been performed and reported: pdf Therefore the candidate can easily advance in the beginning. Supervisor Assistant: Can BALTACI Supervisor Professor: Yusuf LEBLEBICI A2 Effort Breakdown: Main: Device Level Simulations on TCAD 80% Supplementary: Circuit Simulations on Cadence 10%. Matlab, Excel 10% Exploring the Self-Heating Effects on the Noise Figure Performances of LNAs The self heating is an important problem especially in modern technologies such as FDSOI where the device temperatures increase significantly at higher frequencies and high bias currents. High temperature translates into higher thermal and flicker noise in MOSFET devices. In this project, the noise performance of LNA blocks will be analyzed by considering the selfheating effect of the LNA itself. LNAs will be optimized by providing the optimum bias conditions and device sizing for having the lowest operating temperature due to self-heating and lower Noise Figure. For that, different LNA blocks will be implemented and taped-out in 28nm FDSOI technology. Supervisor Assistant: Can BALTACI Supervisor Professor: Yusuf LEBLEBICI A3 Effort Breakdown: Main: Circuit Design in Cadence (Schematic, Simulations, Layout) 75% Supplementary: RF Simulations on ADS or Momentum 25% Implementation and Electro-thermal Analysis of a High Speed 64-bit Adder A high speed (less than 100ps REG-REG delay) 64-bit parallel prefix adder will be implemented in 28nm FDSOI technology. The heat generation sources of the implemented adder will be extracted for performing high resolution thermal simulations. The implemented adder will be simulated for FDSOI and bulk thermal geometries to obtain the temperature maps to observe the peak temperatures. Finally the FDSOI and bulk temperature maps will be compared for 28nm FDSOI. With this project the student will be able to get familiar with an advanced technology node (28nm FDSOI) and work on a wide range of topics (full custom digital design, thermal analysis and simulations, self-heating in nanometer scale devices). Supervisor Assistant: Can BALTACI Supervisor Professor: Yusuf LEBLEBICI 2/10

3 A4 Effort Breakdown: Main: Circuit Design in Cadence (Schematic, Simulations, Layout) 80% Supplementary: Matlab, HotSpot (Thermal Simulator) 20% Design and Implementation of a Single-Sideband Wireline Serial Link Transceiver for Multi- Drop I/O A fast growth of data generated by everything all around us at all the time, leading the era of bigdata, requires explosively increasing input/output (I/O) bandwidth of data communication systems. In addition, systems running memory-intensive applications, such as workstation-level computing systems and high-end video game consoles require ever-increasing memory bandwidth. While on-chip circuit bandwidth is improved by process technology node shrinkage, I/O interconnects raise as bandwidth and power efficiency bottleneck of the entire system. High-speed transceivers (TRXs) including equalization circuits for high-speed electrical links in the interfaces of such systems enable fast and power-efficient data transfer among integrated circuits. In this project, the student will design and implement a single-sideband wireline serial link TRX for multi-drop interfaces such as dual inline memory module (DIMM) for DRAM interfaces. The student will first model a single-sideband wireline serial link system using MATLAB, then design and implement (schematic + layout) the modeled TRX in 28-nm CMOS. Project for MSc diploma students (4 months) Effort breakdown: 20% Literature study 10% MATLAB modeling 40% Schematic design and simulation 30% Layout design A5 Contact/Supervisor in charge: Gain Kim (gain.kim@epfl.ch) Responsible Professor: Yusuf Leblebici Design and Implementation of a Multi-Tone/Single-Sideband Serial Link Transceiver for Lossy Wireline Data Links Ever-increasing amount of data generated by all the connected devices all around the world drive the era of big data. This trend does not only require fast enhancement of processing capability of processing units, but also explosive increase of input/output (I/O) bandwidth for communicating among the connected devices. In addition to this, many-core computing systems for heavy computing tasks require very high bandwidth I/O links to communicate from one chip to other chips. While intra-chip communication bandwidth is improved by fabrication process technology improvement, inter-chip links remain as power efficiency and communication speed bottleneck of the entire system. Therefore, serial link transceivers (TRXs) with high-bandwidth and low energy consumption are essential in next-generation wireline I/Os. In this project, the student will design and implement a multi-carrier single-sideband serial link TRX for lossy wireline data link applications such as server backplane systems. The student will first model a multi-carrier single-sideband serial link system using MATLAB, then design and implement (schematic + layout) the modeled TRX in 28-nm CMOS. Project for MSc diploma students (4 months) Effort breakdown: 20% Literature study 10% MATLAB modeling 3/10

4 40% Schematic design and simulation 30% Layout design A6 Contact/Supervisor in charge: Gain Kim Responsible Professor: Yusuf Leblebici Design and Implementation of a Multi-Drop I/O Wireline Transceiver with Crosstalk and ISI Reduction Property in Multi-Drop Memory Interfaces The demand for higher data bandwidth necessitates a rapid improvement in I/O performance. However,equalizing the channel impairments remains as the major throughput bottleneck in today s high-performance computing era. Memory system employing dual in-line memory modules (DIMMs) are a good example for such a paradigm. The multi-drop nature of DIMM interfaces and crosstalk (Xtalk) between closely spaced memory channels require complex equalization circuitry. For multi-drop bus (MDB) DIMM interfaces, employing multi-tone (MT) signaling offers a lowpower solution to reduce the receiver (RX) complexity, diminish the Xtalk, and ameliorate power efficiency. Therefore, a simple digital coding scheme to shape the transmitter (TX) spectrum according to the MDB notches while the aggregate data rate is kept fixed for different channel configurations has been developed. In this project, the student will design and implement the proposed transceiver (TRX). The student will first perform circuit-level simulations and once validated, design a full-custom layout in 28-nm CMOS. Project for MSc diploma/semester project students (4 months) Effort breakdown: 20% Literature study 50% Schematic design and simulation 30% Layout design Contact/Supervisor in charge: Gain Kim (gain.kim@epfl.ch) Responsible Professor: Yusuf Leblebici 4/10

5 Digital circuits and modeling D1 - D2 - D3 - D4 - D5-5/10

6 Bio-electronic interfaces and biomedical applications B1 Ultra low-voltage, low-power biomedical interface design based on switched-mode operational amplifier The target of this project is to design neural recording system with supply voltage down to 0.5V and low-power consumption for next generation implant. The design strategy is to employ a novel timedomain signal processing circuit called switched-mode operational amplifier (SMOA) to replace the conventional OTA based design. In SMOA, voltage swing of signals is encoded into pulse width using a PWM modulator, which benefits from higher time resolution in scaled technology. Both theoretical and practical part will be explored in this project. Effort breakdown: 30% literature survey, 70% full custom circuit design Supervisor in charge: Wen-Yang Hsu Responsible teacher: Alexandre Schmid B2 Epilepsy Feature Extraction Using Support Vector Machine (SVM) Machine learning is the study of pattern recognition and computational learning theory in artificial intelligence. It has different applications such as finance, E-commerce, web-search, space exploration, robotics, etc. In this project, our goal is to detect the epilepsy by means of a supervised learning which is defined as a type of learning that the computer is presented with example inputs and their desired outputs, given by a "teacher", and the goal is to learn a general rule that maps inputs to outputs. The student should be able to: 1) Implement the SVM on the FPGA. 2) Implement the SVM using 0.18 um technology. Project cut-down: 20% literature review 25% FPGA programming 20% Design and simulation using 0.18 um UMC 35% Full-custom layout using 0.18 um UMC contact person: Reza Ranjandish (reza.ranjandish@epfl.ch) Responsible Professor: Alexandre Schmid B3-6/10

7 Fabrication technologies N1 Characterization and Optimization of Thermo-Compresive Parylene-C Bonding The increasing need for faster and smaller integrated circuits has resulted in continuous downscaling in transistor sizes. A new technology, namely 3D integration, has emerged since the conventional planar IC fabrication has almost reached its limits. This technology facilitates the integration of both identical (homogeneous) and heterogeneous layers. Therefore, it enables reaching higher volumetric densities and stacking different chips produced by dedicated IC technologies. Parylene-C has been used as an adhesive layer for bonding in our group in 3D integration processes. This project aims to investigate the bonding strength of parylene-c layer under different bonding conditions such as temperature and pressure. This project gives the student an opportunity of hands-on fabrication experience in the cleanroom. Experimental results may also be published in a scientific paper. Project for Semester/MSc Diploma Students Project Cutdown 60% Fabrication in the Cleanroom 40% Functionality and Characterization Testing N2 Contact: Seniz Esra Kucuk (seniz.kucuk@epfl.ch) Supervisor: Y. Leblebici A New Approach of TSV Fabrication for Multilayer Stacking The increasing need for faster and smaller integrated circuits has resulted in continuous downscaling in transistor sizes. A new technology, namely 3D integration, has emerged since the conventional planar IC fabrication has almost reached its limits. This technology facilitates the integration of both identical (homogeneous) and heterogeneous layers. Therefore, it enables reaching higher volumetric densities and stacking different chips produced by dedicated IC technologies. Multilayer (more than two layers) stacking has been a prodominant field in the 3D integration processes. New approaches are needed to increase multilayer stacking performance. This project aims to investigate a new approach to be applied on multilayer stacks as well as giving an opportunity to work in the cleanroom. Project for MSc Diploma Students 20% Design 60% Fabrication in the Cleanroom 20% Functionality and Characterization Testing N3 Contact: Seniz Esra Kucuk (seniz.kucuk@epfl.ch) Supervisor: Y. Leblebici Electrical Modeling of Copper Interconnects (TSVs) The increasing need for faster and smaller integrated circuits has resulted in continuous downscaling in transistor sizes. A new technology, namely 3D integration, has emerged since the conventional planar IC fabrication has almost reached its limits. This technology facilitates the integration of both identical (homogeneous) and heterogeneous layers. Therefore, it enables reaching higher volumetric densities and stacking different chips produced by dedicated IC technologies. Through-silicon-vias are one of the key elements in 3D integration technology since they are used to electrically connect the chips to each other. Therefore, modeling and characterization of these metal interconnects plays a vital role in this research topic. 7/10

Leblebici Fabrication and Characterization of Metal Oxide ReRAM Memory Cells Resistive Random Access Memories (ReRAM) are a class of emerging non volatile memories characterized by low operating

8 The purpose of this project is to model the RLC parameters of the TSV as a function of material characteristic and physical parameters. Project for Semester/MSc Diploma Students Project Cutdown 10% Literature Search 90% Modeling N4 Contact: Seniz Esra Kucuk (seniz.kucuk@epfl.ch) Supervisor: Y. Leblebici Fabrication and Characterization of Metal Oxide ReRAM Memory Cells Resistive Random Access Memories (ReRAM) are a class of emerging non volatile memories characterized by low operating voltage, high scalability, high endurance and compatibility with standard CMOS processes. The aim of this project is to investigate the influence of specific process variations (e.g. oxide type and thickness, buffer layers, annealing steps) on the memory cell electrical performances. The student will experience a complete device development flow. This will include process design, device fabrication in a class 100 cleanroom and electrical characterization. Project for MSc Diploma Students 10% Design 70% Fabrication in the cleanroom 20% Electrical characterization Contact: Jury Sandrini (jury.sandrini@epfl.ch) Supervisor: Y. Leblebici 8/10

9 Industrial projects / External projects (MSc diploma) IE1 EM Microelectronic is proposing a number of internships that could be of interest for EE/CS students in your organization. The topics can be found at the link below and we would very much appreciate if you could help inform your students regarding these opportunities. Internships can potentially and in agreement with the student and his thesis advisor be extended into an M.Sc. thesis project. Interested students should submit application letter and resume (CV) as soon as possible: Recruiting@emmicroelectronic.com As an EPFL registered internship or MSc diploma, please also contact one of the following possible supervisor: Y. Leblebici, A. Vachoux, A. Schmid 9/10

10 Application development (software development) SW1 - SW2-10/10

Transmission-Line-Based, Shared-Media On-Chip. Interconnects for Multi-Core Processors

Design for MOSIS Educational Program (Research) Transmission-Line-Based, Shared-Media On-Chip Interconnects for Multi-Core Processors Prepared by: Professor Hui Wu, Jianyun Hu, Berkehan Ciftcioglu, Jie