Low-Power RF Circuit Design and Built-In Test Current Generation Techniques for Wireless Chips in Emerging Sensing Applications

Transcription

1 Low-Power RF Circuit Design and Built-In Test Current Generation Techniques for Wireless Chips in Emerging Sensing Applications A Thesis Presented by Li Xu to The Department of Electrical and Computer Engineering in partial fulfillment of the requirement for the degree of Master of Science in Electrical Engineering Northeastern University Boston, Massachusetts March, 2016

2 Abstract Significant improvements of low-cost energy-efficient integrated circuit designs with sensing, analog signal processing, power management, computation, and communication functions are required to support the envisioned Internet of Things (IoT). Considering the goal to produce more portable wireless terminals and devices that communicate with each other, a critical obstacle is that radio frequency (RF) front-ends consume excessive power in many emerging wireless devices. It is essential and challenging to create novel analog circuit design techniques with significant power reductions while maintaining adequate performance. Another trend is that soaring wireless connections and the associated interference signals increase the demand for highly linear analog circuits in receivers to avoid that the desired signals are distorted by unwanted mixing with interference signals. This problem motivates research efforts to improve the third-order intermodulation performance of RF front-end circuits to minimize signal distortions. The design approaches developed in this thesis work simultaneously address the challenges of achieving low power consumption and high linearity, especially for RF front-end circuits operating with supply voltages below 1V and having power consumptions below 1mW. In particular, this research focuses on a linearization technique for low-power active mixers, which are often the bottleneck of the overall linearity performance in RF receiver front-ends. The concepts are demonstrated with a 2.4GHz RF front-end composed of a low-noise amplifier and mixer. This RF front-end was designed and fabricated in 130nm complementary metal-oxide semiconductor (CMOS) technology. It consumes 0.77mW with a 0.7V supply voltage, while having a measured in-band third-order intermodulation intercept point (IIP3) of -4.5dBm, a noise figure (NF) of 6.3dB, and a spurious-free dynamic range (SFDR) up to 62.8dB. Another aim of this research has been to create circuits for the realization of nextgeneration portable wireless medical monitoring systems. Towards this goal, an on-chip test current generator was designed and integrated into an analog front-end with input impedance self-calibration for electroencephalogram (EEG) signal measurements. The test current generator includes a temperature-compensated relaxation oscillator, a limiter, and a custom operational transconductance amplifier (OTA) with sub-nanosiemens transconductance and high output impedance. The test current generator enables the I

3 injection of a 1pA alternating current into the inputs of an instrumentation amplifier for input impedance estimation based on current injection combined with amplitude detection. The test current generator was designed and fabricated in 130nm CMOS technology, and its functionality was validated with measurements of a test chip that includes the circuits in the signal path of the analog front-end for EEG monitoring applications. Acknowledgements It is difficult for me to believe that my time at Northeastern has come to an end. My experience at Northeastern has been an amazing journey that has shaped my life in many different ways. My experience as a graduate student has been academically challenging, enjoyable and fulfilling at the same time. The past few years would not have been what they were without the help and support of many people. Thank you to all! First, I would like to thank my parents. Without their support (both financial and in spirit), I would not have had the courage and ease to resign from a decent job, apply to graduate school in the U.S., and now apply for Ph.D. studies. In the past two years, my family has always been a constant source of encouragement and understanding. Words cannot express how grateful I am. It was serendipity that I could join the Analog and Mixed-Signal Integrated Circuit Research Laboratory and meet Professor Marvin Onabajo at the beginning of my first semester at Northeastern. He has been a great mentor and teacher and has provided constant and generous support. I have been given freedom and opportunities to pursue different paths in research and I thank him for trusting me. I have learned many things from him in engineering as well as how to be a kind person. I would like to thank Professor Yong-Bin Kim and Professor Nicol E. McGruer for being on my thesis committee. I want to thank Professor Yong-Bin Kim for his excellent teaching of EECE7240 Analog Integrated Circuit Design and EECE7353 VLSI Design, where I rebuilt my understanding of basic analog circuits and digital design. I would like to thank Professor Nian X. Sun for lending us the second RF signal generator for the two-tone testing of the low-power RF front-end, and I really appreciate his comments and advice through my group members and project collaborators Chun-hsiang II

4 Chang and Kainan Wang. I would also like to thank Professor Matteo Rinaldi for his teaching and advice in EECE7244 Microelectromechanical Systems. My warmest gratitude goes to Professor Milica Stojanovic, a great teacher and nice mentor. She has supported me in many different ways and has always been there for help and advice. She is one of the kindest and most respectable people I have come to know here at Northeastern. Thank you! Words can hardly do justice in showing the extent of my gratitude to many friends that I have been blessed with knowing at Northeastern or before. My warmest thanks go to Chun-hsiang Chang, a Ph.D. student in our group from whom I learned so many circuit design techniques and how to face problems with calmness. Also, I must thank Kainan Wang who has been my best partner in many course and research projects. It was Chun-hsiang s selfless sharing and Kainan s support that made the mixer design possible. As an important part of my M.S. program, the summer internship at Linear Technology in Colorado Springs was unforgettable. I would like to thank my supervisor, Mr. Mathew Wich, for being so supportive and kind-hearted. In particular, thank you for helping me to test the temperature performance of the relaxation oscillator with the X- STREAM 4300, as well as for all your guidance and advice. I hope to work with you again in the future. I would like to thank Jiawei Xu (Delft University of Technology Ph.D. candidate in collaboration with IMEC) for kindly sharing the idea for indirect measurement of the instrumentation amplifier input impedance. I would like to thank Yuchi Ni and Junpeng Feng for collaborating during the early phase of the test signal generator design. Furthermore, I would like to thank Alireza Zahrai, Chun-hsiang Chang, and Kainan Wang for collaborating on the SCAFELAB project. Finally, I would like to thank Ms. Faith Crisley, who is such a kind graduate coordinator and has helped me tremendously during my time at Northeastern. III

5 Table of Contents Abstract... I Acknowledgements... II 1. INTRODUCTION Subthreshold Low-Power RF Front-End Circuit Design Digitally-Assisted Input Impedance Calibration of Analog Front-Ends for EEG Signal Measurement Applications Thesis Contributions Thesis Organization LOW-POWER RF FRONT-END DESIGN Linearization Technique for Low-Power Active Mixers Linearity Analysis Conversion Gain Analysis Simulation Results Conclusions based on Mixer Simulation Results V 2.4GHz RF Front-End Design Design Techniques Measurement Results Conclusion ON-CHIP TEST CURRENT GENERATION CIRCUITS FOR INPUT IMPEDANCE CALIBRATION OF ANALOG FRONT-ENDS FOR BIOSIGNAL MEASUREMENTS On-Chip Calibration System Low-Power Temperature-Compensated Relaxation Oscillator Design Antecedent Circuit Description Proposed V T -Based Compensation Technique Simulation Results and Discussion Oscillator Measurement Results IV

6 3.2.5 Frequency Divider Design Limiter Design Custom OTA Topology Sub-Nano-Siemens Transconductance Design Design of an OTA Output Stage With High Output Impedance, Low Noise, and High PSRR Simulation Results Prototype Chip Measurements Input Impedance Test Setup Manual Input Impedance Calibration with an External Test Signal Built-In Input Impedance Test with Current Injection Conclusion CONCLUSION AND FUTURE WORK REFERENCES V

7 List of Figures Fig. 1 The effect of intermodulation distortion due to the presence of multiple transceivers Fig. 2 Schematic of the linearized subthreshold LNA in [14]... 3 Fig. 3 Conventional mixer with annotated parasitic capacitance C p Fig. 4 Linearized mixer with inductors and cross-coupling capacitors in [13] Fig. 5 General negative impedance converter Fig. 6 Proposed mixer with inductorless IIP3 enhancement Fig. 7 Analog front-end for EEG signal measurements with active electrodes to drive the capacitances from the electrode cables Fig. 8 Analog front-end for EEG signal measurements with electrode cable capacitances and calibration blocks for input impedance boosting Fig. 9 Amplitude-based impedance detection with comparators and latches Fig. 10 Proposed mixer with inductorless IIP3 enhancement Fig. 11 Small-signal model of the proposed mixer Fig. 12 Equivalent half-circuit of the small-signal model in Fig Fig. 13 Small-signal model for IIP3 evaluation using Volterra series Fig. 14 Calculated ε( ω,2ω) vs. C C at different f RF Fig. 15 Small-signal model for conversion gain analysis Fig. 16 Calculated conversion gain vs. C C at different f RF Fig. 17 Layout of the mixer core Fig. 18 Key performance parameters over the GHz frequency range (conversion gain, IIP3, and SSB NF with IF = 10MHz) Fig. 19 Schematic of the proposed low-power RF front-end Fig. 20 (a) Phase and amplitude of signals at terminals of C C. (b) Negative capacitance generation and input capacitance resonance Fig. 21 LC filters formed by C C and LNA load tanks Fig. 22 IM2/IIP2 considerations related to C C and the LNA load tank Fig. 23 Die photo of the RF front-end in a QFN-24 package Fig. 24 Printed circuit board for testing of the RF front-end VI

8 Fig. 25 (a) Test setup for the RF front-end. (b) Measured output voltage signals at the 10MHz intermediate frequency (with a power of -27dBm at the LNA input). (b) Simulated output voltage signals at the 10MHz intermediate frequency (with a power of -27dBm at the LNA input) Fig. 26 (a) IIP3 of the RF front-end, (b) IM3 dbc with input power of -31.5dBm (including 10.3dB loss from the buffer stage), (c) IM3 dbc versus mixer supply current, (d) IM3 dbc versus IF frequencies Fig. 27 Measured (a) voltage gain from LNA input to mixer output (with IF = 10MHz) and S11, (b) voltage gain and NF versus LO power, (c) 1dB-compression curve, (d) IIP Fig. 28 Analog front-end for EEG signal measurements with electrode cable capacitances and calibration blocks for input impedance boosting Fig. 29 Relaxation oscillator from [44] Fig. 30 Proposed relaxation oscillator concept with the V PTAT Fig. 31 Complete schematic of the proposed relaxation oscillator Fig. 32 Variations of I 1 and V Cmax - V Cmin vs. temperature Fig. 33 Simulated V O, V C, and V OSC waveforms (frequency = 40kHz) Fig. 34 Output frequency variation vs. temperature (different corner models) Fig Monte Carlo (MC) simulation samples with process variations Fig Monte Carlo (MC) simulation samples with mismatches Fig. 37 Measured oscillator output waveform and frequency at 25ºC Fig. 38 Measured oscillator output frequency vs. temperature variation Fig. 39 Measured oscillator output waveform and frequency at (a) -30ºC and (b) 25ºC. 48 Fig. 40 Measured oscillator output frequency variations Fig. 41 Measured cycle-to-cycle jitter of the oscillator Fig. 42 Oscillator measurement setup with off-chip buffer Fig. 43 Frequency divider (with standard D flip-flops designed on the transistor level). 50 Fig. 44 Schematic of the differential voltage limiter Fig. 45 Simulated differential output voltage (V o1 - V o2 ) of the limiter (typical corner case, 27 C) VII

9 Fig. 46 Schematic of the (a) OTA core, (b) bias current generation structure of the OTA (N = 10), and (c) bias voltage generation structure of the OTA Fig. 47 Simulated differential output voltage of the test signal generator with a load capacitance of 3pF and transient noise enabled ( Hz range) for all devices Fig. 48 Proposed biasing circuit for the OTA s output stage Fig. 49 Output impedance vs. frequency of the OTA with process and temperature variations Fig. 50 Voltage swings at the IA input with current injection from the OTA for two cases: i.) with NCGFB, ii.) without NCGFB. (Noise was activated during the transient simulations based on the integrated noise density from 0.01Hz to 100Hz.) Fig. 51 Micrograph of the test current generator: (a) with EEG front-end blocks, (b) zoomed-in view Fig. 52 Printed circuit board design for the self-calibrated EEG analog front-end Fig. 53 Indirect input impedance measurement with test resistors Fig. 54 Measured waveform (V OUT ) at the IA s output with R TEST = 0 and C in = 100pF Fig. 55 Measured V OUT waveform at the IA s output with R TEST = 5MΩ and C in = 100pF with different codes: (a) , (b) , and (c) Fig. 56 Input impedances for various tuning codes: (a) C in = 50pF, (b) C in = 100pF, (c) C in = 150pF Fig. 57 Current injection with the test current generator Fig Hz frequency divider output signal (20kHz oscillator divided by 512) for the digital calibration control logic circuits Fig. 59 Sawtooth waveforms at the IA output with C in = 100pF and different tuning codes: (a) , (b) , and (c) VIII

10 List of Tables Table 1 Key mixer parameters of the proposed mixer with V dd = 0.6V Table 2 Performance summary of the proposed mixer and comparison with the state-ofthe-art Table 3 Performance summary of the RF-front-end and comparison with the state-of-theart Table 4 Oscillator performance summary and comparison with the state-of-the-art Table 5 Simulated differential output voltage swing of the limiter and phase margin in its regulation loop (IBM 130nm CMOS process) Table 6 OTA simulation results IX

11 1. INTRODUCTION Many ongoing developments of low-power integrated circuits are motivated by the all-encompassing goal to create the Internet of the Things (IoT), in which portable devices will be connected to each other through wireless communication links. Diverse low-power wireless standards and circuit design approaches have been developed for low-rate wireless personal area network (WPAN) and wireless body area network (WBAN) communication [1]-[5]. Their range of applications spans health and fitness monitoring, wireless sensor nodes, automated payments, and smart home applications. The associated standards include IEEE , IEEE , Bluetooth low energy (BLE), Near Field Communication (NFC), and Global Positioning System (GPS). A major challenge is that radio frequency (RF) front-end modules can consume more than 60% of the power budget in transceivers [6]. It is essential and challenging to create novel analog circuit design techniques with significant power reductions while keeping sufficient performance. Current-reuse structures [7] and folded structures with on-chip transformers [8] provide promising solutions for ultra-low power front-ends. However, the linearity performance is typically compromised as a result of low-power and low-voltage design. Methods using a passive gain stage instead of the classic lownoise amplifier (LNA) combined with a passive mixer [9] or a passive mixer-first structure [10] can realize high linearity with minimal power, but the associated low front-end gain augments the noise contribution from the subsequent baseband stages. The increasing number of IoT devices with wireless connections create interference signals that require RF receivers with high linearity. In RF front-end circuits, the thirdorder intermodulation products due to receiver nonlinearities have be minimized to avoid that interference signals corrupt the desired signal. This leads to circuit design challenges, especially when designing with sub-1v supply voltage and sub-mw power consumption that lead to reduced voltage headroom and degraded transistor transconductance values. Consider the scenario in Fig. 1 as example, in which the receiver is designed to receive signals at 2.4GHz using a local oscillator with a frequency of 2.39GHz, which results in an intermediate frequency of 10MHz. However, due to the intermodulation of the interference signals (at 2.41GHz and 2.42GHz), a noise signal is created in the same frequency band as the desired signal, and this interference cannot be filtered out by the 1

12 band-pass filter (or low-pass filter) after the mixer. The ongoing improvements of filters with high quality factors after the antenna can help to attenuate the interferences at the low-noise amplifier input. However, it is difficult to realize on-chip high-q filters due to the low quality factors of inductors in CMOS technologies, and off-chip components would cause extra cost and increase the printed circuit board (PCB) size of portable wireless devices. Recently, passive mixer-first structures have been proposed for enhanced RF filtering and high linearity [11]-[12], especially with oversampling designs. However, the local oscillator (LO) signal generation for such architectures is more complicated and consumes more power compared to conventional low-power receiver designs. Fig. 1 The effect of intermodulation distortion due to the presence of multiple transceivers. 1.1 Subthreshold Low-Power RF Front-End Circuit Design Transistors operated in the subthreshold (or weak inversion) region permit minimization of power consumption in CMOS RF front-end designs. In contrast to strong inversion biasing, three distinguishing characteristics of subthreshold biasing were described in [13]-[14]: 1.) higher transconductance-to-drain-current ratio (g m /I d ) at the expense of slightly higher noise figure (NF); 2.) higher width-to-length ratio to achieve the same g m, which results in larger parasitic capacitances; 3.) a higher third-order 2

13 nonlinearity coefficient (g 3 ) that has the same sign as the linear gain (g 1 ). Over the past years, some of such LNAs and mixers were reported with very low power consumptions [5], [15]-[17], which were made possible by high transconductance-to-drain current ratios (g m /I D ) and low power supply voltages (V DD ). However, the prevalent design challenge associated with subthreshold RF front-end circuits has been linearity degradation. For example, in earlier published subthreshold LNAs and mixers [5],[15]-[17], the third-order intermodulation intercept point (IIP3) is typically below -10dBm. A low-power linearization technique for subthreshold LNAs was introduced by our research group in [14], using the LNA displayed in Fig. 2. In this circuit, a capacitor and an inductor were added to the cascode transistor, which tune the terminal impedances of the transistors to realize third-order nonlinearity cancellation. Fig. 2 Schematic of the linearized subthreshold LNA in [14]. Because the third-order intermodulation intercept point (IIP3) and noise figure of mixers are scaled by the 10-20dB gain of the low-noise amplifier (LNA) during the calculation of a typical receiver s input-referred specifications, the IIP3 of mixers is typically more critical than their noise figure, which is commonly the bottleneck of the RF front-end linearity. Fig. 3 displays a Gilbert mixer without tail current source. In subthreshold operation, M 1 -M 3 are designed with high W/L ratios to realize the same g m 3

14 as that in strong inversion. Hence, the mixer would suffer from significant conversion gain loss due to AC current leakage through the parasitic capacitance (C P ), as well as relatively high distortion from the transconductance stage (M 1 ). Fig. 3 Conventional mixer with annotated parasitic capacitance C p. In previous work [13] (Fig. 4) based on the structure in Fig. 3, an inductor was inserted between each drain of the RF transistors and the common-source node of the LO transistors to resonate with C p, and a g m -boosting structure was introduced with inductive degeneration for the RF transistors and cross-coupling capacitors between the sources of one RF transistor and the drain of the RF transistor in the other branch. Postlayout simulations of the mixer in [13] resulted in an IIP3 of 6.7dBm, a voltage gain of 8.6dB, and a single-sideband noise figure of 19.2dB with a power consumption of 0.423mW and a layout area of mm 2. The key aspect of this IIP3 enhancement method with nonlinearity cancellation is that g 3 and g 1 of the RF transistors have same sign because of the subthreshold biasing, while inductors and cross-coupling capacitors are used to cancel C p and boost the conversion gain. Nevertheless, this design occupied a large layout area because of the four inductors, and there are three passive components involved in the linearization, which make the linearization technique intricate. 4

15 Fig. 4 Linearized mixer with inductors and cross-coupling capacitors in [13]. Fig. 5 General negative impedance converter. Negative capacitance generation is a layout-efficient solution to parasitic capacitances because this method avoids the use of inductors. Fig. 5 depicts a classic negative impedance converter [18]. Negative impedance generation can be realized with a coupling impedance between two selected nodes while satisfying the phase and amplitude requirements that are visualized on the right side of Fig. 5. Applying this principle to the mixer in Fig. 3, a coupling capacitor between the drain of the RF + transistor and the gate of the RF - transistor introduces a negative impedance at the drain of the RF + transistor. Likewise, a coupling capacitor can be added between the drain of the RF - transistor and the gate of the RF + transistor, leading to the new mixer in Fig. 6. This technique is similar to the capacitive neutralization mechanism in power amplifier design [19] but 5

16 with different compensated nodes. Since the gain from the RF input to the compensated node X in Fig. 6 is less than one, the feedback loop is inherently stable. Relative to the conventional mixer architecture, the proposed subthreshold mixer configuration contains only two extra cross-coupling capacitors, providing simplicity and layout efficiency. Compared to inductive compensation [13], the negative impedance generation structure is well-suited for scenarios with wide RF bandwidth and intermediate frequency (IF) output bandwidth, making it a good candidate for multi-standard applications. Fig. 6 Proposed mixer with inductorless IIP3 enhancement. 1.2 Digitally-Assisted Input Impedance Calibration of Analog Front- Ends for EEG Signal Measurement Applications In recent years, significant progress has been made towards the use of dry-contact electrodes for biopotential measurements in long-term brain signal monitoring applications. Compared to electrodes covered with conductive gels or solutions, dry electrodes do not require preparation of the skin surface but suffer from increased contact resistances that can be above 1MΩ [20]-[21]. This brings the requirement of high input impedance at the analog front-end amplifier to above 500MΩ [22]. One approach for dry-electrode measurements is to configure an amplifier with metal-oxidesemiconductor field-effect transistor (MOSFET) input stage as unity-gain buffer at each (active) electrode [21] as shown in the left part of the Fig. 7. Instead, a goal of our research group is to enable biopotential measurements without power-consuming buffers 6

17 before the instrumentation amplifiers. For this reason, a self-calibrated analog front-end architecture has been developed in a group project to permit the use of passive dry electrodes. The focus in this thesis is on the test signal generation circuitry for the system. Fig. 7 Analog front-end for EEG signal measurements with active electrodes to drive the capacitances from the electrode cables. Fig. 8 Analog front-end for EEG signal measurements with electrode cable capacitances and calibration blocks for input impedance boosting. Fig. 8 depicts the integrated electroencephalography (EEG) front-end that includes on-chip blocks for self-calibration. Parasitic capacitances from the electrode cables, the printed circuit board, and the package could be as high as pF, which can limit the 7

18 input impedance at 100Hz to approximately 8MΩ. A negative impedance converter [18] has been integrated into the instrumentation amplifier to generate negative capacitance at its input nodes for cancellation of the parasitic capacitances. This internal negative capacitance generation circuitry is digitally programmable. Prior to the measurement, a first calibration step will be performed with open electrodes terminals in Fig. 8, where the switches S 1 and S 2 will be closed to inject differential test currents (i t ) from the operational transconductance amplifier (OTA) into both input nodes to generate a voltage swing. The calibration step will be repeated until the negative capacitance value is adjusted for sufficient input capacitance cancellation to meet the high input impedance requirement. In each cycle, the output of the lowpass and notch filter (LPF) will be monitored as visualized in Fig. 9, taking advantage of the fact that the output amplitude (with combined amplifier and LPF gain of around 100) reflects the equivalent impedance at the instrumentation amplifier input because the test current magnitude is known. The amplitude of the signal will be determined based on simulations with worst-case process-voltage-temperature variations prior to selecting the number of comparators and their reference voltage levels. At least four comparators will be used to identify the amplitude around the required peak voltage swing (with minimum acceptable input impedance). In each cycle, the latched outputs of the comparators can be interpreted as thermometer-coded representation of the front-end input impedance. Prior to the reset in every cycle, the digital calibration control block will save and compare the current code with the previous codes. The negative capacitance value will be adjusted step by step by cycling through all digital settings to identify the one that results in the maximum output voltage swing that corresponds to the maximum front-end input impedance condition. The approach avoids direct measurement of the input impedance by using low-power area-efficient circuits in an amplitude detection scheme. Even though only one comparator would be needed in the typical case to check if the LPF output amplitude is large enough for a given input impedance requirement, a bank of comparators will be used to ensure detection capability in the presence of process variations, which will be evaluated with statistical simulations. With the above calibration mechanism, the input impedance of the EEG front-end can be boosted each time before long-term EEG monitoring is started. 8

19 Fig. 9 Amplitude-based impedance detection with comparators and latches. 1.3 Thesis Contributions This thesis summarizes two main research endeavors. First, a linearization technique for low-power active mixer with cross-coupling capacitors was developed [23], which was combined with a subthreshold LNA to demonstrate low-power design techniques with high linearity performance. A test chip was designed and fabricated in 130nm IBM CMOS process technology and tested in the laboratory with experimental measurements. Second, a test current generation method is introduced in this thesis, which is part of a self-calibrated EEG analog front-end [24]. The test current generator includes a 20kHz temperature-compensated relaxation oscillator [25], a frequency divider, a limiter, and a custom operational transconductance amplifier. It can inject picoampere-range AC current into the inputs of the instrumentation amplifier to enable input impedance estimation based on current injection and amplitude detection. The test current generator was designed and fabricated in 130nm IBM CMOS process technology and measured within an analog front-end for EEG measurement applications. 9

20 1.4 Thesis Organization This thesis consists of four chapters: Chapter 1 introduced the needs for low-power RF front-end design and analog frontends for EEG signal measurements with dry-contact passive electrodes. Linearization techniques for low-power LNAs and mixers in previous works were summarized, and the proposed structure with cross-coupling capacitors was briefly discussed. In addition, analog EEG front-end design with input impedance self-calibration was described and compared with classic analog EEG front-ends using active electrodes. Chapter 2 develops the linearization technique for the low-power active mixer with cross-coupling capacitors, including the analysis of voltage gain and linearity. The proposed mixer was combined with a LNA, and design techniques of reusing the inductors in the LNA tanks are introduced. A test chip design with a LNA and mixer in 130nm CMOS technology is discussed with measurement results. Chapter 3 presents a test current generation technique that is part of a self-calibrated analog front-end for long-term EEG monitoring. The test current generator includes a 20kHz temperature-compensated relaxation oscillator, a frequency divider, a limiter, and a custom OTA. It allows injecting picoampere AC currents into the inputs of an instrumentation amplifier to enable input impedance estimation. The test current generator was fabricated in 130nm IBM CMOS process and verified with measurements. Chapter 4 concludes the thesis and discusses possibilities for future research. 10

21 2. LOW-POWER RF FRONT-END DESIGN As mentioned in Chapter 1, the linearity performance of RF front-end can be severely degraded due to the low-power and low-voltage operation. Founded on linearization techniques published by our research group [13]-[14], a novel linearization method for low-power active mixers was developed with cross-coupling capacitors in this thesis project. The new structure can generate negative capacitance to mitigate gain loss due to parasitic capacitance. At the same time, the effect can be utilized to adjust the terminal impedances of the mixer input transistor, leading to linearity improvement. These techniques are demonstrated in this chapter with a receiver front-end consisting of a subthreshold LNA and the proposed mixer topology. 2.1 Linearization Technique for Low-Power Active Mixers Fig. 10 presents the proposed low-power mixer with cross-coupling capacitors. Fig. 11 shows the small-signal model of this mixer under the assumption that the signal swings at LO + /LO - are large enough to model M 2 and M 3 as switches. The impedances looking into the source of M 2 and M 3 are approximated as 1/g m2 and 1/g m3. Since the small-signal model in Fig. 11 is a fully symmetric circuit, it can be simplified further with the equivalent half-circuit displayed in Fig. 12. Fig. 10 Proposed mixer with inductorless IIP3 enhancement. 11

22 Fig. 11 Small-signal model of the proposed mixer. Fig. 12 Equivalent half-circuit of the small-signal model in Fig. 11. The voltage at the drain of the RF transistor M 1 is defined as V X here. Z C1 is the equivalent impedance (with respect to ground) looking from the gate of M 1 through C C, while Z C3 is the equivalent impedance looking from the drain of the RF transistor through C C. Because C C introduces an equivalent impedance via feedback, the impedance at the drain of M 1 (Z 3 in the Fig. 12) can be expressed as: Z m, (1) 1 3 ( g 2 j C Y) where C is the capacitive component combining C P and the capacitive part of Z C3, and Y is the reciprocal of the resistive component due to the feedback compensation. The following equation can be obtained from current summation at node X: 12

23 ids gm 1 Vin j Cgd 1( Vx Vin) gm 1 V, (2) where C gd1 is assumed to be small (e.g., less than 100fF in the design described in Section 2.1.3) and is neglected in the above approximation. It follows that in Vx i Z g V ( g j C Y. (3) ds 1 3 m1 in m2 ) The negative impedance Z C3 due to C C can be written as: Z C3 V i x C3 jc C V [ V x x ( V in )]. (4) Using equations (1)-(4), Z 3 becomes Z ( g j C 1/ Z. (5) 1 3 m2 P C3 ) It can be shown that equations (1) and (5) are equivalent when variables C and Y are: g C C g ( g g C, (6) 2 m1 P C m1 m1 m2 ) g m1 CC 2 C Y g m1 C C. (7) It can be observed from equation (6) that the parasitic capacitance C P can be partially cancelled through the proper selection of C C depending on the difference between g m1 and g m2. Minimization of the numerator in (6) also reduces the dependence of the equivalent capacitance C at the drain of M 1 on frequency (through ω in the denominator). The impedance Z C1 in Fig. 12 can also be derived in terms of C and Y from small-signal analysis: Z C1 V i jc C1 C in ( g g m2 jc m2 C V [ V in Y g in ( V jc Y m1 x )] 2 ) CC C. (8) 13

24 2.1.1 Linearity Analysis It was shown in [26] that the third-order intermodulation (IM3) of a time-varying mixer can be estimated with one time-invariant IM3 calculation at the maximum of the LO signal. Furthermore, the linearity of the mixer is limited by the linearity of the voltage-to-current converter (M 1 in the Fig. 10) [27]. The IIP3 of the proposed mixer can be evaluated using Volterra series analysis [13]-[14], [28]: IIP 3 6R s 1 H( ) A ( ) 1 3, (9) (,2) where: (, 2) g3 g ob, (10) g ob g2 3 g g( ) g g(2), (11) 1 Z ( ) Z ( ) j C Z ( ) Z ( ) 1 j Cgd1 1 3 gs1 1 x g( ), (12) Z ( ) Z x Z 2 jcgd1[ Z1 Z 2 Z Z Z Z ] 1 x C1) , (13) Z ( ) ( jc gb 1/ Z, (14) Z ( ) 0, (15) 2 Z ( ) ( g m jc Y. (16) ) 2 In the above equations, g 1, g 2, and g 3 are the coefficients from i ds = g 1 v gs1 + g 2 v gs1 + g 3 v 3 gs1, and ω = ω RF = 2π f RF is the center frequency of the two intermodulation tones at ω RF1 and ω RF2, while ω is defined as ω RF1 -ω RF2. A 1 (ω) is the linear transfer function from V in to V gs1, R S is the reference impedance (typically 50Ω), and H(ω) is the thirdorder nonlinear transfer function from the input to the drain-source current. ε( ω,2ω) signifies how the drain current nonlinearities contribute to its IM3 response [28]. Note that g ob is a function of the impedances seen at the three terminals (gate, source, and drain) as annotated in Fig. 13. As mentioned in Section 1.1, g 3 has the same sign as g 1 14

25 for a MOSFET transistor biased in the subthreshold region. Based on equations (9)-(16), g ob can be designed to cancel g 3 for IIP3 improvement. Note that equations (14)-(16) are specific for the proposed mixer structure. The IIP3 was evaluated by plotting ε( ω,2ω) vs. cross-coupling capacitor values using the parameters (g 1 -g 3, C gb1, C gs1, C gd1 g m2, and C p ) at the operating point from a transistor-level simulation of the mixer design in Section Fig. 14 displays the results, demonstrating the significant IIP3 improvement with an optimum C C value that minimizes ε( ω,2ω) in equation (9). Fig. 13 Small-signal model for IIP3 evaluation using Volterra series. Fig. 14 Calculated ε( ω,2ω) vs. C C at different f RF. 15

26 2.1.2 Conversion Gain Analysis Fig. 15 displays the small-signal model for conversion gain analysis. Two steps were taken to derive the voltage conversion gain: First, the transfer function from V gs1 to V X was derived, and i out at the drain of RF input transistor (M 1 ) was expressed using the equation for V X. From current summation at the drain of M 1 : j C ( V V ) g V V Z, (17) gd1 x gs1 m1 gs1 x / where Z 3 is defined as in equation (5). After rearrangements: 3 V V x gs1 ( gd1 m1 gd1 3 j C g ) /( jc 1/ Z ). (18) Based on the model in Fig. 15, i out can be written as i out Vx 1/ g g m2 ( jc jc gd1 1 m2 gd1 / g Z m1 3 ) V gs1. (19) As second step, the conversion gain was obtained with the same simplification as in [13], which is that the down-converted component of i out (at ω IF ) flows into the load tank (R d in Fig. 10) and a parallel parasitic capacitance at the output (C out ) to generate the output voltage, where the down-conversion is modeled with a multiplication by a square waveform: g CG ( jc g 2 m2 gd1 m1 1 1 ( jif Cout) jcgd 1 1/ Z3 Rd ). (20) Fig. 16 shows the evaluation results of the conversion gain equation vs. C C at different RF frequencies. When C C is close to zero, the cross-coupling capacitors can be regarded as an open circuit. The results demonstrate that the cross-coupling capacitor has a gain-boosting effect. 16

27 Fig. 15 Small-signal model for conversion gain analysis. Fig. 16 Calculated conversion gain vs. C C at different f RF Simulation Results The mixer in Fig. 10 was designed in 130nm CMOS technology for an RF frequency range from 2.4GHz to 11.4GHz. An LO frequency of f RF + 10MHz was employed (f RF + 264MHz for the simulation results referred to as ultra-wideband (UWB) version ). The second tone in the two-tone tests was located at f RF - 2MHz. Table 1 lists its main design parameters. All the transistors are biased in the subthreshold region. Fig. 17 displays the layout of the linearized mixer, which occupies an area of mm 2. The post-layout simulation results of the conversion gain, IIP3 and single sideband noise 17

28 figure (NF SSB ) are shown in Fig. 18 for three different C C values. The same mixer without C C was simulated for comparison, exhibiting a gain of 4.5dB, IIP3 of -2.6dBm, and NF SSB of 24.65dB at 2.4GHz, which confirms the improvement. There is a trade-off between input impedance at the RF + /RF - terminals and the performance-boosting effects of the cross-coupling capacitors. Even though the value of C c and the operating point of the RF transistors can be carefully selected for optimum performance, there will be a fF increase of the equivalent capacitance at the RF inputs due to Z C1 in Fig. 12, which is expressed in equation (8). Nevertheless, this mixer input capacitance increase can be accounted for during the design of the preceding low-noise amplifier; e.g., by reducing the capacitance in the inductor-capacitor load tank or by increasing the driving capability of a broadband low-noise amplifier. Table 2 summarizes the simulated performance in comparison to state-of-the-art low-power mixers. The proposed mixer has competitive performance based on the figure of merit (FOM) from [29], while consuming 0.373mW and occupying a layout area of only mm 2 thanks to the absence of inductors. Table 1 Key mixer parameters of the proposed mixer with V dd = 0.6V Design Parameter Value I SS 0.576mA RF_DC 0.368V LO_DC 0.430V C C R d W/L (M 1 ) W/L (M 2, M 3 ) 2.8pF 1kΩ 300μm / 0.12μm 300μm / 0.12μm 18

29 Fig. 17 Layout of the mixer core. Fig. 18 Key performance parameters over the GHz frequency range (conversion gain, IIP3, and SSB NF with IF = 10MHz). 19

30 Table 2 Performance summary of the proposed mixer and comparison with the state-of-the-art Reference [30]* [31]* [32]* [33] # [13] # This Work # This Work # UWB Version V DD [V] Bandwidth [GHz] 3.1 ~ ~ ~ ~ 10.6 RF [GHz] IF [MHz] P LO [dbm] Conversion Gain [db] 9.8 ~ > 7.6 NF SSB [db] 17.5 ~ < 18.7 P 1dB [dbm] -24 ~ > IIP3 [dbm] > 1.0 Power [mw] Layout Area [mm 2 ] $ $ Technology [μm] FOM + [db] * Measurement results, # post-layout simulation results, $ mixer core, + FOM = (Gain[dB] + IIP3[dBm] NF[dB])/2-10 log(power[w]) from [29] 20

31 2.1.4 Conclusions based on Mixer Simulation Results A subthreshold mixer with cross-coupling capacitors was presented to achieve IIP3 enhancement by creating internal negative capacitances that cancel parasitic capacitances. Small-signal analysis and simulation results revealed that this design approach leads to significant IIP3 and conversion gain improvements. The design technique was demonstrated with a mixer in 130nm CMOS technology, which has a simulated conversion gain of 9.3dB and an IIP3 of 14.2dBm from 2.4GHz to 11.4GHz. Having a 385MHz output bandwidth (with a gain above 7.6dB and an IIP3 above 1.0dBm), the mixer shows potential for low-power UWB applications V 2.4GHz RF Front-End Design This section describes low-power design techniques that are validated with measurements of an RF front-end consuming 0.77mW while having a -4.5dBm in-band third-order intermodulation intercept point (IIP3), a noise figure (NF) of 6.3dB, and a SFDR up to 62.8dB. Instead of utilizing a passive mixer, the proposed active mixer was adopted to trade off linearity against voltage gain and noise figure. Cross-coupling capacitors were utilized to alleviate gain degradation due to parasitic capacitances, as shown by the simulations of a standalone mixer in Section This section introduces the reuse of inductors in the LNA load tank to aid linearization and to alleviate loading effects when an LNA is combined with an active mixer having cross-coupling capacitors. The shared inductors form filters together with the cross-coupling capacitors in the mixer, leading to improved linearity while enabling adequate gain with low power consumption. 21

32 Fig. 19 Schematic of the proposed low-power RF front-end Design Techniques The schematic of the front-end is shown in Fig. 19, which includes a pseudodifferential common-source LNA and a double-balanced active mixer. The current efficiency (g m /I d ) of the input transistors in the LNA and mixer are 22 and 24, respectively. The voltage headroom is relaxed due to the weak inversion operation. To realize transconductances comparable to transistors in strong inversion, high width/length (W/L) ratios were chosen as annotated in Fig. 19, introducing large parasitic capacitances (C P in Fig. 20) that would cause conversion gain loss. To avoid this problem, the crosscoupling capacitors C C create negative capacitances [23] approximately equal to (1-1/A) C C at the common sources of the switching stage to partially cancel C P because the condition 0.5 < A < 1 is satisfied by design as annotated in Fig. 20(b). However, the 22

33 capacitors C C also add undesirable Miller capacitances at the inputs of the mixer that load the LNA stage. The inductors in the LNA load are used to resonate with the input capacitance at the RF input frequency as visualized in Fig. 20(b). A moderate LNA gain around 15dB was chosen to reduce the linearity requirement for the mixer that has a conversion gain of 8dB. With the aforementioned low-power design approach, the frontend is able to realize a 22.7dB voltage gain with 0.77mW power consumption and a single 0.7V supply. (a) Fig. 20 (a) Phase and amplitude of signals at terminals of C C. (b) Negative capacitance generation (b) and input capacitance resonance. 23

34 IIP3 Improvement As indicated in Fig. 21, the cross-coupling capacitors provide paths from the common sources of the mixer switching stage to the LNA load, forming inductorcapacitor (LC) filters. These filters create low impedances at a frequency that is twice of the local oscillator (LO) frequency, thereby attenuating the common-mode voltage swing due to LO self-mixing, which significantly improves the IIP3 as in [34]. Thus, the codesign of the LNA and mixer in the presented front-end leads to further performance improvement. The cross-coupling capacitors and the LNA load form feedback paths for the drain current of a mixer input transistor to interact with the gate-to-source voltage of the input transistor in the other branch. The second-order response from the drain current and the fundamental signal mix to produce a third-order intermodulation (IM3) product that can be designed to cancel the third-order nonlinearity [35]. Fig. 21 LC filters formed by C C and LNA load tanks IIP2 Considerations The common-source LNA topology in Fig. 19 employs a linearization method based on [14] for the first time within a fabricated RF front-end, which is why it includes an inductor between the gate of the cascode transistor and the supply voltage. Section 2.3 contains first proof-of-concept measurement results for the realization of this linearization 24

35 approach for a subthreshold LNA loaded by this mixer topology. Both, the LNA and mixer, are configured as pseudo-differential structures to realize a high IIP3 at the expense of a lower second-order intermodulation intercept point (IIP2) compared with fullydifferential structures. However, as labeled in Fig. 22, the LNA load and the DCdecoupling capacitor between the LNA and mixer constitute a high-pass filter that attenuates the second-order intermodulation (IM2) component from the LNA. In the mixer stage, the negative capacitance generation of this design partially cancels C P and reduces the down-converted IM2 current. Another distinguishing characteristic of the presented mixer stage is that the negative capacitance generation of this design partially cancels C P and reduces the down-converted IM2 current. Fig. 22 IM2/IIP2 considerations related to C C and the LNA load tank. 2.3 Measurement Results The proposed RF front-end was fabricated in a 0.13μm CMOS process and packaged in a QFN-24 package. Fig. 23 displays the die in the package with bonding wires. The proof-of-concept chip includes six single-ended inductors and the active area is less than 0.5mm 2. However, the layout area could be reduced if one differential inductor can replace two single-ended inductors in Fig. 19, or if the bonding wire lengths are increased to replace a portion or all of the 2.3nH inductor and the 3.9nH inductor. The printed circuit board designed for the RF front-end measurements is shown in Fig

36 Fig. 23 Die photo of the differential RF front-end in a QFN-24 package. Fig. 24 Printed circuit board for testing of the RF front-end. 26

37 Fig. 25 visualizes the test setup for the RF front-end and the 10MHz transient intermediate frequency (IF) output voltages at IF+ and IF- measured with an LNA input power of -27dBm, simulated waveform is presented for comparison. An off-chip balun was used for the single-ended to differential conversion of the 2.4GHz RF input signal. The outputs of the front-end were connected to two off-chip op-amps and combined with a 1:1 balun to drive the 50Ω impedance of the Agilent N9010A signal analyzer. An external -6dBm LO signal was applied through a 1:1 balun (~0.2dB loss) with resistive matching. The measured 5.5dB loss of the input balun and cables were de-embedded from all measurement results. The measured IF output bandwidth is 30MHz due to the mixer being loaded with capacitances from the pad, package, and off-chip op-amps. There is a 10.3dB gain loss associated with the test buffer, output balun and cables, as annotated in Fig. 25(a). 27

38 (a) (b) (c) Fig. 25 (a) Test setup for the RF front-end. (b) Measured output voltage signals at the 10MHz intermediate frequency (with a power of -27dBm at the LNA input). (b) Simulated output voltage signals at the 10MHz intermediate frequency (with a power of -27dBm at the LNA input). 28

39 A two-tone test with inputs at [f LO +8MHz, f LO +10MHz] demonstrates an in-band IIP3 of -4.5dBm in Fig. 26(a). For an input power of -31.5dBm, the IM3 after the output balun is 54.2dBc as indicated in Fig. 26(b), which is also plotted from measurements with different mixer bias currents (Fig. 26(c)) and intermediate frequencies (Fig. 26(d)). The results in Fig. 26(c) reveal that the proposed linearization helps to achieve an IIP3 above - 10dBm and more than 21dB voltage gain with mixer supply currents ranging from 240μA to 360μA. The dependence of linearity on bias currents was also observed in simulations, and it is theoretically expected due to the operating point dependence of the nonlinearity coefficients [14], [23], [35]. As can be observed in Fig. 26(d), the IM3 varies less than 0.5dB when the two tones are swept from [f LO +3MHz, f LO +4MHz] to [f LO +9MHz, f LO +10MHz], confirming the robustness of the linearization method over frequency. As shown in Fig. 27, a voltage gain of 22.7dB was measured at 2.4GHz with S11 below -13dB, and a total double-sideband (DSB) NF of 6.3dB at 10MHz IF is achieved with LO power of approximately -6dBm. The input-referred 1dB-compression point (P 1dB ) is -19.8dBm, which is limited by the voltage headroom in the mixer stage. Even though the LO power is low in the proposed design, the IIP2 reaches 20.8dBm, which meets the IIP2 requirement (10.5dBm) for the ZigBee standard. The simulation results in Fig. 26(a) and Fig. 27(a)-(c) were obtained with models of bonding and package parasitics, which is particularly important for accurate S11 parameter results. 29

40 (a) (b) (c) (d) Fig. 26 (a) IIP3 of the RF front-end, (b) IM3 dbc with input power of -31.5dBm (including 10.3dB loss from the buffer stage), (c) IM3 dbc versus mixer supply current, (d) IM3 dbc versus IF frequencies. 30

41 (a) (b) (c) (d) Fig. 27 Measured (a) voltage gain from LNA input to mixer output (with IF = 10MHz) and S11, (b) voltage gain and NF versus LO power, (c) 1dB-compression curve, (d) IIP2 31

42 Table 3 Performance summary of the RF-front-end and comparison with the state-of-the-art This Work Simulated This Work Measured JSSC'15 [7] TMTT'14 [36] JSSC'14 [37] ISSCC'13 [8] JSSC'06 [9] Application ZigBee ZigBee Bluetooth ZigBee ZigBee Energy Harvesting Supply Voltage [V] / / Power [mw] 0.82* 0.77* * 0* RF Input Freq. [GHz] Voltage Gain [db] 23.7* 22.7* * 17* DSB NF [db] * 7 In-Band IIP3 [dbm] (Out of Band) -7 (Out of Band) -6 (Out of Band) WSN -21.5* -7.5 IIP2 [dbm] 24.1/44.3** P 1dB [dbm] P LO [dbm] CMOS Technology 130nm 130nm 130nm 65nm 65nm 65nm 130nm Area[mm 2 ] 0.5* 0.5* SFDR*** * LNA and Mixer ** Minimum/Mean of 100 Monte Carlo samples with process variation and mismatch 2( PIIP 3 174dBm NF 10log BW ) *** SFDR SNRmin, BW 2MHz, SNRmin 4dB 3 32

43 2.4 Conclusion The simulated and measured performance parameters of the front-end are summarized in Table 3. The measured 1-dB compression point is 5.4dB higher because the output DC level of the mixer stage was approximately 75mV higher than its simulated level, which provides more headroom for larger voltage swing. Compared with state-ofthe-art low-power RF front-ends (Table 3), this work succeeds in squeezing the power and improving in-band IIP3 with a 0.7V supply while maintaining sufficient NF and IIP2 performance. The SFDR is included as figure of merit in Table I, assuming a bandwidth of 2MHz and minimum signal-to-noise ratio (SNR) of 4dB for comparison. The presented RF front-end achieves better SFDR performance than the other sub-mw works, even though its SFDR was calculated with in-band IIP3 which is typically worse than the outof-band IIP3 with RF and baseband filtering. 33

44 3. ON-CHIP TEST CURRENT GENERATION CIRCUITS FOR INPUT IMPEDANCE CALIBRATION OF ANALOG FRONT-ENDS FOR BIOSIGNAL MEASUREMENTS 3.1 On-Chip Calibration System Fig. 28 Analog front-end for EEG signal measurements with electrode cable capacitances and calibration blocks for input impedance boosting. As an important part of the built-in calibration system design discussed in Section 1.2, the test current generator in Fig. 28 injects AC current (i t ) into the instrumentation amplifier (IA) input such that a corresponding voltage swing is created that depends on the magnitude of the input impedance. In this system, the on-chip oscillator generates a 20kHz rail-to-rail square wave, which is divided down to 19.5Hz. A voltage limiter converts the rail-to-rail signal to an 80mV differential peak-to-peak level that is compatible with the operational transconductance amplifier (OTA) input requirement. The OTA s transconductance is designed to be 25pS, which makes the i test magnitude equal to 1pA. If the input impedance of the IA is boosted to above 2.5GΩ at 19.5Hz, the voltage swing at the IA s inputs would be more than 5mV peak-to-peak because of the harmonics. This voltage swing is amplified and filtered by the following stages in the 34

45 analog front-end. The requirements of the OTA for test current generation are stringent because of its interface with the IA: 1.) The output impedance of the OTA should be high enough to avoid excessive loading effects even when the input impedance of the IA reaches more than 500MΩ at frequencies up to 100Hz. 2.) The output voltage amplitude is limited by the IA s input range that is designed for electroencephalography (EEG) signals, requiring an OTA transconductance in the sub-nano-siemens range. 3.) The output noise of the OTA should be small enough compared to the small voltage swing at the IA input during the current injection test mode. Here, we assume an output noise target of less than 100μV integrated from 0.01Hz to 100Hz. 4.) The power supply rejection ratio (PSRR) and common-mode rejection ratio (CMRR) of the OTA should be similarly high as in typical analog front-ends for biosignal processing applications. 5.) As part of the test current generator, it is preferred that the OTA has small layout dimensions and low power consumption. 3.2 Low-Power Temperature-Compensated Relaxation Oscillator Design New process technologies allow the design of chips with added functionality and improved performance, but their manufacturing process variations and post-production aging effects create a need for low-power on-chip self-test and calibration systems [38], which often include precise frequency references for test signal generation. In our research project (from [24]), the temperature-compensated oscillator plays a key role (Fig. 28) in the generation of the test signal that is used to calibrate the input impedance of the analog front-end for EEG signal acquisitions. Relaxation oscillators [39]-[43] are often employed for low-power operation with a relatively good accuracy compared to ring oscillators [39]. The frequency drift of the relaxation oscillator is mainly caused by the changes of polysilicon resistors and bias currents due to process, voltage and temperature (PVT) variations [40]. A relaxation 35

46 oscillator that utilizes electron mobility has been reported in [39], which realizes temperature compensation and is inherently process insensitive. A pseudo-differential architecture can be employed to avoid frequency fluctuations caused by bias current variations [40]-[41]. Composite resistors, which are created by mixing polysilicon resistors with opposite temperature coefficients, are sometimes employed to achieve a near-zero temperature coefficient (TC) [40],[42]. A relaxation oscillator with two current-mode comparators and integrated latches [44] offers a compact alternative to the commonly used combination of comparators, voltage references, and digital control logic. In this thesis, a proportional-to-absolute-temperature (PTAT) current reference circuit operating in the subthreshold region generates the bias current for the relaxation core based on the mechanism in [44], and a PTAT voltage is proposed to achieve a voltage swing across the timing capacitor that depends on the thermal voltage (V T ). Assuming that the charging current (I PTAT ) is equal to the discharging current, the proposed relaxation oscillator output frequency can be expressed as f OSC I, (21) 2 V C max PTAT V C min C T where both I PTAT and the voltage swing across the timing capacitor (V Cmax - V Cmin ) depend on the thermal voltage which itself is a function of the absolute temperature T: V kbt q T, (22) where q is the magnitude of the electron charge and k B is the Boltzmann constant. Because q and k B can be regarded as constant values, the PTAT current I PTAT and the voltage swing across the timing capacitor can both be designed proportional to absolute temperature. Hence, the temperature dependence of equation (21) can be minimized by design Antecedent Circuit Description The current-mode relaxation oscillator from [44] is visualized in Fig. 29. It operates under the conditions that I 4 > I 3 > I 2 > I 1. There are two phases per cycle: one is the charging phase when M 1 is off and C T is charged by I 1, and the other is the discharging 36

47 phase when M 1 is on and the discharging current is equal to I 2 - I 1. The control of the switching between the two phases depends on the voltage V C across the timing capacitor and the two current-mode comparators whose input transistors are M 5 and M 7, respectively. Fig. 29 Relaxation oscillator from [44]. Assuming the initial condition is that V C equals to zero and V O is greater than zero; then M 1 and M 7 are turned off, and M 2 and M 6 pass most of the currents from sinks I 2 and I 4. Thus, in this state, the currents i 2 (a copy of i 2 ) and I 3 charge the parasitic capacitances at node V O towards V DD. When the currents from sinks I 2 and I 4 entirely pass through M 2 and M 6, C T is linearly charged by the current I 1. Once V C rises to a level V Cmax that makes M 5 and M 8 strong enough to drive a drain current of I 2 + I 3, then V O will begin to drop. A positive feedback action via the current mirror accelerates the decrease of V O until V O reaches its lowest voltage (close to zero). With a near-zero V O and maximum V C, all the current from I 2 and I 4 is passed through M 1 and M 7, causing C T to linearly discharge with a current of I 2 - I 1 until V C approaches a minimum voltage V Cmin at which M 7 is not able to pass the current I 3. At this moment, V O and V C are both at low levels, and part of I 3 charges the node V O, which triggers the positive feedback that drives V O to be close to V DD to repeat the cycle. 37

48 All transistors operate in the subthreshold region. Hence, the drain currents of the transistors can be expressed as [44] I W L V V gs TN nvt I 0 e ; (23) i D where I D0 is reverse voltage saturation current, V T is thermal voltage, and n is the slope factor. V gs, V TN, W and L are the gate-source voltage, threshold voltage, width and length of the transistor, respectively. Note that V Cmax occurs when M 5 and M 8 pass the sum of currents I 2 and I 3 [44]: where VC max V V 2V nv D, (24) gs5 gs8 I 2 I D 1 ln I D0 V Cmin occurs when M 7 passes the current I 3 [44]: 3 2 TN L5I 8 W W 5 8 T 1. (25) V C min V V nv D, (26) gs7 TN T 2 where I D 2 ln I 3 D0 L7 W 7. (27) In this manner, the circuit oscillates by charging and discharging the timing capacitor C T with I 1 and I 2 - I 1. The time durations of the charging and discharging phases are [44]: T T C V V T C max C min 1, (28) I1 C V V T C max C min 2. (29) I 2 I1 Hence, the output frequency of the oscillator is obtained as [44] f OSC 1 I1 I 2 I ; (30) T T I V V C max 1 C min C T 38

49 and from equations (24) and (26) it follows that where V C max C min V V nv D D, (31) D 1 D2 ln TN I 2 I I I 3 3 D0 T L5L8W W W L (32) In [44], the voltage difference (V Cmax - V Cmin ) in equation (21) includes one threshold voltage (V TN ) and the squared component of I 2 + I 3 because M 8 is included to spare headroom for keeping M 1 in saturation and realizing a low output frequency. In this thesis it is proposed to replace M 8 with a voltage proportional to absolute temperature, such that the D 1 - D 2 term in (12) depends on device dimensions while canceling out the temperature-dependence due to I D0. Furthermore, without the extra V TN from M 8, V Cmax - V Cmin in (31) strictly depends on V T and a constant term (D). Fig. 30 displays the modified circuit in which M 8 is replaced with a PTAT voltage source. The equations associated with the new circuit are: V V L I 7 3 C min VTN 7 nvt ln, (33) W7 I0 L5 I 2 I3 VC max VTN5 nvt ln VPTAT, (34) W I V V nv T D 5 0 PTAT, (35) nv W7 L5 I 2 I L W I D 3 C max C min T ln, (36) f OSC I1, (37) 2 V V C max C min C T 39

50 Fig. 30 Proposed relaxation oscillator concept with the V PTAT. where term D depends on the V PTAT design (Section 3.2.2), the approximation in (36) implies that M 5 and M 7 have the same threshold voltage, and equation (37) is derived from (30) with the condition I 2 = 2 I 1. Expressions (36) and (37) reveal the design strategy for a temperature and process stable oscillator. If we design such that I 1, I 2, I 3, and I 4 are proportional to each other and mirrored from a PTAT current reference, then the temperature dependence of the terms in the denominator and numerator of equation (37) can cancel each other such that the frequency error depends predominantly on transistor mismatches Proposed V T -Based Compensation Technique Fig. 31 presents the proposed relaxation oscillator circuit, which consists of a PTAT current reference (M R1 -M R6, R), two integrated current-mode comparators with positive feedback, and a PTAT voltage reference (M I5, M 9, M 10 ). An output buffer (M B1, M B2 ) is included to drive the load. 40

51 Fig. 31 Complete schematic of the proposed relaxation oscillator PTAT Current Reference In this prototype, a classic structure is adopted to generate a 80nA current at 300K (27ºC). M R5 and M R6 in Fig. 31 are biased in the subthreshold region, and their drain currents can be expressed with equation (23). The voltage across resistor R is V gsr W 5 ln L R6 R5 VgsR 6 nvt, (38) LR6WR 5 where channel length modulation is neglected and it is assumed that the drain currents of M R5 and M R6 are identical because of the current mirror structure. It follows that the PTAT reference current is nv W L T R6 R5 I PTAT ln. (39) R LR6WR 5 As can be observed in Fig. 31, this PTAT reference current is mirrored to obtain reliable PTAT currents for the PMOS and NMOS transistors based on matched devices. A capacitor C N of 10pF was added to suppress high-frequency noise. As stated in Section 3.2.1, the oscillator operates under the conditions I 4 > I 3 > I 2 > I 1. To realize a 50% duty cycle, we let I 2 equal to 2 I 1. Furthermore, we select the following bias current relationships in this design: I PTAT 1 4I1 2I 2 I3 I 4 4I5. (40) 2 41

52 PTAT Voltage Generation for Compensation A key aspect of the process and temperature compensation is to design a PTAT charging/discharging current and a PTAT voltage difference (V Cmax - V Cmin ). Let us consider the phase when V O is close to V DD and V C is linearly rising due to the charging current I 1. The moment at which V C reaches V Cmax, M 5 conducts current I 2 + I 3 and M 10 conducts current I 2 + I 3 + I 5. M 9 and M 10 are biased in the subthreshold region, in which their drain currents can be expressed as in equation (23). Hence, at the moment of interest, and neglecting channel length modulation, the PTAT voltage generated at the drain of M 10 is: V W L I I I PTAT Vgs 10 Vgs 9 nvt ln. (41) L9W 10I5 The voltage difference V Cmax - V Cmin can be derived from equations (33), (34) and (41) as follows: V W L W L I I I I I C max VC max nvt ln. (42) L7W5 L9W 10I3I5 Equation (42) shows that the voltage difference across the timing capacitor is considered proportional to absolute temperature when all the bias currents (I 1, I 2, I 3, I 4, and I 5 ) are designed as current mirrors with certain ratio Cancelation of the Thermal Voltage With a PTAT charging and discharging current and a PTAT voltage difference across the timing capacitor, the output frequency can be written as 42

53 f OSC 2RC 2 V 2nV C T T T C max I1 V C min nvt WR6LR5 ln R LR6WR5 W7L5W 9L ln L W L W I WR6LR5 ln LR6WR5 W7L5W 9L10 2 ln L W L W 7 C 7 I I I I I I I I I I 5 T I I I (43) The above equation shows that the combination of the PTAT current reference and the PTAT voltage difference realizes an output frequency that only drifts with R in the PTAT current reference, C T, and matched transistor dimensions. Hence, the output frequency is quite stable with good layout practice and a resistor R having a low temperature coefficient Simulation Results and Discussion The relaxation oscillator was designed in a 0.13μm CMOS technology with 1.2V supply, and post-layout simulations were performed. The circuit occupies 0.025mm 2 and uses only thick oxide MOS devices with a length of 4μm (400nm for the output buffer). Thin oxide devices were avoided because of their high gate leakage current, which is significant in this circuit and which represents a significant fraction of the drain current for very long devices [45]. Fig. 32 presents the simulation results for the percent changes of I 1 and V Cmax - V Cmin in equation (43) versus temperature, showing good agreement between the temperature dependence of the terms in the numerator and denominator of the equation, and validating the proposed V T -based temperature compensation. Fig. 33 displays the voltage across the capacitor V C and the output waveform before the output buffer V O. Fig. 34 shows the output frequency variation from -30 ºC to 85 ºC for different process corners. The results demonstrate that the proposed relaxation oscillator exhibits temperature and process insensitivity. Resistor R (polysilicon over isolation) in 43

54 the PTAT current reference has a temperature coefficient of 45ppm/ºC. In the fast corner with high temperature, the leakage currents increase and the mismatch of the slope factors between transistors (M 5, M 7, M 9, M 10 ) and (M R5, M R6 ) become significant, which increases the frequency variation to around 2.6%. Fig. 35 and Fig. 36 show the results of 100 Monte Carlo (MC) simulation runs with process variations and mismatches using foundry supplied device models, revealing the robustness of the design. Fig. 32 Variations of I 1 and V Cmax - V Cmin vs. temperature. Fig. 33 Simulated V O, V C, and V OSC waveforms (frequency = 40kHz). 44

55 Fig. 34 Output frequency variation vs. temperature (different corner models). Fig Monte Carlo (MC) simulation samples with process variations. Fig Monte Carlo (MC) simulation samples with mismatches. 45

56 A drawback of the proposed relaxation oscillator is the line regulation (3% frequency variation with a supply voltage change from 1.2 V to 1.5 V) due to the choice of utilizing long channel lengths, which introduce high parasitic capacitance at node V O. Though the positive feedback mechanism during the transitions of V O alleviates the delay due to the parasitic capacitance at V O, the delay becomes significant as the output frequency is increased by design. Hence, as mentioned in [44], this structure is only suitable for low-frequency applications. Table 4 presents a comparison with state-of-art relaxation oscillators in the sub-mhz regime. The proposed oscillator shows comparable performance with regards to the temperature coefficient while being compact and resilient to variations. Table 4 Oscillator performance summary and comparison with the state-of-the-art Reference [39] [40] [41] [42] [43] [46] This Work* Technology [nm] # Frequency [khz] Power [μw] V DD [V] TC [ppm/ºc] Temperature Range -20 to 80ºC -20 to 100ºC -40 to 90ºC -20 to 80ºC -40 to 100ºC -30 to 85ºC -30 to 85ºC Variation with V DD Process Sensitivity 3.5%/V (1.0 to 2.5V) 6.9% σ (80 MC runs) ±0.4% over V 1%/V - 1.7%/V (1.0 to 2.0V) %/V % σ (20 samples) >20% over V - 3% over 1.2 to 1.5V 6.0% σ (100 MC runs) Layout Area [mm 2 ] FOM $ [db] * post-layout simulation results, # only 3.3V thick oxide transistors are used (minimum length = 400nm), $ FOM = 10 log(frequency/power) from [39] Oscillator Measurement Results The oscillator on the test chip includes a bias multiplexer that allows to switch between internal PTAT current reference and external current bias. In addition, the output frequency was reduced to approximately 20kHz, and two stages of digital inverters were 46

57 added as buffers to drive the long metal lines because the oscillator output is more than 1mm away from its pad. Fig. 37 displays the output waveform and frequency of the proposed oscillator at 25ºC. The temperature performance of the oscillator output frequency with on-chip PTAT current reference was measured using an X-STREAM 4300 at Linear Technology, from which the results are plotted in Fig. 38. Fig. 39 shows example output waveforms at -30ºC and 25ºC. The measured temperature coefficient in the range of -30ºC to 85ºC is 535ppm/ºC for Chip 1, and the trend of frequency vs. temperature does not match the simulations. The prototype chip design does not provide access to the internal nodes of the oscillator through pins. To properly investigate the source of the measurement vs. simulation discrepancy after a future chip fabrication, it would be advisable to include buffers at internal nodes in the oscillator to drive pads for external monitoring. Nevertheless, the measured oscillator performance meets the target application requirements as part of the test signal generation block in the EEG front-end system. Fig. 40 and Fig. 41 display the measurement results at room temperature for time-domain frequency variation (27.5Hz standard deviation) and cycle-to-cycle jitter (116.4ns standard deviation), respectively. For these two measurements, an off-chip buffer stage was used to drive the 50Ω input impedance of the oscilloscope Agilent DSA80000B as shown in Fig. 42. The measured power consumption of the oscillator is 1.13μW. Fig. 37 Measured oscillator output waveform and frequency at 25ºC. 47

58 Fig. 38 Measured oscillator output frequency vs. temperature variation. (a) (b) Fig. 39 Measured oscillator output waveform and frequency at (a) -30ºC and (b) 25ºC. 48

59 Fig. 40 Measured oscillator output frequency variations. Fig. 41 Measured cycle-to-cycle jitter of the oscillator. 49

60 Fig. 42 Oscillator measurement setup with off-chip buffer Frequency Divider Design The divide-by-1024 operation is implemented through 10 cascaded divide-by-2 stages consisting of D flip-flops with feedback as shown in Fig. 43. Fig. 43 Frequency divider (with standard D flip-flops designed on the transistor level) Limiter Design Based on the simulated transconductance and noise of the OTA, the swing at its input should be limited to a differential peak-to-peak voltage of 80mV. Fig. 44 displays the proposed voltage limiter that was designed for this purpose. Its output signal level is changed by alternatively steering the current I SS into resistor R 2 (connected to V o1 ) when the 19.5Hz (20kHz/1024) output signal (Φ CLK ) of the frequency divider is low, or by steering I SS into the parallel combination of R 1 and R 2 when Φ CLK is high. For the V o2 branch, the operation is the same but with reversed clock signals at the switching transistors. The values of R 1, R 2 and I SS can be calculated based on the output voltage swing requirement, where the voltage drop is either I SS R 2 or I SS (R 1 R 2 ). However, the use of large currents causes high power consumption, while the use of large resistors results in 50

61 large layout area. In the described design, a current of 100μA was chosen in combination with R 1 = 82kΩ and R 2 = 6.15kΩ. The output DC level of the limiter can also be controlled with the values of R 1, R 2, and I SS. Since the input DC level of the OTA is 600mV, the component values were chosen such that the limiter output signal levels at V o1 and V o2 range from 580mV to 620mV. Transmission gates are used as switches to minimize the resistance in series with R 1 when the switches are closed. Fig. 45 shows the simulated transient differential output voltage swing of the limiter, which has a peak-to-peak value close to 80mV. Fig. 44 Schematic of the differential voltage limiter. The amplitude of the limiter output should exhibit as little variation as possible under different process corner and temperature conditions. As depicted in Fig. 44, a regulation loop with a differential amplifier was added, in which the dummy transistor M ND has the same dimensions as transistor M N, such that the voltage at node V X reflects the variations of R 2 and M N in the main branches because the transistors have the same gate and source voltages. A textbook amplifier [47] was designed for this loop. The negative feedback loop adjusts the gate voltage of M ND such that its drain-to-source voltage is driven to a value close to V ref = 580mV. When M N, M ND, and all resistors are realized with multiple sub-devices that are matched through proper layout, then the I SS R 2 product only has a small error between the branches and the drain-to-source voltage of M N is also equal to V ref (580mV) when R 1 is disconnected. Furthermore, the difference between the minimum and maximum output voltages depends on the ratio of the matched resistors, and has a reliable maximum value that is 40mV higher when the 51

62 switch in a branch is closed. Consequently, the peak-to-peak differential output signal swing (V o1 - V o2 ) is always close to 80mV. Table 5 presents the simulation results of the limiter with process corners and temperature variations, and it reveals that the phase margin of the negative feedback loop in Fig. 44 is always higher than 60, ensuring the stability of the circuit. Fig. 45 Simulated differential output voltage (V o1 - V o2 ) of the limiter (typical corner case, 27 C). Table 5 Simulated differential output voltage swing of the limiter and phase margin in its regulation loop (IBM 130nm CMOS process) Process Temperature Differential Output Swing (mv) Phase Margin Typical Fast Slow -30 C 78.4mV 70.9 deg. 27 C 80.2mV 73.9 deg. 85 C 81.3mV 76.4 deg. -30 C 78.4mV 69.8 deg. 27 C 80.2mV 72.9 deg. 85 C 80.9mV 75.6 deg. -30 C 78.3mV 72.0 deg. 27 C 80.3mV 74.8 deg. 85 C 81.4mV 77.2 deg. 52

63 3.3 Custom OTA Topology Fig. 46 shows the OTA and its biasing circuit. The OTA should have significantly higher output impedance than the impedance of the node into which the current is injected. Since the input impedance requirement of the instrumentation amplifier (IA) is 500MΩ [22], an OTA output impedance of at least 1GΩ up to 100Hz is targeted here to avoid excessive loading effects. Moreover, the maximum output capacitance target for the OTA design is 200fF to ensure that it is small compared to the total capacitance (C in in Fig. 28) after partial capacitance cancellation. Due to the high impedance at the IA input, a differential test current magnitude of 1pA was chosen to keep the input voltage swing at the injection node in the millivolts range, which maintains linear operation of the IA and LPF. This requires an OTA with very small transconductance around 25pS (with V in = V in+ - V in- = 40mV peak ). 53

64 (a) (b) (c) Fig. 46 Schematic of the (a) OTA core, (b) bias current generation structure of the OTA (N = 10), and (c) bias voltage generation structure of the OTA. The instrumentation amplifier [48] used in this project has a simulated inputreferred noise of 2.5μV in the band of the interest (0.01Hz to 100Hz), and the proposed OTA generates 78μV output-referred noise integrated from 0.01Hz to 100Hz. Hence, the total noise is small compared to the approximately 4mV peak-to-peak differential swing 54

65 at the instrumentation amplifier inputs that is shown in Fig. 47. To obtain the result in this figure, the test current generator was simulated with 3pF capacitances at the OTA output nodes, which ensures that the front-end input impedance is higher than 500MΩ in the 100Hz band of interest (i.e., after partial input capacitance cancellation). Fig. 47 Simulated differential output voltage of the test signal generator with a load capacitance of 3pF and transient noise enabled ( Hz range) for all devices. The proposed OTA is fully-differential to obtain a high power supply rejection ratio (PSRR) and common-mode rejection ratio (CMRR). Furthermore, common-mode interference will be suppressed by the instrumentation amplifier, which typically has a CMRR of more than 70dB in biopotential measurement applications. For the ease of signal generation and amplitude detection with comparators (Fig. 28), a square wave input signal is employed in this method, which results in a slewed waveform (Fig. 47) at the capacitively loaded OTA output and into an almost sinusoidal waveform at the LPF output due to the filtering (Fig. 9, Fig. 28). The linearity of the OTA is not critical in this amplitude detection-based method, and a third-order harmonic distortion (HD3) specification of -20dB is sufficient since it ensures that the OTA s HD3 remains below the third-order component of an ideal square wave. 55

66 3.3.1 Sub-Nano-Siemens Transconductance Design The target value of the IA input impedance is 500MΩ up to 100Hz. A differential test current magnitude of 1pA was chosen to keep the input voltage swing at the injection node limited to a few millivolts, which maintains linear operation of the IA and lowpass filter. Hence, the OTA s transconductance was designed to be approximately 25pS. Its differential inputs are limited to 40mV peak. There are several methods to design sub-nano-siemens OTAs [49]. In the proposed architecture shown in Fig. 46, transistors M 2 -M 6 in Fig. 46(a) implement a series-parallel current division with an 8:1 ratio, which was adapted from the OTA design with 33pS transconductance in [50]. To generate precise picoampere-range bias currents such as I b2, the current splitting technique from [51] was applied as shown in Fig. 46(b) with N = 10 and I REF = 150nA, which is a layout efficient configuration to obtain such small currents. With these two structures, a transconductance of 25pS is obtained at the cost of the input stage s linearity performance which is not critical in this amplitude detection application Design of an OTA Output Stage With High Output Impedance, Low Noise, and High PSRR As depicted in Fig. 46(a), the output stage of the OTA is composed of transistors M 3 -M 10, which includes a PMOS common-gate structure (M 8 -M 10 ). Biased with a DC current less than 1nA, the output impedance could reach tens of gigaohms without M 8 - M 10. Such high output impedance is desirable for current injection at the instrumentation amplifier input. However, without M 8 -M 10, the output noise of the OTA would be several millivolts because of the low transconductance of the transistors in the output stage and the high output impedance. In order to alleviate the trade-off between low output noise and high output impedance in the conventional output stage (M 3 -M 7 ), a common-gate structure whose input transistor is M 8 was added to lower the output impedance to approximately 1/g m8. Hence, the OTA s low-frequency output impedance can be estimated with equation (44), where g m8 is the transconductance of M 8. This modification significantly reduces the output noise. 56

67 1 rout, OTA. (44) g In our previous work [24], M 8 was biased with a diode-connected NMOS driven by a reference current. This creates sensitivity to temperature and process variations. For example, when the temperature changes, the DC bias voltage provided by the diodeconnected NMOS transistor changes due to the temperature s effect on the threshold voltage. Since the gate of M 8 is a sensitive node in the output stage, especially in a scenario where the bias current is only a few picoamperes, the output impedance (approximately 1/g m8 ) would change significantly in response to a temperature change. Even though the simple biasing structure consisting of a diode-connected NMOS and current mirrored from I REF has the advantage of high PSRR, it is not a good choice when it is required to ensure a high output impedance that is insensitive to temperature and process variations. Fig. 46(c) presents the topology for the generation of most of the OTA s bias voltages, and Fig. 48 displays the proposed biasing circuit for the PMOS transistor in the common-gate structure of the OTA output stage in Fig. 46(b). The asterisks of M * 25 and M * 26 indicate that these composite transistors consist of multiple unit transistors in series with shared gate connections, which are implemented in the same way as M 3 -M 6 in Fig. 46(b). Currents I b1 -I b4 are generated from the current splitting structure in Fig. 46(a), and I b2 -I b4 are bias currents produced from I b2 -I b4 using simple current mirrors, respectively. There are two benefits of the structure in Fig. 48: one is a high OTA PSRR, and the other is that the voltage V pb2 adapts to compensate for temperature and process variations. m8 57

68 Fig. 48 Proposed biasing circuit for the OTA s output stage. Assuming that I REF in Fig. 46(a) is obtained from a current reference circuit with very high PSRR, then I b1 is also robust to supply voltage ripples because it is mirrored from I REF using transistors that experience the same gate-source voltage fluctuations. Thus, if there is a ripple on V DD, the fluctuation at node A in Fig. 48 can be ignored because I b1 remains almost constant despite of the ripple from V DD. Hence, the mirrored current flowing into M 15 also maintains its value, which causes the gate voltage of M 15 (node B) to follow the ripple at V DD because the source-gate voltage (V SG ) of M 15 is constant as a result of its constant current. As a consequence, M 16 also has an almost constant source-gate voltage in the presence of a supply voltage ripple, and therefore the drain current flowing into the diode-connected load is quite insensitive to ripple on V DD. Note that the voltage at node C is produced with the same configuration as the bias voltage V pb2 in our previous work [24], which exhibits a decent PSRR. With a robust voltage at node C and current mirrored from I b1, the voltage V pb2 can be expressed as: V V V V, (45) pb2 C SG24 GS 25 where V SG24 is the source-gate voltage of M 24 and V GS25 is the gate-source voltage of M * 25. Both voltages are insensitive to power supply ripple because M 24 and M * 25 are biased with the current that is mirrored from I b1. Hence, V pb2 exhibits an equally good PSRR as the voltage V C at node C. In the OTA output stage in Fig. 46(b), M 7 is biased 58

69 with a diode-connected PMOS transistor (M 27 in Fig. 46(c)). Therefore, the ripple effect from V DD through M 7 to V out is negligible. As revealed by simulation results and comparisons in Section 3.3.3, the PSRR of the OTA with the proposed biasing structure is higher than that of our previous design [24]. If we lump the gate-source voltage changes due to temperature and process variations as threshold voltage changes, the deviation of V pb2 can be expressed as: V pb2 V V THN C V V THP24 SG24 V V THN GS 25 V THP24. (46) The underlying assumption in the above equation is that the threshold voltage changes of the composite transistor M (formed by M 17 - M 23 ) are the same as the changes of the composite transistor M * 25. Hence, in the presence of temperature or process variations, the change V pb2 = - V THP24 can compensate for the change of the threshold variation of M 8 as long as the bias current or copies of the bias currents (I b2, I b3, and I b4 ) are generated as robustly as previously described: V V ) V V 0. (47) ( SG8 THP8 THP24 THP8 Partial cancellation necessitates that the PMOS transistors are laid out carefully (i.e., in proximity to each other with a matching technique) such that their threshold variations are highly correlated. With the proposed structure, the variation-induced V V ) ( SG8 THP8 is compensated by V pb2, making the output impedance of the OTA ( 1/g m8 ) more robust Simulation Results All aforementioned circuits were designed and simulated using 0.13μm CMOS technology with 1.2V supply. Since the test signal generator was designed for amplitude-based detection, the effects of process and temperature variations on key parameters were evaluated with foundry-supplied device models. Fig. 49 shows the simulated output impedance of the OTA in the test current generator for different temperature and process variation cases, which demonstrates that the output impedance is reliably high enough for current injection with the proposed biasing structure for the output stage. Table 6 summarizes the simulation results of the OTA s most important parameters for the target application. As discussed at the beginning of the Section 3.3, 59

70 the design approach with the proposed OTA focuses on the realization of sub-ns transconductance with substantial output impedance, adequate output noise, as well as good CMRR and PSRR. These application-specific characteristics are needed for reliable picoampere current injection at the high-impedance input nodes of the instrumentation amplifier with a limited voltage swing to avoid saturation. As a consequence, this OTA is different from conventional low-transconductance OTA designs for filters with low cut-off frequency, which are typically optimized for low input-referred noise, low distortion, and high dynamic range [52]. Nevertheless, for comparison, Table 6 also lists the reported parameters of some similar OTAs found in the literature. Fig. 50 displays the voltage swings (with and without NCGFB) at the IA s input using the described OTA for current injection. In an automated calibration such as in Fig. 28, this input signal would be amplified and filtered for impedance estimation through amplitude detection. The simulation result in Fig. 50 reveals that the input impedance is greatly boosted by the NCGFB activation, and that the voltage swing at the IA input is far above the noise level during the test current injection with the OTA. Fig. 49 Output impedance vs. frequency of the OTA with process and temperature variations. 60

71 Table 6 OTA simulation results Performance [50] [53] [24] This Work Output impedance at 100Hz GΩ 4.6GΩ Transconductance 33pS pS 25.9pS 29.2pS Output-referred noise / integration range HD3 (of i out, sinusoidal V in = 80mV p-p at 19.5Hz) CMRR mean / standard deviation (with mismatch*) PSRR mean / standard deviation (with mismatch*) 160μV rms / Hz - - < 1% (THD) μV rms / Hz -30.1dB 69dB / 7.2dB 56dB / 6.5dB 74μV rms / Hz -29.5dB 85dB / 6.6dB 72dB / 7.3dB Supply current ~100nA < 1μA 168nA $ 686nA $ * 100 Monte Carlo simulations with a load capacitance of 3pF at 60Hz. $ Includes supply currents for bias circuits. Fig. 50 Voltage swings at the IA input with current injection from the OTA for two cases: i.) with NCGFB, ii.) without NCGFB. (Noise was activated during the transient simulations based on the integrated noise density from 0.01Hz to 100Hz.) 61

72 3.4 Prototype Chip Measurements In this section, measurements with the negative capacitance generation technique are presented and discussed, proving the feasibility of the proposed input impedance boosting method through manual adjustments of the capacitor bank codes instead of using the outputs from the automatic digital calibration (Fig. 28). The built-in test signal generation circuits for the input impedance estimation with current injection were also validated through test chip measurements together with the on-chip instrumentation amplifier (IA). Fig. 51 displays the part of the fabricated die that contains the EEG frontend blocks, and the zoomed-in view of the test current generator (TCG). The printed circuit board (PCB) that was designed and assembled for this project is shown in Fig. 52. (a) (b) Fig. 51 Micrograph of the test current generator: (a) with EEG front-end blocks, (b) zoomed-in view. 62

73 Fig. 52 Printed circuit board design for the self-calibrated EEG analog front-end Input Impedance Test Setup The IA s input impedance can be as low as 8MΩ if there is 200pF parasitic capacitance from the chip package, PCB, and electrode cable. This section focuses on the assessment of the manual input impedance tuning capability and input impedance estimation with an external test signal. Fig. 53 Indirect input impedance measurement with test resistors. 63

74 Jiawei Xu (Delft University of Technology Ph.D. candidate in collaboration with IMEC) kindly shared the idea of indirect measurement of the input impedance using test resistors. As depicted in Fig. 53, test resistors are placed in series with the IA s input impedance, which forms attenuating structures. With a certain test signal input amplitude of V S in Fig. 53, the associated IA output amplitude (V OUT ) can be monitored with and without the test resistors (R TEST ). Since the values of the variable test resistors can be measured, the different output amplitudes can be used to calculate the IA input impedance. The following equations are written under the assumptions that the input impedance is predominantly capacitive and that the input capacitances at both inputs are approximately the same after tuning: When R TEST is set to zero in Fig. 53, there will not be any attenuation of the singleended-to-differential converter s output, and the voltage gain of the single-ended-todifferential converter is 2. Under this condition, the signal at each input of the instrumentation amplifier (V IN+, V IN -) is expressed as V 1. (48) IN V S On this prototype chip, a test pin permits to monitor the combined amplified signal at the IA output: V Gain V. (49) OUT1 2 IA IN1 When R TEST is set to a nonzero value, then the output signal from the single-ended-todifferential converter is attenuated at each IA input: The corresponding output of IA is An attenuation factor (K) can be defined as: V V IN 1/ jcin 2 VS. (50) R 1/ jc TEST OUT 2 2 IA IN 2 IN Gain V. (51) K V V OUT 2 OUT1 V V IN 2 IN jr TEST C IN 1 1 R C 2 TEST From the above equation, the input capacitance can be calculated as follows: IN. (52) 64

75 C IN 2 2 1/ K 1 1/ K 1. (53) R 2f R TEST TEST TEST With test signal frequency of f test, the input impedance at f test can be estimated as Z IN 1 2 f test C IN. (54) The expected input impedance after tuning is several hundreds of megaohms at 50Hz, and simulations confirmed that the negative capacitance generated by the feedback loop would be affected if the test resistance value is comparable to the input impedance at the test signal frequency. For this reason, the test resistor was implemented with a potentiometer that is adjustable from 0 to 5MΩ. If the test signal frequency is low when using a test resistance of several megaohms, then the attenuation would be hardly observable. Hence, a higher test signal frequency of 1kHz was chosen, which is still within the bandwidth of the IA. During the described test, the IA gain was set to 20dB, and the amplitude of the source signal was set to 4mV. Thus, the expected IA output amplitude is around 80mV in the case without attenuation and with the AD8131 gain of Manual Input Impedance Calibration with an External Test Signal Three different C in values (50pF, 100pF, 150pF) were used to experimentally examine the functionality of the negative capacitance generation. Fig. 54 displays the waveform at V OUT when R TEST is set to zero and with C in of 100pF, resulting in no attenuation due to C in as explained in Section Setting R TEST to 5MΩ with C in of 100pF resulted in the V OUT waveform that is shown in Fig. 55(a). After the manual increase of the negative capacitance, the V OUT waveform in Fig. 55(b) was obtained with a code of and the waveform in Fig. 55(c) with the optimum code of The results in Fig. 55 demonstrate the increased voltage amplitudes from the input impedance boosting mechanism through input capacitance cancellation. Fig. 56 contains plots of the IA input impedances with the aforementioned input capacitance values for several control codes of interest, which were calculated from the measured amplitudes using the procedure described in Section The maximum (boosted) differential input impedances for C in values of 50pF, 100pF and 150pF are 1GΩ, 800MΩ and 65

76 550MΩ, respectively. Note that the codes on the x-axes in Fig. 56 are not continuous because the selected measurements were performed to visualize the impedance boosting effect for codes of interest. Since the calibration method involves cycling through all codes to find the optimum, the linearity of the Z in vs. code relationship is not important. To identify the over-compensation regions in Fig. 56, an oscillation detector has been incorporated into the automatic calibration system using an on-chip comparator [54]. Fig. 54 Measured waveform (V OUT ) at the IA s output with R TEST = 0 and C in = 100pF. 66

77 (a) (b) (c) Fig. 55 Measured V OUT waveform at the IA s output with R TEST = 5MΩ and C in = 100pF with different codes: (a) , (b) , and (c)

78 (a) (b) (c) Fig. 56 Input impedances for various tuning codes: (a) C in = 50pF, (b) C in = 100pF, (c) C in = 150pF. 68

79 3.4.3 Built-In Input Impedance Test with Current Injection The blocks for the test current generation and the amplitude of the IA output are visualized in Fig. 57. The total power consumption of the test signal generator was measured as 487μW, of which approximately 90% is consumed by the limiter. There is no output pin for the 19.5Hz signal after the frequency divider, but the 20kHz/512 39Hz intermediate signal for the digital calibration logic circuits is accessible through a test pin on the chip, which is shown in Fig. 58. Fig. 59 shows the measured sawtooth waveforms at the IA output during the test current injections with an input capacitance of 100pF and different calibration codes. Fig. 57 Current injection with the test current generator. Fig Hz frequency divider output signal (20kHz oscillator divided by 512) for the digital calibration control logic circuits. 69

80 (a) (b) (c) Fig. 59 Sawtooth waveforms at the IA output with C in = 100pF and different tuning codes: (a) , (b) , and (c)