Belle Trigger/DAQ Workshop Workshop Summary R.Itoh, KEK

Transcription

1 Belle Trigger/DAQ Workshop Workshop Summary R.Itoh, KEK Shinshu University, 2/17-18/ participants Shinshu Univ. Matsumoto Catsle and Mountains

2 Workshop Goals 1. Confirm the feasibility and compatibility of the near-term upgrade plans between Trigger/DAQ and detector groups. * We need prompt upgrade of DAQ to cope with the luminosity increase in coming years. * The upgrade should be as much as compatible with the upgrade for Super B. 2. Discuss readiness of our design for Super KEKB with L=5x1035 cm-2sec-1. * Previous design was for L=1x1035 cm-2sec-1 with rather pessimistic assumption on trigger rate. * Update trigger rate estimation using the latest data and verify our design.

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4 CDS Agenda was used to manage program and talk slides! You can reach the page from

5 Current Status DAQ dead time during data taking (2/19-20/2005) Dead Time Fraction ~3.5% deadtime added due to injection VETO w/ injection w/o injection Average dead time during data taking = Hz L1 rate = ~4% (readout) + ~2% (Inj. VETO) + ~1% (CDC current limit.) Estimation of dead time with increased luminosity

6 Possible DAQ condition until SuperB upgrade - L is ~1.5 x 1034 in 2005 Ave. trigger rate ~ 500 Hz => intrinsic DAQ deadtime ~ 3-4% can live with current DAQ - L will increase up to 2~5 x 1034 in xx (with crab cavity installed) Ave. trigger rate ~ 1-2kHz => intrinsic DAQ deadtime >20% needs effort to reduce deadtime and to increase processing power for event builder/l3 farm - L > 1035 in 20xx (xx can be 08~11?) by SuperB upgrade Ave. trigger rate >10kHz (max. 30kHz) => pipelined DAQ is really necessary >10 x CPU power for EB/L3 farm Clear and Present Danger by Tom Clancy

7 35 Trigger rate ) According to present knowledge, Luminosity term is quite large. 200Hz x Luminosity ( unit:1034cm-2sec-1) 10kHz at L = 5x1035cm-2sec-1 To reduce it, better trigger system is necessary. To keep tau events and to suppress two-photon events HER beam dominantly affects the background trigger rate. Trigger rate P x IHER I2HER 200Hz at IHER =1.27A 0.2x(4.1/1.27)2 = 2kHz One worry : Lower y* 6mm 3mm Good point : More bumps at Tsukuba straight section to reduce the vacuum pressure. Uno

8 Iwasaki

9 Expected performance without upgrade of frontend readout Trigger Rate A) 500Hz Readout deadtime 4% B) 1KHz ~20 % ~ 75 % C) 2KHz >50 % <45 % D) 10 KHz ~100 % ~0% Needs some upgrade! Total efficiency ~ 91 % Current condition SuperKEKB * We need to manage B) and C) even before SuperKEKB upgrade without interrupting scheduled accelerator running. 1. Upgrade of readout system to pipeline-based system * Another possibility is further sub-division of slow detector readout (like ECL), but LeCroy does not support FASTBUS TDCs any longer Upgrade of Event Builder/RFARM also. * To remove 650Hz barrier

10 Smooth adiabatic upgrade scenario to SuperB DAQ No distinction between near-term and SuperB upgrades * Keep intrinsic dead time ~ 5% even with increased luminosity * Upgrade is consistent with further SuperB detector upgrade * Upgrade scenario is as much as independent of SuperB budget profile * Do not interrupt accelerator running by the upgrade * Replace existing FASTBUS TDC system with COPPER based pipelined TDC system(no dead time) detector by detector during scheduled accelerator shutdown time (Summer, Winter). - Start from the detector with the longest readout deadtime (CDC) next FY. - Repeat replacement year-by-year and move to fully pipelined readout system in 3 years. - Further upgrade (for SuperB) are managed by replacing FINESSE + increasing no. of modules. * Modularize backend DAQ (event builder+reconstruction farm) and add new units whenever more processing power is required.

11 Higuchi Common Readout Platform: COPPER Form factor = VME 9U FINESSE PMC Processor FINESSE O(100) of the COPPER boards are used by each subdetector system. - Developed in cooperation with KEK electroncs group Ready for Mass Production FINESSE FINESSE modules Trigger FINESSE On-board Ether Generic PMC slot COPPER module by KEK. - Common Readout Module to handle pipelined readout - Digitizers are implemented as daughter cards (FINESSE) - Works at >30KHz!

12 Near-term Upgrade of Digitizers Replace FASTBUS TDC system with COPPER based TDC system COPPER : Common readout module to handle pipeline readout Event Builder Event Builder GbE Trigger (SEQ) FastEther Gate Generator TDM FPI Controller Readout PC VME 6U GbE Network SW FastEther COPPER TT RX TT RX TT RX TT-SW Trigger COPPER COPPER LeCroy 1877S LeCroy 1877S LeCroy 1877S FASTBUS VME 9U Xn

13 Near-term Upgrade of Event Builder/RFARM Current DAQ : Readout subsystems are connected to single Event Builder through point-to-point network connection CDC TOF ECL KLM VTX VTX CDC TOF ECL KLM VTX VTX VTX VTX VTX VTX Event Builder Transfer Network Matrix - Modularize (Event Builder + RFARM) as a unit - Have multiple units Event Builder RFARM Event Builder RFARM Event Builder RFARM RFARM -2-1 L=1.5x1034cm sec /unit

14 Design for SuperKEKB Current DAQ Input: ~ 100K channels >10 Event Building Farms ~1000 Pipeline ROM(COPPER) (pipelined readout) mass storage... ~50 Readout PCs Transfer Network >10 L3 Farms... all components are Linux-based PC's

15 !! d e at Estimated DAQ condition at SuperKEKB Upd L1 trigger rate Belle(L=1.5x1034) SuperKEKB(L=5x1035) 500 Hz 20 khz Maximum trigger rate 650 Hz Event size at L1 40 kb/ev Data flow rate at L1 25 MB/s 9 GB/sec Data flow at storage 13 MB/s 250 MB/sec Subdetector readout HLT reduction khz 300 kb/ev >

16 Detector SuperKEKB Quick Summary - SVD : CMS APV25 chip - Pixel : MAPS(CAP3) or striplet (APV25) - CDC : 2 stage upgrade 1) Pipelined TDC with Q-to-T conversion (shorter shaping time) 2) ADC with waveform sampling (10bit@>100MHz) - ECL : Wave form sampling needed to manage pileup effect (14bit FADC@2MHz for barrel, >20MHz for pure CsI) - TOP/RICH : Need to manage pixel photo-detector * Time stretcher, HPTDC, Analog pipeline - KLM : Readout scheme is not so much different from Belle's regardless of choice of detection device (RPC/Sci. Tile) * "hit" info multiplexing + on-board data compression

17 Higuchi TDC FINESSE 24 ch LVDS input (96 ch / COPPER) ~150 COPPER boards in total for the SuperBelle CDC. Time resolution 0.78 ns/bit (w/ 40MHz clock) ~ 27 m position resolution Dynamic range = 17 bit equivalent to 100 s pipeline depth Linearity = 0.49% TDC chip: AMT-3 Originally designed for ATLAS

18 Flash ADC FINESSE 8 ch differential input Sampling clock = 65 MHz Dynamic range = 12 bit Linearity = 1.2% Equips 512 word/ch FIFO (500 MHz FADC FINESSE of 2 ch / 8 bit has also been developed) The FINESSE with higher channel density is under design. * Current prototypes : channel density is too low * Needs to develop high-density 10bit/100MHz ADC (~ 100 ch / module (VME 9U) ) -> can be used for CDC and PID Higuchi

19 2004/5 Hawaii FINESSE Efforts CuEval Varner (COPPER2) HPTDC LAB2 8 chan. * 256 samples 128x Wilk ADCs 8x HS Analog out, 1x MUX out TOF/TOP/F-DIRC electronics 19

20 HPTDC FINESSE HPTDC chip 32-channels (8 channel HP mode) Varner Spartan-3 FPGA COPPER Interface 20

21 SVD Based on IBM 0.25µm technology Input stage: shaping time: 50nsec ENC(e)=270+38/C (pf) or 2000 electrons at 45 pf input capacitance Analog deconvolution is possible but will not be used in Belle SVD. 160 out of 192 stage analog pipeline operated at 40 MHz clock Overview of APV25 ~4 µsec trigger latency 30 events can be queued for readout 40 MHz analog multiplexing (3+ ) µsec for 128 channel readout) 2 mw/channel Tsuboyama

22 Schwanda Readout electronics front end: APV25, Vienna repeater (not the final version, a new version with AC coupling and base line restore will be ready in April) 15m CAT5 cable (like SVD2) back end: Vienna readout system with programmable APV sequencer and fast ADCs (same as on CMS Pixel FED)

23 Schematics of the ADC-Pixel with the possibility of single channel processing and output with data for trigger processor (largely exists) Schwanda TTC input optical connection VME protocol Altera 4 times 10 bit 4 clocks with data adjustable phase 12 in p ut o pt 4 ADC Altera Daughter 9 inputs 9 data proc + FIFO s Transmit crate clock, P control 0 signals and event number 64 (or 32 bit) bit data bus 40 MHz+4 control lines CMS Delayed clock and control sig.distributer, VME control 1 9 lines with information for trigger proc. TTC P Altera daughter P Data 2 for trigger, serial with final FIFO Control bus 2 clocks phase shifted P Fast data transfer to PCI 3 * Signal processing on FPGA for occupancy reduction Vienna group has two ideas on the algorithm

24 Nishida PID

25 Nishida PID

26 Schwartz * Wave form sampling is required

27 Schwartz

28 Schwartz

29 Role of FINESSE - Two implementations are cosidered 1. On-board digitizers - Original idea - ~ 100 channels / 4 FINESSE cards = 1 COPPER module - AMT based TDC, high-speed ADC cards are being developed 2. Interface to outside digitizer system - For complicated readout electronics unified with digitizers i.e. SVD (APV25), Pixel (CAP), ECL, etc. - Standard interface FINESSE is being considered ex. Optical S-link

30 Upgrade Timeline FY2004: - Complete R&D on COPPER Almost done TDC FINESSE design and production in progress FY2005: Summer - Replacement of EFC TDCs with COPPER TDCs - 2nd unit of Event Builder + RFARM Winter (during crab cavity installation) - Replacement of CDC readout FY2006: - New timing distribution system - Replacement of KLM and TRG readout FY2007: - Replacement of TOF and ACC readout - 3rd unit of Event Builder+RFARM (if necessary) - SVD readout upgrade + inner SVD upgrade - Full upgrade of readout for ECL (wave form smpl.) FY20xx: - Full upgrade with new electronics / new FINESSE - Operation with >10 units of Event Builder+RFARM Su B r pe

31 Conclusions of TRIG/DAQ WS Adiabatic upgrade scenario to pipelined readout + modularized backend meets both requirements by near-term and SuperB upgrades. -> The scenario was approved. - Upgrade project has already started. 2. The design goal for DAQ at SuperKEKB has been updated and it was confirmed that current approach can satisfy the requirements even with the luminosity of L= 5 x 1035cm-1sec COPPER based readout system is ready for mass production. 4. Development of FINESSE cards for each subdetector is now going on.

32 Backup Slides

33 K.Ito(Tokyo) Performance test of Transfer Network Matrix 1000Base-T Dual Xeon(3.06GHz), RedHat9 PC PC PC PC PC PC PC PC PC PC PC PC PC PC PC PC PC Sender Receiver PC Test Bench at KEK 6x6 network matrix Evolution of data transfer rate was studied by adding reciever nodes up to 6.

34 Measured Performance typical data size Scalabilit y EventRate (receiver 2 ~ 6) EventRate (receiver 1) At typical data size # receiver PC = 6 increase K.Ito # receiver PC = 1 - Performance of Transfer Network Matrix is proven to be scalable up to 6 output nodes. No performance degradation by adding 2nd,3rd... Event Builder+RFARM units

35 Higuchi's talk COPPER based TDC Idea: Build a TDC module compatible with 1877S as possible using COPPER + FINESSE TDC => Pipelining of digitizers becomes possible without modifying frontend electronics LeCroy 1877S Multi-Hit TDC * 96ch/module, 16hits/channel, 16bit(500ps/LSB) * equipped with LeCroy's MTD133B chip COPPER + TDC FINESSE x 4 * Based on AMT3 chip (16bit(780ps/LSB)) - Some difference from MTD133B * depth of multi-hit buffer (256 words for 24ch) * method of multi-hit recording (FIFO vs. Buffer full handling) * TDC FINESSE - 48 ch / 2 FINESSEs - The same input connectors as that of 1877S's (16 inputs * 6 ) - differential ECL input -> needs LVDS conversion

36 Evolution of intrinsic dead time for higher trigger rate w/o Event Builder Upgrade * Dead time evolution is not linear to trigger rate. * Prediction is obtained by a fit to 0 ~ 550 Hz region with a 2nd order polynomial * Prediction has a large ambiguity.