Robustness improvement of an SRAM cell against laser-induced fault injection

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1 Robutne improvement of an SRAM cell againt laer-inuce fault injection Alexanre Sarafiano, Mathieu Liart, Olivier Gagliano, Valérie Serraeil, Cyril Rocian, Jean-Max Dutertre, Aia Tria To cite thi verion: Alexanre Sarafiano, Mathieu Liart, Olivier Gagliano, Valérie Serraeil, Cyril Rocian, et al.. Robutne improvement of an SRAM cell againt laer-inuce fault injection. Defect an Fault Tolerance in VLSI an Nanotechnology Sytem (DFT), 2013 IEEE International Sympoium on, Oct 2013, New York, Unite State. < /DFT >. <eme > HAL I: eme Submitte on 24 Jan 2015 HAL i a multi-iciplinary open acce archive for the epoit an iemination of cientific reearch ocument, whether they are publihe or not. The ocument may come from teaching an reearch intitution in France or abroa, or from public or private reearch center. L archive ouverte pluriiciplinaire HAL, et etinée au épôt et à la iffuion e ocument cientifique e niveau recherche, publié ou non, émanant e établiement eneignement et e recherche françai ou étranger, e laboratoire public ou privé.

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3 Defect an Fault Tolerance in VLSI an Nanotechnology Sytem (DFT), 2013 IEEE International Sympoium on Robutne improvement of an SRAM cell againt laer-inuce fault injection Alexanre Sarafiano, Mathieu Liart, Olivier Gagliano, Valérie Serraeil STMicroelectronic Rouet, France Cyril Rocian, Jean-Max Dutertre, Aia Tria Centre e Microélectronique e Provence - George Charpak Garanne, France Abtract Thi paper preent the eign of an SRAM cell with a robutne improvement againt laer-inuce fault injection. We report the fault enitivity mapping of a firt SRAM eign. A careful analyi of it reult combine with the ue of an electrical moel at tranitor level of the photoelectric effect inuce by a laer permit u to valiate our approach. The robutne improvement i ue to a pecific layout which take into account the topology of the cell an to the effect of a triple well implant on the laer enitivity of NMOS tranitor. Keywor-component; SEU; SRAM cell; pule PLS; 1064nm wavelength; electrical imulation, robutene I. INTRODUCTION SRAM memory cell are prone to Single Event Upet (SEU) when expoe to ionizing particle hit (in harh a raioactive environment). An SEU conit in an inverion of the ata bit tore by the truck SRAM. SEU were trongly take into account when further problem were oberve in pace electronic evice uring the 1960 ue to the high expoition of chip embee in pace vehicle to raioactive particle emitte mainly by the un. Nowaay, SEU i yet a major threat for emiconuctor manufacturer. The robutne of chip againt SEU coul be tete by a cyclotron or pule laer equipment uing the Photoelectrical Laer Stimulation (PLS) effect inuce in ilicon. However thi kin of experiment coul be very expenive an time conuming. Phyical (i.e. TCAD) imulation [1, 2] may be ue, but a Spice imulation i fater [3]. In thi context, it i intereting to ue a imulation tool at gate level in orer to imulate with goo accuracy the effect of PLS on a chip in orer to analyze it enitivity to SEU in a very mall amount of calculation time. In thi paper, we preent an electrical moel of the backie PLS of an SRAM cell in 0.25 µm CMOS technology. We ue a pule laer at 1064 nm wavelength to conuct the PLS experiment. The obtaine meaurement were ue to buil an electrical moel of the cell uner PLS an to analyze it behavior. Thi electrical moel make it poible to imulate the repone of the SRAM cell to laer pule in a very mall amount of calculation time. Moreover, comparion between imulation an meaurement will rather be qualitative than quantitative ue to the fact that the electrical moel of PN junction uner PLS wa tune thank to meaurement on a STMicroelectronic 90 nm technology. Electrical moel of PN junction uner pule laer timulation (N+ on Pubtrate, P+ on Nwell an Nwell on Pubtrate) were previouly introuce [4, 5]. We have alo alreay introuce electrical moel, bae on preliminary tuie mae from meaurement an TCAD imulation [6, 7] for continuou PLS at low laer power (uner ~100 mw), which create only photoelectrical effect [8, 9]. Thi moel conit in a imple current ource controlle by voltage to moel the laer inuce photocurrent. The novelty of the moel preente in thi paper i that it i the firt moel of a relatively complex CMOS cell mae from NMOS an PMOS tranitor uner pule PLS which take into account the topology of the target (i.e. the layout of the cell) relatively to the effect area of the laer beam which have a Gauian-like intenity profile. Thi paper i organize a follow. Section II preent, from a theoretical point of view, the SEU enitivity of an SRAM cell expoe to PLS. In theory four enitive area are expecte. Section III report meaurement on an actual SRAM cell. It turn out that only three enitive area were reveale: a making effect of the forth enitive area appeare. The Gauian intenity profile of the laer beam an the topology of the cell coul explain thi unexpecte reult. Moreover, electrical moeling an relate imulation confirm thi particular reult. Senitivity map obtaine from imulation an meaurement howe a very goo correlation. Thi valiate the relevance of our imulation tool. In ection IV, a new olution to increae the SEU robutne of a tanar ix tranitor (6T) SRAM cell i introuce. Thi new eign involve the ue a triple well (eep Nwell) implant uner the NMOS tranitor of the SRAM cell an a careful poitioning of the cell tranitor. The latter technique take avantage of the SEU enitive area making effect analyze in ection 3. The new 6T SRAM cell wa then tete with our electrical moel. Finally, our fining are ummarize in the concluing ection V with ome perpective.

4 II. EFECT OF SINGLE EVENT UPSET ON AN SRAM CELL The photoelectric effect i generate by a laer beam paing through ilicon provie that it photon energy i greater than the ilicon ban gap [10]. Thi effect create electron-hole pair along the laer path. Generally thee pair recombine an there i no noticeable effect on the IC behavior. However, uner pecific conition, ome uneire effect may appear: the o-calle Single Event Effect (SEE). A SEE happen when the charge carrier (i.e. electron an hole) create by the laer beam are rifte in oppoite irection by the electrical fiel foun in the PN-junction of CMOS tranitor intea of recombining. A a conequence a tranient current (i.e. moving charge carrier) i generate through the truck junction. After the creation of the electronhole pair along the laer beam, two phenomena lea to the creation of the tranient current: the prompt charge collection, or funneling, an the iffuion. The firt phenomenon tretche the epletion region (where it exit a trong electric fiel) along the laer beam, within a few picoecon the charge nearby are collecte giving a current peak. Then, in a econ time, the remaining charge are collecte in a longer iffuing cheme: the iffuion [11]. When uch a tranient current i inuce in the logic of a memory cell it may caue the flipping of it logical tate: a o-calle SEU. A. Decription of the tuie SRAM cell The cell tuie in thi ection of the paper i a configuration SRAM (CSRAM) mae of five tranitor (ee fig. 1) imilar to thoe ue to tore the configuration bittream in programmable evice (FPGA). The SRAM i embee in a tet chip eigne in a CMOS 0.25 µm proce. However, we will rather ue the term SRAM in thi paper, ince it main reult may be generalize to 6 tranitor SRAM cell. V V Figure 1. Schematic of the CSRAM cell. When the election ignal () i at a high tate (= 1 ) the SRAM cell i in write moe: i applie to noe through tranitor. Thi value i then latche by the two couple inverter mae from,, an. In the following the enitivity of the cell to PLS i tuie accoring the SRAM cell chematic an it bia conition. A enitive noe of a CMOS gate i efine a a noe in a circuit whoe electrical potential can be moifie by internal injection or collection of electrical charge. B. Stuy of the SEU enitivity of the SRAM cell In thi ubection, the SRAM SEU enitivity i tuie from a theoretical point of view (coniering it chematic an it tate) in it hol tate (i.e. it acce tranitor i OFF).We refer to tate one (repectively tate zero) when the noe i in high tate (rep. low tate). The enitivity of the cell can be invetigate by coniering which PN junction are the mot revere biae in function of the SRAM tate. Inee, thee revere biae PN junction are the place where the electrical fiel i trong enough to generate a tranient current likely to inuce an SEU. Two cae are coniere: tate 1 an. The re arrow in figure 2 an 3 alo give the irection of the inuce photocurrent between the tranitor rain an bulk or ource an bulk. The thick arrow repreent trong photocurrent, the thin arrow maller one. V 1 High laer enitivity Small laer enitivity V Figure 2. Schematic of the SRAM cell laer enitivity in tate 1. In tate 1, epicte in fig. 2, the two mot enitive area to laer illumination are the rain junction of an. In tate, epicte in fig. 3, the intenitie of the inuce photocurrent are inverte in comparion with the tate 1 : the two mot enitive area are the rain of an / (note that an hare a common rain iffuion, ee the SRAM layout in fig. 5). Therefore four enitive area are expecte: two in tate an two other in tate 1. 1 High laer enitivity Small laer enitivity V V Figure 3. Schematic of the SRAM cell laer enitivity in tate.

5 III. MEASUREMENT AND ELECTRICAL MODDELING OF THE SEU SENSITIVITY OF AN SRAM CELL A. Meaurement The SRAM tet erie were performe with a pule laer equipment (at 1064 nm wavelength, 0.16 µj energy, an 50 n pule uration). The laer beam pot iameter wa et to 1 µm. Injection experiment were performe by expoing the front ie of the SRAM cell. Thi cell wa eigne with a minimum of metallization, in orer to be able to perform front ie an backie laer injection. The aborption of the ilicon at 1064 nm wavelength i weak. The carrier are alo eeply create an can rift quite for approximately 10 or more µm. Thee two phenomena have probably a effect to increae the urface of the enitive area in comparion with comic ray, which are more point ource in comparion with the iameter of our laer pot. However, the SEU enitivity mapping we have obtaine in thee conition i rawn in figure 4. Dark re color i ue to epict SEU enitivity in tate, an blue color to epict SEU enitivity in tate 1. A the laer pot i targeting a re cae on thi map an provie the SRAM i in tate an SEU occur: the cell flip to tate 1. Repectively, a the laer pot i targeting a blue cae on thi map an provie the SRAM i in tate 1 an SEU occur too: the cell flip to tate. Moreover, the tren in continuouly reucing the technology ize make it very ifficult to illuminate only one junction without creating effect on the other. Thi i the reaon why it i neee to take into account the topology an ize of the cell an the effect of the laer on everal junction at the ame time. The layout of the tuie SRAM cell i epicte on figure 5. It ize i 4x9 µm. Note that tranitor an have a hare rain iffuion (which i cloe to the rain of ). Figure 5. Layout of the SRAM cell. We mae the hypothei that thi layout ha the effect to mak the enitivity of rain (which i the miing enitivity area in fig. 4). Figure 6 illutrate thi making effect which originate from the photocurrent generate by the rain hare between an (blue arrow) that counterbalance the effect of the photocurrent inuce in the Drain/Nwell junction of (croe arrow). Thi effect lie in the proximity between the rain of an /, an alo in their izing. Therefore with a topological approach there i only one enitive area in tate 1 which i the rain/pubtrate junction of. There i no uch imilar counterbalancing effect in tate. Figure 4. Experimental SEU enitivity map of the SRAM cell at a laer energy equal to 0.16 µj. Only three enitive area were experimentally reveale (ee fig. 4), epite four were theoritically expecte. An explanation of the icrepancy between theory an experiment lie in the fact that the previou theoritical analyi wa mae accoring the aumption that a laer hot only affect one enitive area. However, thi aumption oe not hol experimentally becaue PLS may inuce photocurrent in everal PN junction epening on the target topology an on the location an ize of the laer pot. Inee, the laer beam effect area ha a Gauian like profile an it effect may exten beyon the pot ize. V 1 High laer enitivity Small laer enitivity Deacreae enitivity of the Drain of Figure 6. Schematic of the SRAM cell laer enitivity in tate 1, with a layout approach. V

6 It i then propoe to illutrate thank to electrical moeling the effect of the cell topology which give only three enitive area, while four are expecte in theory. B. Electrical moeling In thi ection we preent an electrical moel of the SRAM cell uner Photoelectrical Laer Stimulation. In thi moel we conier that the laer power ue in meaurement an electrical imulation are not capable to trig the ifferent paraitical bipolar tranitor preent in thi cell [12]. For every PN junction, a ub circuit which contain a pecific controlle voltage current ource i ae to the netlit of the SRAM cell (See Fig. 7) to moel the laerinuce photocurrent. Thee moel were built an valiate from actual meaurement on tranitor. Thi reearch work i reporte in [5, 6]. V Inee, our electrical moeling coul reveal the number of enitive area ant a tren of their urface. C. Meaurement veru electrical imulation In thi ection, cartographie mae from our electrical moel are preente. We ue a 0.5 µm tep to raw the SEU enitivity map epicte in figure 8. The imulator wa ue in orer to take into account the topology of the target relatively to the location of the laer beam. SEU enitivity in tate i rawn in re, wherea SEU enitivity in tate 1 i rawn in blue. Thee imulation reult are well correlate to the meaurement reult (cf. figure 4): the enitivity of rain in tate 1 i make. Thi provie a high confience in the valiity of our moeling of PLS at tranitor level an of it ue to perform SEU enitivity tuie. The next ection report the ue of thi methoology to analyze an improve the SEU enitivity of a 6T SRAM cell. V V Nw/Pub V V N+/Pub P+/Nwell V V Figure 7. Electrical moel of the SRAM cell uner PLS. The current amplitue of the current ource of each PN junction i efine thank to equation preente on Table I. TABLE I. EUATIONS WITH COEFFICIENTS WHICH CONTROL THE PHOTOCURRENT GENERATED BY THE PN JUNCTIONS OF THE SRAM CELL DURING THE LASER PULSE. a p P 2 laer I ph q P ( a V b) S V laer r b gau P laer laer _ trig Coefficient N+/Pub P+/Nwell Nwell/Pub p 4E -9 9E -5 6E -11 q -5E -7 2E -4 9E -9 r 9E -6-5E -6 1E -7 4E E -3 6E -8 gau 2 2 ( ) exp w c exp c 1 2 I ph i the photocurrent generate uring the laer pule expree in Ampere. P laer i the laer power expree in Watt. The function α gau expree in % i a function which efine the patial epenency of the photocurrent ( i the itance, expree in µm, between the laer pot an the PN junction of interet). In thi layout there are ome junction which are hare (ource of an, ource of an, an rain of an ). It i the reaon why only eight ub circuit are connecte to the SRAM netlit. Reult obtaine in electrical imulation are more qualitative than quantitative. Figure 8. Simulation-bae SEU cartography of the SRAM cell. IV. SRAM ROBUSTNESS IMPROVEMENT The firt part of thi ection ecribe attempt to ecreae the number of enitive area by uing the previouly ecribe making effect. The econ part report the ue of triple well (eep Nwell) implant [15] to obtain a further ecreae of SEU enitivity. The tuy wa one now on a tanar 6T SRAM cell eigne in CMOS 90 nm technology. A. Decreaing the number of SEU enitive area The chematic of the 6T SRAM cell i preente in fig. 9. BL WL V V WL MN4 Figure 9. Schematic of the tanar 6T SRAM cell. BL

7 In tate (efine for in low tate), a making effect of SEU enitivity (imilar to that ecribe in the previou ection) may be obtaine by placing the hare rain of the NMOS tranitor an in it cloene. Likewie, in tate 1 (efine for in high tate), the SEU enitivity of rain may be make by placing the hare rain of an MN4 cloe to it. The previou placing contraint were ue to raw the layout of the 6T SRAM cell a epicte in figure 10 (we have alo followe the guieline given in [14] for the rawing of SRAM layout). moifie trongly the collection charge mechanim which occur on an NMOS tranitor. In thee conition the mot important photocurrent are generate by the eep Nwell/Pubtrate an the eep Nwell/Pwell junction, which have for effect to ecreae the photocurrent generate by the two N+/Pwell junction. Moreover, but in mall proportion, thi implant create an optical interface between the eep Nwell an the Pubtrate: a reflection phenomenon take place. A a reult, ue to thee two effect, the inuce photocurrent at the NMOS tranitor N+/Pwell junction houl be reuce. In orer to tuy the influence of the eep Nwell implant on an NMOS tranitor we have compare the photocurrent generate on an NMOS tranitor, in OFF tate, with an without eep Nwell. The biaing conition of the NMOS eep Nwell tranitor are the following: the ource, the gate an the triple well are biae at 1.2V, an the Pubtrate, the Pwell an the rain are groune. Figure 12 preent the photocurrent meaure on NMOS tranitor with an without a eep Nwell implant. Figure 10. New layout of the more robut SRAM cell. The correponing SEU enitivity map rawn from electrical moeling of PLS an imulation i given in figure 11. Figure 11. SEU enitivity map of the 6T SRAM cell. Thi layout olution of the 6T SRAM cell ha remove the two enitive area of an (one more than for the 5T SRAM cell thank to the aitional acce tranitor MN4). However there are alway two remaining enitive area which are the hare rain of NMOS tranitor /MN4 an /. In the following a olution i propoe to ecreae the threhol of thee enitive area. B. SRAM cell uing triple well implant 1) Triple well effect on NMOS tranitor a) Meaurement Another approach in orer to increae the robutne of the SRAM cell uner PLS i to ue triple well implant (i.e. a eep Nwell implant) uner NMOS tranitor. Thi implant Figure 12. Photocurrent generate on an NMOS tranitor with (left) an without eep Nwell (right). The photocurrent meaure on the rain (ID) an the ource (IS) of the NMOS tranitor with eep Nwell are negligeable in comparion with the photocurrent generate by the eep Nwell/Pubtrate junction (IPW an IDeep Nw). Thi reult i confirme by TCAD imulation. The triple well implant (which alo create a trong photocurent generation between the eep Nwell an the Pubtrate) lea to a ecreae by a factor of 10 of the photocurrent inuce in an puhe through the rain of the NMOS. The latter photocurrent i the one that may caue a SEU. b) TCAD imulation In orer to confirm the tren een in meaurement, TCAD imulation were ran. Two TCAD tructure were built: a tanar NMOS tranitor (fig. 13a), an a NMOS with eep Nwell tranitor (fig 13b). Figure 13. TCAD cut with (a) an without eep Nwell implant (b).

8 Reult of the photocurrent generation between an N+/Pubtrate junction an an N+/Pwell junction are preente in table II. A een in meaurement, the eep Nwell implant ecreae the photocurrent generation on the rain of the NMOS tranitor. TABLE II. COMPARISON OF THE PHOTOCURRENT GENERATION BETWEEN AN NMOS TRANSISTORI WITH AND WITHOUT DEEP NWELL. IDNMOS (A) IPub (A) STD 3.1E E-10 eep Nwell 1.1E E-9 2) New layout propoal of the 6T SRAM cell uing triple well implant A triple well (eep Nwell) wa ae to the layout epicte in figure 10. The ame kin of electrical imulation for the purpoe of rawing it SEU enitivity cartography wa then ran. The moel we ue took into account the effect of the triple well on PLS (the moel wa tune thank to the actual meaurement reporte previouly). At the ame imulate laer power which wa ue in orer to raw the electrical cartography preente in figure 11, all the enitive area of the cell have iappeare. An increae by a factor of 4 of the imulate laer power i neee to make it reappear. V. CONCLUSION An analyi of the laer inuce enitive noe of an SRAM cell wa firtly reporte in thi paper. The preliminary concluion of thi theoretical analyze wa that there are two enitive area of the SRAM cell which moify the output from to 1 an two other for an output tate moification from 1 to. However thi concluion wa not verifie in practice. The topology of the cell ha a trong impact on the enitivity of a CMOS gate. A making effect occurre: only one area which moifie the output noe from 1 to wa reveale. Thi phenomenon reveale by meaurement cartographie wa alo confirme by proper electrical imulation that take into account the topology of the target an the inuction of photocurrent in everal enitive noe. The valiity of the approach wa aee by the very goo correlation obtaine between electrical imulation (bae on SPICE language) an meaurement. Thi moel permit u to propoe an to valiate (on imulation bai) a new layout of a tanar 6T SRAM cell more robut againt SEU. The SEU robutne of PMOS tranitor i obtaine thank to the making effect provie by the photocurrent inuce in the NMOS enitive junction. We alo ue a eep Nwell implant to increae the SEU robutne of the SRAM NMOS. A a reult the SEU enitivity threhol of the SRAM wa ignificantly raie. The main interet in increaing the robutne of CMOS gate i that it will be neceary to increae the laer power in orer to obtain the ame effect. Thi laer power increae coul be more eaily etecte by SEU enor which coul be embee on a chip [15]. Moreover, thi enitivity improvement of the cell coul permit to ecreae the number of thee enor on the ie too. A a concluion we can ay that the electrical moel preente in thi paper coul be an intereting tool for eigner who want to buil more robut CMOS gate againt SEU effect or againt fault injection in the ecurity fiel. REFERENCES [1] R. Minixhofer, "TCAD a an integral part of the emiconuctor manufacturing environment", Simulation of Semiconuctor Procee an Device, pp.9-16, [2] P. E. Do, Phyic-Bae Simulation of Single-Event Effect, Tranaction on evice an material reliability, vol. 5, N 3, [3] ELDO uer Manual Software Verion 6.6_1 Releae Mentor Graphic uer manual, [4] A. Sarafiano, J-M Dutertre, O. Gagliano, M. Liart, V. Serraeil, A. Tria, " Electrical moeling of the photoelectric effect inuce by a pule laer applie to an NMOS tranitor.," IRPS In pre. [5] A. Sarafiano, J-M Dutertre, O. Gagliano, M. Liart, V. Serraeil, A. Tria, " Electrical moeling of the photoelectric effect inuce by a pule laer applie to a PMOS tranitor.," IPFA In pre [6] R.Llio, A. Sarafiano, O. Gagliano, V. Serraeil, V. Goubier, M. Liart, G. Haller, V. Pouget, J.M. Dutertre, A. Tria, Characterization an TCAD Simulation of 90nm Technology NMOS Tranitor Uner Continuou Photoelectric Laer Stimulation for Failure Analyi Improvement, IPFA [7] R.Llio, A. Sarafiano, O. Gagliano, V. Serraeil, V. Goubier, M. Liart, G. Haller, V. Pouget, J.M. Dutertre, A. Tria, Characterization an TCAD Simulation of 90nm Technology NMOS Tranitor Uner Continuou Photoelectric Laer Stimulation for Failure Analyi Improvement, IPFA [8] R.Llio, A. Sarafiano, O. Gagliano, V. Serraeil, V. Goubier, M. Liart, G. Haller, V. Pouget, J.M. Dutertre, A. Tria, Characterization an TCAD Simulation of 90nm Technology NMOS Tranitor Uner Continuou Photoelectric Laer Stimulation for Failure Analyi Improvement, ISTFA [9] A. Sarafiano, R. Llio, O. Gagliano, J.M. Dutertre, M. Liart, V. Serraeil, V. Goubier, V. Pouget, D. Lewi, A. Tria, Builing the electrical moel of the Photoelectric Laer Stimulation of an NMOS tranitor in 90nm technology, ISTFA [10] A. Sarafiano, R. Llio, O. Gagliano, J.M. Dutertre, M. Liart, V. Serraeil, V. Goubier, V. Pouget, D. Lewi, A. Tria, Builing the electrical moel of the Photoelectric Laer Stimulation of a PMOS tranitor in 90nm technology, ESREF [11] Habing, D.H.: The ue of laer to imulate raiation-inuce tranient in emiconuctor evice an circuit. In: Nuclear Science, IEEE Tranaction on. Volume 12. (1965) [12] Wang, F., Agrawal, V.: Single event upet: An embee tutorial. In: Proc. of 21t International Conference on VLSI Deign. (2008) pp [13] M.A. Bajura et al, Moel an algorithmic limit for an ECC-bae approach to harening ub-100-nm SRAM, IEEE Tran. Nucl. Sci., vol. 54, no. 4, pp. 935, Aug [14] M.Ihia et al., A novel 6T-SRAM cell technology eigne with rectangular pattern calable beyoun 0.18µm generation an eirable for ultra high pee operation, Int Electron Device Meeting Tech. Digitet, 1998, pp [15] Puchner, H.; Xu, Y. Z.; Raaelli, D., "Avance SEU engineering uing a triple well architecture [CMOS SRAM]," Soli-State Device Reearch conference, ESSDERC Proceeing of the 34th European, vol., no., pp.369,372, Sept [16] Neto, E.H.; Ribeiro, I.; Vieira, M.; Wirth, G.; Katenmit, F.L., "Uing Bulk Built-in Current Senor to Detect Soft Error," Micro, IEEE, vol.26, no.5, pp.10,18, Sept.-Oct