CHAPTER 1 Introduction

Transcription

1 CHAPTER 1 Introduction Modeling and simulation of lithography and topography for processes and inspection in fabricating integrated circuits are the subject of this monograph. The introduction begins by establishing an appreciation for the revolutionary impact of the planar IC process, its growth in complexity, and the pace at which technologists are being asked to develop future generations. The role of modeling and simulation in pursuit of this evolving technology, the new opportunities challenging simulation, and essential ingredients necessary in simulation to meet these challenges are then discussed. The interrelationship between CAD tools for traditional IC circuit design and for device development and process technology Technology CAD (TCAD) are described. Process TCAD which follows the timeevolution of the device during processing is further divided into tools which describe the impurity distributions and those which track the topographical features. The latter which includes lithography and deposition and etching simulation is the primary focus of this monograph and a short guide to the historical work and useful texts in the field is given. A brief explanation of the choice of the physically based viewpoint and organizational flow used in presenting the material throughout the monograph concludes this chapter. 1.1 IC Process Technology and Marching to Moore s Law Planar Process Silicon has been called the new steel because integrated circuit electronics is creating a economic revolution similar to that brought on by the introduction of steel in the 1800 s. In the late 1950 s discrete transistors at about 1 US each were replacing more expensive and less energy-efficient electronic tubes. At that time one major computer manufacturer went into its own components production when no supplier would commit to long term SIMULATION OF SEMICONDUCTOR LITHOGRAPHY AND TOPOGRAPHY - ARN 18

2 IC Process Technology and Marching to Moore s Law prices of 0.10$US per transistor. Then in 1959 a planar process [rzzplanar59kilbyand Noyce] was invented which consisted of simultaneously forming and interconnecting many transistors and other components on a single chip of silicon. Suddenly the price of an integrated circuit transistor began decreasing by 30% per year. This trend has continued for 30 years, resulting in over five orders of magnitude price decrease; several more orders of magnitude decrease will likely occur in the future. The initial success in integrating electronics was associated with the unique oxide forming properties of silicon. Today, however, technologies for processing integrated electronics with germanium, compounds such as gallium-arsenide, and micromechanical structures add a much greater richness to the variety of devices which can be made. In addition to oxidation the basic planar process steps include ion implantation, diffusion, lithographic pattern definition, pattern transfer through etching and deposition. At each mask level the lithography introduces device features by first patterning a resist material and then transferring that pattern into the underlying layers. The deposition and etching of layers in patterns causes the device features to evolve in the vertical direction as well giving rise to the device cross section or topography frequently seen in SEM s. The device structure evolves from properly coordinating the circuit layout of multiple mask levels with a sequence of processing steps or process flow. The circuit designer and process technologist agree in advance on a set of layout design-rules to assure proper spacing and overlap of the device features. The success of electronic integration is also based upon the degree to which massive parallelism and miniaturization have been achieved in the planar process. Today optical lithography can print features as small as 0.25 μm or 1/100 of the diameter of a human hair over more than a 1 cm 2 area in a fraction of a second. This pattern can then be stepped and repeated across a circular wafer of single crystal silicon from 100 to 400 mm in diameter. The entire wafer is then placed in a deposition-etching tool or furnace for the next process step in simultaneously forming over a billion of components. Just one of these wafers can contain enough product to pay for a college education! Increasing Complexity in IC Technology Today the planar process is evolving toward more complex processes involving increased mask levels and smaller features with higher aspect ratios. The layout and cross sections from a 16M bit DRAM process in Figure 1.1 illustrates these trends [rzz:bakeman.vlsi90]. In the layout the horizontal wordlines make a vertical jog around a contact (not shown) and the current flows from this contact in the vertical direction under the wordline to the node (or drain). From the node it flows horizontally through the surface strap into the storage trench where it is stored on the capacitance provided by a very thin (and difficult to see) insulator which lines the trench in the region between the polysilicon fill of the trench (area in (b) with grains) and the single crystal silicon of the substrate. Notice also in (b) the collar of oxide (dark material along sides of trench) near the top which reduces the capacitance from the polysilicon fill to the highly doped horizontal surface region of the adjacent node on the right side of the trench. The width of this trench is 0.5 μm and it is 9 μm deep. This 18 to 1 aspect ratio results in this DRAM cell made with the so called planar process having a cross section which is 9 times higher than it is wide. In the SEM in (c) the difficult problem of protecting the surface strap with photoresist for etching can be seen. This resist must be patterned deep in to the canyon between the polysilicon word 3/3/06 SIMULATION OF SEMICONDUCTOR LITHOGRAPHY AND TOPOGRAPHY - ARN 19

3 Introduction lines in three-dimensions. There are many technology issues which arise such as the change in W/L of the transfer device with misalignment, the effect of scattering from the polysilicon trench refill during alignment, and 3D lithography over canyons with 1 to 1 aspect ratios. (a) (c) (b) FIGURE Mbit DRAM (a) layout, (b) trench cross section and (c) surface strap formation showing a negative resist plug which has been successfully patterned down in a canyon formed by two polysilicon wordlines and used to etch a thin surface TiN strap between a diffusion node and a deep trench storage node [rzz.ibm.16dram.vlsi.1990]. A second example of the trends in today s planar devices is the 256M bit DRAM design using phase-shift lithography shown in Figure 1.2 [rzz:sagara.vlsi.92]. In (a) 0.25 μm lines and spaces have been formed by imaging a mask with the phases of the light between alternating apertures being out of phase by 180 degrees so that spillovers between features subtract. The exposure was made with 365 nm light and a negative resist. The resulting 0.25 μm resolution is smaller than the wavelength of light used to form the image! Due to the regularity of the underlying active device regions phase-shift techniques can also be used to create their oval shapes which form the contact (center), transfer gates (crossing polysilicon), and storage node contacts (oval ends). After covering with a thick oxide, holes are opened to the oval ends and CVD tungsten is used to connect to the node and 20 SIMULATION OF SEMICONDUCTOR LITHOGRAPHY AND TOPOGRAPHY - ARN 3/3/06

4 IC Process Technology and Marching to Moore s Law form one plate of a cylindrical capacitor structure as shown in (b). A thin insulator coating and a second CVD tungsten deposition then form the dielectric and top capacitor electrode. Again with this new phase-shift lithography and vertically stacked capacitor there are many new process technology issues which must be carefully explored. (a) (b) FIGURE 1.2 Polysilicon word lines with 0.25 μm lines and spaces patterned with phase-shift lithography at a wavelength of 365 nm and etching (a) SEM top view of line and space pattern and (b) SEM of the device cross-section [rzz:sagara.vlsi.92] Device Generation Scaling and Lithography Requirements The ground rules for each generation of devices evolve out of the hard work to develop exposure tools, masks, resist materials, and compatible processing. Standing back and looking at data from several generations as Gordon Moore has done [rzz:moore s.law] shows that the device feature sizes are on a forced march in which the features of the next generation are only 2/3 as large as those of the current generation. This trend in feature sizes for DRAM s as well as similar trends for chip area and device count have been used to calculate the key DRAM lithography requirements shown in Figure 1.3. These DRAM milestones are a bit simplistic and do not reflect the trend of microprocessor area to grow faster than that of DRAMs nor do they describe the tendency in logic to use more circuits running slower to reduce the energy required to perform a given calculation. Yet they are a convenient measure of the progress and future requirements in IC fabrication. In generating Figure 1.3 two rules have been assumed. First the linewidth is scaled by a factor s (which has an assumed value of 2/3 for the numerical values shown). S Linewidth = s = ( 2 3) (EQ 1.1-1) Second the number of features to form the bit cell per generation is taken to be a factor f (which geometrically over 4 generations reduces the feature count by a factor of 2 or 0.84). 3/3/06 SIMULATION OF SEMICONDUCTOR LITHOGRAPHY AND TOPOGRAPHY - ARN 21

5 Introduction FIGURE 1.3 Projected lithography needs for linewidth, chip area, and feature count for various DRAM generations. See text for the scaling rules used. S FeaturesCell = f = = ( 0.84) (EQ 1.1-2) Requiring 4 times as many bits per generation gives a rule for the chip area increase per generation (or a factor of 1.49 per generation). Note that the smaller linewidth and reduced features per cell are not, even together, able to prevent the chip area from increasing. S AREA = 4 s 2 f = 4 ( 2 3) = ( 1.49) (EQ 1.1-3) The increase in the number of features per chip each generation is simply the increase in capacity times the factor by which the number of features per cell decreases (or 3.36). This is about half an order of magnitude increase in the number of picture elements (pixels) which must be correctly patterned per generation even when some allowance has been made for advances in circuit and process cleverness. S = 4 f = = 3.36 (EQ 1.1-4) The starting point for Figure 1.3 is a 1.2 μm linewidth, 20 features per cell, an area of 0.6 cm 2 and a memory array area of half of the actual chip area for the 1 Mbit chip in The linewidth, number of features per cell, and chip area for each generation were then calculated and placed at 2.5 year intervals. While this model is clearly simplistic it reasonably matches the historical data as well as future projections. Regardless of whose data or models are used it is very clear that the march toward greater IC functionality is placing major demands on lithography and processing. Linewidths of nm and even nm are not that distant in the future and raise questions as to how far optical projection printing can be extended. Stitching of fields will likely be required once chip areas exceed several cm 2. Even today he number of features that must be simultaneously resolved by projection printers is higher than that used in lenses in any other application of optics. It is equivalent to photocopying 100 sheets of paper simultaneously without scanning. (At 600 dots per inch there are about 4x10 7 dots on a 8.5 inch by 11 inch page which is the number of minimum feature sizes on a Mbit DRAM.) 22 SIMULATION OF SEMICONDUCTOR LITHOGRAPHY AND TOPOGRAPHY - ARN 3/3/06

6 IC Process Technology and Marching to Moore s Law Yet cell projection electron-beam systems [rzz.okazaki] and optical scanning systems at 13 nm EUV wavelengths [rzz.tishner.1995] are appearing in the wings as candidates for cost effective lithography down into the 50 nm regime. In standing back and looking at the big picture it is also appropriate to question if lithography at 50 nm will ever be needed. The answer is not clear and is really as much a matter of product economics as it is of either process or device technology. Fortunately, from a device research point of view there are no show stoppers in that devices have been shown to work to down to channel lengths as small as 70 nm and below [rzz:sai- Halasz.iedm.1987]. Clearly the circuit design, device design and process technology will need to undergo major changes. There can be no doubt, however, that there will emerge a potential use for such circuit capability as history has proven anyone who predicted other wise to be in error. The real question is whether the expense to make these changes can be off set by the return on investment from the products which they make possible Critical Issues in Lithography and Pattern Transfer As feature sizes are reduced traditional optical projection printing has been facing increasingly more difficult challenges in reproducing on the wafer what the designer specifies in the layout. The challenge in optical lithography is to produce the resolution required while simultaneously maintaining an adequate depth of focus. Various methods are being pursued to extend the limits of optical lithography. These include lenses which collect more off-axis waves with 1) higher numerical apertures, 2) shorter DUV wavelengths at 248 nm and below, very soft 13 nm x-rays in the Extreme Ultraviolet range in 3) EUV systems, 4) improved resist materials, and 5) super-resolution techniques. For resolution of 100 nm and beyond an EUV system with all-reflective optics looks promising. Research is also being conducted on direct-write electron beam lithography, projection electron-beam and ion-beam lithography. Patterning approaches based on massively parallel scanning and imaging arrays are also being explored which exploit the parallelism possible in microfabrication techniques. The resist reaction to the incident aerial image and the pattern transfer process must be consistent with creating well defined resist profiles and device features. Near the limit of optical resolution the optics tends to deliver a sine wave approximation to the openings in the mask. The chemistry must then convert these sine waves into square resist profiles. The image in the resist is thus a less than an ideal copy of the designed layout pattern. Figure 1.4 compares an SEM of a the printed resist image with the initial mask. Here a terminating line perpendicular to a passing line is designed to have a minimum feature size separation. The resist profile in the SEM differs significantly from the design especially in that the terminating line is noticeably foreshortened. A considerable portion of the terminating line appears to be affected by the proximity of the passing feature. The foreshortening in this particular example is particularly severe because both the imaging effects and the resist process effects additively combine. An important final step is the pattern transfer of the resist profile into the device structure. There are many resist material and related etching issues [Zeiger] [Reinberg]. And the resulting nonidealities in the pattern transfer steps of etching and deposition are also a concern in modern process development and characterization. 3/3/06 SIMULATION OF SEMICONDUCTOR LITHOGRAPHY AND TOPOGRAPHY - ARN 23

7 Introduction FIGURE 1.4 Top down SEM of imaged photoresist on a wafer with the outline of the mask superimposed for comparison [ref.zuniga.sem]. Inspection of lithographic features and patterned wafers is also a major challenge. Much of the technology used and many of the issues in optical and electron-beam lithography are also common to optical and electron-beam inspection. While lower intensities can be utilized the inspection problem is often even more difficulty because the inspection tool must be about an order of magnitude more accurate to provide proper feedback. Optically, for example, very sophisticated techniques are needed to utilize phase effects and make their sensitive reflect only the feature shape changes essential to a successfully formed product wafer. While optical inspection and monitoring are much more convenient they will slowly give way to more accurate electron-beam and even ion-beam inspection. Integrating knowledge of resolution enhancement effects, optical proximity effects, resist dissolution, and pattern transfer into an overall view point which spans both IC design and process development is the principle difficulty in extending the limits of optical lithography. There is a very complex interrelationship between the lithography exposure tool, the resist material, its processing, and pattern transfer. While historically IC design and process development have been successfully partitioned through the introduction of design rules significant gains will come from IC designers and lithographers working together to establish restricted sets of layout pattern shapes which can be produced with good latitude in processing The Product Design Cycle Developing a product which is based on a new technology requires a multiple year collaboration between Circuit Designers, Process Technologists and Manufacturing Engineers. An overview of the time history of this collaboration for the development of a new generation of a microprocessor is shown in Figure 1.5 [rxx.hatz.mem]. The horizontal axis which is time in years shows that this activity can easily take 5 or more years. Each row shows the activities of the three participating teams throughout the product development. The vertical arrows show occasions when considerable interaction takes place between the teams. Initially an agreement about layout design rules allows the circuit 24 SIMULATION OF SEMICONDUCTOR LITHOGRAPHY AND TOPOGRAPHY - ARN 3/3/06

8 Role of Modeling and Simulation design and process development to begin in parallel. Not all issues can be envisioned in advance so negotiations on design rule changes are made periodically. FIGURE 1.5 Time scale and activities typically required in cooperation between product circuit designers, process technologists and manufacturing engineers in producing a new microprocessor [rzz.hatz.time]. The really expensive and risky part is moving into production. Major equipment purchases have been made and the price of sitting idle one day is in the millions of dollars. Yet typically several tape-outs of masks are required to get the process going. Engineers must deliver on commitments to produce even though not every structure used by circuit designers has been tested and many hidden gotchas come up. The equipment is being modified by the vendor at the last minute in hopes of addressing problems noted on a conditional sign-off from process development. Simply moving a existing product from an old facility to a new and more capable one still requires circuit layout changes to get the timing correct. For complex designs such as microprocessors these layout changes can take longer than the time it takes to physically construct the fabrication facility. One of the goals of the IC industry is to reduce this product design cycle to about one year and to be able to move an existing product to a new fabrication facility in a few months. Concurrent engineering and re-engineering of circuit design, process development and manufacturing is envisioned. This activity will require new information systems to coordinate activities and more flexible layout descriptions such as flexible design rules to facilitate more dynamical changes in the design. 1.2 Role of Modeling and Simulation Modeling and simulation have made significant contributions to the development of unit process steps, to the integration of sequential process steps and to providing a characterization foundation manufacturing. Simulation is a cost effective means of under- 3/3/06 SIMULATION OF SEMICONDUCTOR LITHOGRAPHY AND TOPOGRAPHY - ARN 25

9 Introduction standing physical aspects of a processes step, the complexity of interstep process interactions, and the statistical nature of manufacturing. Modeling and simulation of semiconductor topography and inspection are especially useful in coping with the complexity associated with emerging technology issues. A given process step such as lithography may depend upon up to 25 parameters which describe the equipment used to perform the step, the characteristics of the materials being modified at that step, and the condition of the underlying films and wafer going into the step. The consequences in the integrating the process flow must be considered once the individual process steps have been characterized. Understanding the effects say 25 parameters for each of over 100 process steps and 20 mask levels is almost beyond human comprehension. A third important challenge is to understand the fabrication process from the manufacturing point of view to include the statistical variations in materials and tool performance. Here TCAD tools may play a major role in providing and efficient physically based structure to assist in unbundling statistical variations to identify likely causes Examples of Uses in Unit Process Development Historically, most of the TCAD development has been at the unit process level in developing particular models and simulators sometimes referred to as point solution approaches. These simulators are used for education, identifying the phenomena dominating a process step, determining optimum process conditions, and exploring hypothetical impacts of improvements in materials and equipment. Part of this unit process simulation thrust is to carry out characterization experiments and computerized instrumentation and data analysis to establish quantitative physical models. An example of rigorously simulating the time-evolution of a critical device feature in lithography unit process in semiconductor fabrication is shown in Figure 1.6 where the SEM and simulated result for the profile of a submicron resist feature are given [rzz:ahlquist.1980]. Here optical projection printing with a 1978 technology has produced a very impressive 0.3 μm resist feature which is not much wider than two of the 130 nm interference fringes. The manufacturability of this feature is quite another matter. As shown in the simulation a little defocus badly degrades this particular result which was achieved by over-exposure and over-development of a much larger 1.0 μm feature. A practical process must be sufficiently robust to withstand normal variations in every conceivable parameter of the resist process, exposure tool and wafer condition. Simulation can help systematically examine key concerns in technology and help convert the art of process technology into a quantitative design science Process Integration Chaining together simulators with process flow and layout is also available and in use. These process flow simulators allow interaction effects which propagate from one process step to another to be assessed and worst case process flow scenarios to be analyzed. To meet the challenge of design and control for manufacturability, information systems and on-line monitoring/control are providing a foundation for characterizing the statistical nature of manufacturing. Flexible design rules are envisioned as a means of dynamically improving the design. TCAD will hopefully help interpret monitor data, provide a structure for control concepts and design trade-off studies, as well as augment empirical tech- 26 SIMULATION OF SEMICONDUCTOR LITHOGRAPHY AND TOPOGRAPHY - ARN 3/3/06

10 Role of Modeling and Simulation niques such as the Design of Experiments (DOE) to provide a more efficient and powerful approach. (a) SEM Profile (b) SIM Profile FIGURE 1.6 Resist profile of a 0.3 μm line from a 1.0 μm mask produced by over exposure and over development (a) SEM and (b) simulation showing extreme sensitivity to defocus [rzz.ahlquist.80]. A second modeling and simulation example which emphasizes the process integration aspects of process simulation is that for a CMOS device and mechanical structure for a microelectromechanical (MEM) process [rzz.analog] shown in Figure CP.16 and Figure CP.17 respectively. Here the complete formation of the topographical features on the wafer has been simulated from combining the layout with the complete process sequence of lithography, etching and deposition steps. Process integration requires that the device structure be properly formed even when process parameters are at their specification limits and masks have worst case alignment allowed by design rules. Through simulation an overview of the formation of device features throughout the entire fabrication under worst case scenarios can be synthesized. For example, Figure CP.17 shows the possibility of polysilicon stringers between fingers in the MEM structure due to poor oxide step coverage and the tendency of polysilicon to fill any remaining trenches Growing Opportunities for Modeling and Simulation It is difficulty to generate the physical models, algorithms and user interfaces to support IC process technology. In the 1980 s when simulation had yet to establish a firm base several slogans were developed which reflect this difficulty. In our research group at Berkeley in we had a sign which read [rzz.addiego.nand] Those who can do, and those who can t simulate. 3/3/06 SIMULATION OF SEMICONDUCTOR LITHOGRAPHY AND TOPOGRAPHY - ARN 27

11 Introduction At Stanford there was a similar slogan [rzz.law.sologan] Yesterday s technology simulated tomorrow While experimental characterization is essential it is unfortunately being impacted today due to increased cost per experiment, short equipment lead times, and the factorial increase in combinations of parameters which must be considered. In fact, due to the increase in experimental costs technologists are often asked to simulate their experiments first to justify the need to purchase experimental equipment. So today one of these signs might read Those who can do, and those who can t simulate aren t as effective. A simple argument could be made using cost trends that today simulation should almost be free compared to experiment. This is due to the dramatic drop in the cost of CPU cycles compared to the rise in equipment prices. CPU cycles are now 100,000 times cheaper than they were just 15 years ago. A PC is 10 to 100 times faster than the early mainframes and can be outright purchased for a few hours of early mainframe CPU time. Equipment costs, on the other hand, have risen about a factor of 20 in the same time period. Taken together the same simulation is now over one million time more cost effective than it was initially. Clearly the improvement in the leverage of simulation relative to experiment is offset somewhat by the fact that in pushing the limits of the technology today many more complex physical phenomena must be simulated. The real gating factor is, however, the investment of resources in establishing the physical models, algorithms and applications interfaces. A sufficient investment should be made to grow the TCAD capability along with the technology itself. While occasionally top down investments are made, most of the growth of TCAD has been through the return on investment it provides in helping technologists address specific problems with purpose built simulators. This has been successful across a broad front of processes and the hope of simulator developers is that before too long a critical mass will be reached where investments in integration into comprehensive process flow and manufacturing simulation systems will be cost effective Basic Ingredients and Uses of Process Simulators In developing simulators the models and algorithms are the key ingredients. It has been possible to find both physical models and efficient algorithms to simulate most of the individual processes and phenomena used in the fabrication and operation of integrated circuits. The modeling begins with experimental investigations of the physical mechanism and important variables in the process to establish a basic model. Careful parametric studies must then be carried out to provide quantitative parameters for the range of operating conditions of interest in application of the simulator. At the practical level simulation 28 SIMULATION OF SEMICONDUCTOR LITHOGRAPHY AND TOPOGRAPHY - ARN 3/3/06

12 Evolution of Process Simulation emphasizes the need to partition the characterization process and to identify key models for physical and chemical processes. These modeling activities are the bottleneck and are usually more time consuming than programming. The programming includes developing an algorithm which is CPU and memory efficient and yet accurate. The program must also be made user friendly and machine portable. Once the device structure has been defined the electrical performance can then be determined through the use of device simulation programs. The simulator developer must also have a clear description of the manner in which the simulator is to be used as there are trade-offs in configuring the system. The models and simulators can form an educational base. The use of key parameters in the models suggest basic trends which can be used for diagnostic purposes. The sensitivity to all parameters gives an idea of process latitude. Systematic design centering and be carried out with a complete set of quantitative models and associated algorithms. Simulation capabilities for sequential steps allow interactions between process steps to be explored. A base of such models allows entirely new process sequences to be explored. With simulation many technology trends can be extrapolated in hypothetical assessment studies in advance of the delay and expense of developing new materials and equipment. 1.3 Evolution of Process Simulation Functional Grouping of Simulators In addressing process technology issues CAD tools for layout, circuit design, process and device must work together. Figure 1.7 shows these functional categories and gives examples of well known simulators in each. Looking at process issues requires layout data which can then be combined with process flow to examine cross sections. Lithography, topography and impurity related processes may need to be examined rigorously by additional simulators. These examples highlight CAD tools from universities and research organizations and parallel industrial grade tools are generally available from vendors. Frameworks for sharing data between modular simulators can help facilitate these detailed studies. The device geometry and impurity information is then passed on to electrical device analysis be it MOS, bipolar or parasitic capacitance. The data for individual devices and parasitics eventually must link up with circuit simulation. The individual unit processes simulators used in the fabrication of integrated circuits can be roughly grouped into the four application areas of lithography, etching, deposition and thermal processing shown in Figure 1.8. Lithography which is the process of writing a pattern on the wafer might be accomplished by means of parallel or serial exposure by beams of photons (optical or x-ray) or particles (electrons and ions). Typically a radiation sensitive material called a resist is coated on the wafer to record the pattern and resist the etchant used to transfer the pattern to the films on the wafer. Etching with chemicals or plasma excited gases can be used to transfer the pattern. Materials such as polysilicon, metals and dielectrics are deposited on the wafer by either blanket or selective techniques. Thermal processing includes oxidation of silicon to form silicon dioxide, implantation of dopants by ion bombardment, and diffusion of dopants. Lithography, etching and deposition are primarily responsible for the topographical features of the circuit above the silicon surface. These topography forming processes are the focus of this monograph. Thermal 3/3/06 SIMULATION OF SEMICONDUCTOR LITHOGRAPHY AND TOPOGRAPHY - ARN 29

13 Introduction FIGURE 1.7 Functional categories of CAD tools and examples of simulators. processing primarily deals with changes below the silicon surface in the impurity distribution or oxide. More details on these individual process technologies can be found in text such as that of Jaeger [Jaeger], Sze [rzz SZE.tech], Brodie [Brodie] and Wolf and Tauber [rzz.wolftauber] Emergence of Topography Simulators A considerable repertoire of process topography simulation programs has been developed for semiconductor devices. Figure 1.9 andfigure 1.10 of 2D and 3D simulators were compiled recently by Ed Scheckler [rzz:scheckler.phd]. The data on 2D simulators while only a sampling shows maximum growth about 1985 and the emergence of commercial simulators about that time. A total of 17 3D simulators were described in the literature by 1991 and commercial 3D simulators are already available. There is also work on framework standards for representing device geometry and impurity distributions called Semiconductor Wafer Representation (SWR) {PIF, SWR} and process flow called semiconductor process Representation (SPR) [rzz.spr] so that physical simulators can be invoked in a modular manner. As the TCAD field matures it is beginning to move toward common environments for unit process simulators to share common centralized utilities and to take advantage of specialization such as in areas of algorithms from computational geometry [rzz:swr.nupadiv]. 30 SIMULATION OF SEMICONDUCTOR LITHOGRAPHY AND TOPOGRAPHY - ARN 3/3/06

14 Evolution of Process Simulation FIGURE 1.8 Grouping of fabrication processes into four major application areas. Topography simulation in which the time-evolution of the device structure is modeled includes primarily lithography, etching and deposition Brief History of Topography and Lithography Simulators The equations used to describe phenomena in classical physics are the foundation of almost all models used for simulation. For this reason many of the concepts can be found in standard texts from physics and Electrical Engineering. Optical lithography draws on near field diffraction, and standingwave effects found in texts [Jenkins and White, RWV] as well as advanced imaging theory and algorithms for multilayer films found in advanced books and monographs [Born and Wolf, Berning]. Election beam lithography is based on models for electron optics and interaction of electrons with materials [refeb]. Gas phase reactions, plasmas and the kinetic theory of gases are essential to deposition and etching [CALE?, Lieberman, KTGtext]. The fact that a simulator is expected to produce a result means that the developer must integrate together a series of models which capture the complete nature of the materials, equipment, and wafer state under the process conditions used by the technologist. Developing simulators thus requires a multifaceted effort to establish models, quantitative parameters, algorithms and user interfaces. An early example of this multifaceted thrust is the case of the modeling optical projection printing organized by Rick Dill in support of IBM s transition from contact to projection printing[rzz.dill.1975]. A key breakthrough was the recognition that positive resist dissolution could be modeled as surface etching and the commitment to establishing both the instrumentation and the data analysis capability to determine and quantify the underlying models. A similar development was made in IBM for simulating electron beam lithography in support of direct write to reduce mask costs for chips with low part counts [rzz.kyser.pyle]. Deposition in IC production equipment was first modeled by a group in AT&T based on a systematic characterization of the tool geometry, emulation of the Al deposition and comparison of orientation dependent results with SEM s profiles [rzz.blech]. The local morphology of deposited films was 3/3/06 SIMULATION OF SEMICONDUCTOR LITHOGRAPHY AND TOPOGRAPHY - ARN 31

15 Introduction FIGURE 1.9 Survey of 2D topography simulation programs [after rzz.scheckler.phd]. FIGURE 1.10 Survey of 3D topography simulation programs [after rzz.scheckler.phd]. 32 SIMULATION OF SEMICONDUCTOR LITHOGRAPHY AND TOPOGRAPHY - ARN 3/3/06

16 Organization and Viewpoint of this Monograph undertaken more recently with a careful comparison of simulation and SEM profiles of columnar structure [rzz.brett.tait]. The simulation of plasma etching proved to be much more difficult do to the necessity of modeling the plasma, surface reactions and profile evolution and early work had only limited success [Reynolds, Viswathanathan, Others]. The roots of modeling plasma etching are in simulating ion milling [Doucomon and Chambers Univ] and crystal etching and slowness factors introduced by Frank [Frank]. Only today are the more formidable aspects being adequately addressed [McVittie, Cale, Others]. An important growth in the associated algorithms for topography and lithography simulation has also occurred. A methodology for tracking vertices with arbitrary etch rate versus angle was developed by C.H. Sequin [rzz.sequin.sa]. The ability to efficiently represent, advance, and regularize collisions and meshing of 3D device topography with surface facets has been implemented [rzz.toh, rzz.scheckler, rzz.helmsen, rzz.sefler]. A fundamentally new level-set contour approach has been invented in which the shocks and fans which plague surface advance implementations do not need special attention [rzz.sethian]. Advances in time-domain [rzz.wojick, rzz.guerrreri] and fast multipole frequency domain electromagnetic analysis techniques [rzz.rocklin, rzz.yeung] have also been made which are applicable to process TCAD. In the area of optical proximity corrections very rapid methods for large are masks have been developed using singular-value decomposition techniques [rzz.wolf, rzz.pati, rzz.cobb]. There is a rich literature on modeling and simulation of topography in integrated circuits. In addition to the texts mentioned earlier books on more advance aspects such as optical lithography [SPIE], electron-beam lithography [Brewer], and resist materials [TWB and Dammel]. A number of book chapters on specific technology also include concepts useful to modeling such as those on lithography by King, Lin, Mack, Others[ref]. Easily over one thousand papers relevant to modeling and simulation of topography have been published since the mid 1970 s and most of this dialog has appeared in the SPIE Proceedings, the Journal of Vacuum Science and Technology, and IEEE transactions on Electron Devices and Computer Aided Design. The synergistic relationship between impurity and topography simulation and the developments in TCAD environments can be found in several books [TUVws, TUV conf, Dutton]. 1.4 Organization and Viewpoint of this Monograph The material in this monograph has been selected and presented from the point of view of supporting the process engineer known as the technologist. The ultimate consumer of TCAD is the technologist who has to develop a fabrication capability on schedule and sustain with minimal resources. In so doing the technologists must quickly penetrate to the essence of the physics and chemistry which dominate in the process. This pushes the frontiers of knowledge and raises many fundamental and stimulating questions. Much of the material in this monograph has in fact been developed by researchers and modelers attempting to answer these questions through engineering characterization and simulation. Since the physical models and associated phenomena are of interest to the technologists this monograph is in most cases organized around the models for the process physics. Hopefully, the technologists will find that the models provide both insight for new tech- 3/3/06 SIMULATION OF SEMICONDUCTOR LITHOGRAPHY AND TOPOGRAPHY - ARN 33

17 Introduction nology directions and an efficient foundation for characterization. The models should also give students who are new to the field a set of stepping stones for rapidly coming up to speed. For the simulation system and computational geometry specialists the models hopefully define the nature and complexity of the problem so that they can quickly identify where they can make a contribution. In some topical areas especially in the later chapters this monograph also emphasizes the algorithms and simulator environments which are of interest to those developing TCAD systems. In putting together the highlights of this work it became clear that there is a lack of an intermediate level reference on which to launch into a discussion of the advanced research results. For this reason in a special effort is made in the initial chapters to describe important physical phenomena and their impacts without going through the usual rigorous derivations. Some of this rigor is added later with the advanced models albeit it is limited by the length requirements of the monograph. This monograph is somewhere between a class room text and a compendium on simulation research. The initial seven chapters are suitable for use either in the class room or as a reference text in an undergraduate or graduate course on process technology. For example, the modeling material complements that found in text books such as those of Jaeger, Sze and Wolf and Tauber. This basic modeling discussion is also well suited for hands on use with simulators. Chapter 1 and 2 give an overview of IC fabrication technology and process flow integration. Deposition and etching and their characterization are considered in Chapters 3 and 4. Optical lithography and its characterization are covered in Chapter 5 and 6. Chapter 7 does likewise for electron-beam and x-ray lithography. The second half of this monograph is more research oriented. Chapters 8-11 take a more in-depth look an advanced phenomena in optics, resist materials, and electromagnetic scattering from topography as well as 3D topography simulation. Chapter 12 emphasizes a new simulation community paradigm in which a top down organizational approach of process simulation allows computation and simulation system specialists to contribute their services. Chapter 13 provides a closing perspective on future directions and opportunities in topography simulation References 34 SIMULATION OF SEMICONDUCTOR LITHOGRAPHY AND TOPOGRAPHY - ARN 3/3/06