IRLR8503 IRLR8503 PD-93839C. HEXFET MOSFET for DC-DC Converters Absolute Maximum Ratings. Thermal Resistance Parameter

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1 PD-93839C N-Channel Application-Specific MOSFET Ideal for CPU Core DC-DC Converters Low Conduction es Minimizes Parallel MOSFETs for high current applications 100% R G Tested HEXFET MOSFET for DC-DC Converters D Description This new device employs advanced HEXFET Power MOSFET technology to achieve very low on-resistance. The reduced conduction losses makes it ideal for high efficiency DC-DC converters that power the latest generation of microprocessors. G S D-Pak The has been optimized and is 100% tested for all parameters that are critical in synchronous buck converters including R DS(on), gate charge and Cdv/dtinduced turn-on immunity. The offers an extremely low combination of Q sw & R DS(on) for reduced losses in control FET applications. The package is designed for vapor phase, infra-red, convection, or wave soldering techniques. Power dissipation of greater than W is possible in a typical PCB mount application. DEVICE RATINGS (MAX. Values) V DS R DS(on) Q G Q SW Q OSS 30V 18 mω 0 nc 8 nc 9.5 nc Absolute Maximum Ratings Parameter Drain-Source Voltage Gate-Source Voltage T C = 5 C Continuous Drain or Source Current T C = 90 C Pulsed Drain Current c T C = 5 C Power Dissipation g T C = 90 C Junction & Storage Temperature Range Continuous Source Current (Body Diode) Pulsed Source Current c Thermal Resistance Parameter Maximum Junction-to-Ambient eh Maximum Junction-to-Lead h Symbol Units V DS V GS I D I DM P D 6 W 30 T J, T STG -55 to 150 C I S I SM 30 V ± A A 196 Symbol Typ Max Units R θja 50 C/W R θjl /6/05

2 Electrical Characteristics Parameter Symbol Min Typ Max Units Drain-to-Source Breadown Voltage* V (BR)DSS 30 V V GS = 0V, I D = 50µA Static Drain-Source On-Resistance* R DS(on) mω Gate Threshold Voltage* V GS(th) V V DS = V GS, I D = 50µA Drain-Source Leakage Current I DSS 1.0 V DS = 30V, V GS = 0 µa 150 V DS = 4V, V GS = 0, T J = 100 C Gate-Source Leakage Current* I GSS ±100 na V GS = ± 0V Total Gate Charge, Control FET* Q g 15 0 V GS = 5V, I D = 15A, V DS = 16V Total Gate Charge, Synch FET* Q g V GS = 5V, V DS < 100mV Pre-Vth Gate-to-Source Charge Q gs1 3.7 nc Post-Vth Gate-to-Source Charge Q gs 1.3 V DS = 16V, I D = 15A Gate-to-Drain Charge Q gd 4.1 Switch Charge* (Q gs + Q gd ) Q SW Output Charge* Q OSS V DS = 16V, V GS = 0 Gate Resistance R G Ω Turn-On Delay Time t d(on) 10 V DD = 16V, I D = 15A Drain Voltage Rise Time tr V 18 V GS = 5.0V ns Turn-Off Delay Time t d(off) 11 Clamped Inductive Load Drain Voltage Fall Time tf V 3 See Test Diagram Fig. 14 Input Capacitance C iss 1650 V DS = 5V Output Capacitance C oss 650 pf V GS = 0 Reverse Transfer Capacitance C rss 58 Source-Drain Rating & Characteristics Parameter Symbol Min Typ Max Units Conditions Diode Forward Voltage* V SD 1.0 V I S = 15Ad, V GS = 0V Reverse Recovery Charge f Q rr Reverse Recovery Charge (with Parallel Schottsky) f Q rr(s) 67 Notes: Repetitive rating; pulse width limited by max. junction temperature. Pulse width 300 µs; duty cycle %. ƒ When mounted on 1 inch square copper board, t < 10 sec. Typ = measured - Q oss 76 nc di/dt = 700A/µs V DD = 16V, V GS = 0V, I S = 15A di/dt = 700A/µs (with 10BQ040) Conditions V GS = 10V, I D = 15A d V GS = 4.5V, 1 D = 15A V DD = 16V, V GS = 0V, I S = 15A Calculated continuous current based on maximum allowable Junction temperature; switching and other losses will decrease RMS current capability; package limitation current = 0A. R θ is measured at T J approximately at 90 C *Devices are 100% tested to these parameters.

3 Power MOSFET Optimization for DC-DC Converters While the IRLR8103V and can and are being used in a variety of applications, they were designed and optimized for low voltage DC-DC conversion in a synchronous buck converter topology, specifically, microprocessor power applications. The (Figure 1) was optimized for the control FET socket, while the IRLR8103V was optimized for the synchronous FET function. (Cont FET) IRLR8103V (Sync FET) Figure 1 Application Topology CGD CGS CDS Figure Inter-electrode Capacitance Because of the inter-electrode capacitance (Figure ) of the Power MOSFET, specifying the R DSON of the device is not enough to ensure good performance. An optimization between R DSON and charge must be performed to insure the best performing MOSFET for a given application. Both die size and device architecture must be varied to achieve the minimum possible in-circuit losses. This is independently true for both control FET and synchronous FET. Unfortunately, the capacitances of a FET are non-linear and voltage dependent. Therefore, it is inconvenient to specify and use them effectively in switching power supply power loss estimations. This was well understood years ago and resulted in changing the emphasis from capacitance to gate charge on Power MOSFET data sheets. VGTH Table New Charge Parameters New Charge Parameter Description Waveform Q GS1 Pre-Threshold Gate Charge Q GS Post-Threshold Gate Charge Figure 3 Q GCONT Control FET Total Q G Q SWITCH Charge during control FET switching Combines Q GS and Q GD Q OSS Output charge Figure 5 Charge supplied to C OSS during the Q GD Figure 6 period of control FET switching Q GSYNC Synchronous FET Total Q G (V DS 0) Figure 4 QGS1 QGS Figure 3 Control FET Waveform Figure 4 Sync FET Waveform The waveforms are broken into segments corresponding to charge parameters. These, in turn, correspond to discrete time segments of the switching waveform. g1 g QG (Control FET) QSwitch QGD Drain Voltage VIN Gate Voltage Drain Current N1 Cont FET N Sync FET Coss1 n SN Coss n 0 V Dead Time Gate Voltage VGTH Drain Voltage QG (Sync FET) 0 A Body Diode Current Drain Current Switch node voltage (VSN) N1 Gate Voltage N1 Current N1 Coss Discharge + N Coss Charge Table 1 Traditional Charge Parameters Device Capacitance Corresponding Charge Parameter Figure 5 Q OSS Equivalent Circuit Figure 6 Q OSS Waveforms C GS C GS + C GD C GD Q GS Q G Q GD International Rectifier has recently taken the industry a step further by specifying new charge parameters that are even more specific to DC-DC converter design (Table ). In order to understand these parameters, it is best to start with the in-circuit waveforms in Figure 3 & Figure 4. es may be broken into four categories: conduction loss, gate drive loss, switching loss, and output loss. The following simplified power loss equation is true for both MOSFETs in a synchronous buck converter: P LOSS = P CONDUCTION + P GATE DRIVE + P SWITCH + P OUTPUT For the synchronous FET, the P SWITCH term becomes virtually zero and is ignored. 3

4 Table 3 and Table 4 describes the event during the various charge segments and shows an approximation of losses during that period. Table 3 Control FET es Conduction Gate Drive Switching Output Conduction Gate Drive Switching Output Description es associated with MOSFET on time. I RMS is a function of load current and duty cycle. es associated with charging and discharging the gate of the MOSFET every cycle. Use the control FET Q G. es during the drain voltage and drain current transitions for every full cycle. es occur during the Q GS and Q GD time period and can be simplified by using Q switch. es associated with the Q OSS of the device every cycle when the control FET turns on. es are caused by both FETs, but are dissipated by the control FET. Table 4 Synchronous FET es Description es associated with MOSFET on time. I RMS is a function of load current and duty cycle. es associated with charging and discharging the gate of the MOSFET every cycle. Use the Sync FET Q G. Generally small enough to ignore except at light loads when the current reverses in the output inductor. Under these conditions various light load power saving techniques are employed by the control IC to maintain switching losses to a negligible level. es associated with the Q OSS of the device every cycle when the control FET turns on. They are caused by the synchronous FET, but are dissipated in the control FET. COND Segment es RMS P = I R P = V Q ƒ IN G G QGD SWITCH V V IN V I I IN L Q I Q I G DS (on) GS PQGS IN L G P P GD Q IL I SW G ƒ ƒ ƒ QOSS POUTPUT = VIN F COND Segment es RMS P = I R P = V Q ƒ IN G G P SWITCH 0 P OUTPUT DSon QOSS = V ƒ IN Typical PC Application The IRLR8103V and the are suitable for Synchronous Buck DC-DC Converters, and are optimized for use in next generation CPU applications. The IRLR8103V is primarily optimized for use as the low side synchronous FET (Q) with low R DS(on) and high CdV/dt immunity.the is primarily optimized for use as the high side control FET (Q) with low cobmined Qsw and R DS(on), but can also be used as a synchronous FET. The is also tested for Cdv/dt immunity, critical for the low side socket. The typical configuration in which these devices may be used in shown in Figure 7. Control FET (Q1) 1 x IRLR8103 Vor or x Synchronous FET (Q) Figure 7. & 3-FET solution for Synchronous Buck Topology. 4

5 I D, Drain-to-Source Current (Α) R DS(on), Drain-to -Source On Resistance (Ω) R DS(on), Drain-to-Source On Resistance (Normalized) V GS, Gate-to-Source Voltage (V).5 I D = 15A V GS = 4.5V Typical Characteristics 6.0 I D = 15A V DS = 0V T J, Junction Temperature ( C ) Q G, Total Gate Charge (nc) Figure 8. Normalized On-Resistance vs. Temperature Figure 9. Gate-to-Source Voltage vs. Typical Gate Charge VGS = 0V, f = 1MHz Ciss = Cgs + Cgd, C ds SHORTED Crss = Cgd Coss = Cds + Cgd I D = 15A C, Capacitance (pf) C iss C oss V GS, Gate -to -Source Voltage (V) Figure 10. Typical Rds(on) vs. Gate-to-Source Voltage C rss V DS, Drain-to-Source Voltage (V) Figure 11. Typical Capacitance vs. Drain-to-Source Voltage T J = 150 C 10.0 T J = 5 C V DS = 15V 0µs PULSE WIDTH V GS, Gate-to-Source Voltage (V) Figure 1. Typical Transfer Characteristics 5

6 10 Thermal Response (Z thjc ) D = SINGLE PULSE (THERMAL RESPONSE) Notes: 1. Duty factor D = t 1 / t. Peak T J= P DMx Z thjc + TC t 1, Rectangular Pulse Duration (sec) PDM t1 t Figure 13. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient Inductive Load Circuit Figure 15. Switching waveform Figure 14. Clamped Inductive Load test diagram 6

7 D-Pak (TO-5AA) Package Outline Dimensions are shown in millimeters (inches) 5.46 (.15) 5.1 (.05) 6.73 (.65) 6.35 (.50) - A (.050) 0.88 (.035).38 (.094).19 (.086) 1.14 (.045) 0.89 (.035) 0.58 (.03) 0.46 (.018) (.040) 1.64 (.05) 1.5 (.060) 1.15 (.045) X 1.14 (.045) 0.76 (.030) 1 3 3X 6. (.45) 5.97 (.35) - B (.035) 0.64 (.05) 0.5 (.010) M A M B 10.4 (.410) 9.40 (.370) 6.45 (.45) 5.68 (.4) 0.51 (.00) MIN (.03) 0.46 (.018) LEAD ASSIGNMENTS 1 - GATE - DRAIN 3 - SOURCE 4 - DRAIN.8 (.090) 4.57 (.180) NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 198. CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-5AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX (.006). D-Pak (TO-5AA) Part Marking Information EXAMPLE: THIS IS AN IRFR10 WITH ASSEMBLY LOT CODE 134 ASSEMBLED ON WW 16, 1999 IN THE ASSEMBLY LINE "A" Note: "P" in assembly line position indicates "Lead-Free" INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE IRFR10 916A 1 34 PART NUMBER DATE CODE YEAR 9 = 1999 WEEK 16 LINE A OR INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE IRFR10 P916A 1 34 PART NUMBER DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 9 = 1999 WEEK 16 A = AS S E MBLY S IT E CODE 7

8 Tape & Reel Information TO-5AA TR TRR TRL 16.3 (.641 ) 15.7 (.619 ) 16.3 (.641 ) 15.7 (.619 ) 1.1 (.476 ) 11.9 (.469 ) FEED DIRECTION 8.1 (.318 ) 7.9 (.31 ) FEED DIRECTION NOTES : 1. CONTROLLING DIMENSION : MILLIMETER.. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA INCH NOTES : 1. OUTLINE CONFORMS TO EIA mm Data and specifications subject to change without notice. This product has been designed and qualified for the commercial market. Qualification Standards can be found on IR s Web site. 8 IR WORLD HEADQUARTERS: 33 Kansas St., El Segundo, California 9045, USA Tel: (310) TAC Fax: (310) Visit us at for sales contact information. 5/05

9 Note: For the most current drawings please refer to the IR website at: