AUTOMOTIVE MOSFET. A I T C = 25 C Continuous Drain Current, V 10V (Package Limited)

Transcription

1 PD AUTOMOTIVE MOSFET Features llogic Level ladvanced Process Technology lultra Low On-Resistance l175 C Operating Temperature lfast Switching lrepetitive Avalanche Allowed up to Tjmax Description Specifically designed for Automotive applications, this HEXFET Power MOSFET utilizes the latest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this design are a 175 C junction operating temperature, fast switching speed and improved repetitive avalanche rating. These features combine to make this design an extremely efficient and reliable device for use in Automotive applications and a wide variety of other applications. Absolute Maximum Ratings Parameter I T C = 25 C Continuous Drain Current, V 1V (Silicon Limited) HEXFET Power MOSFET V DSS = 55V R DS(on) = 8.mΩ I D = 42A HEXFET is a registered trademark of International Rectifier. 1 G D S D-Pak IRLR375Z IRLR375Z IRLU375Z I-Pak IRLU375Z Units I T C = C Continuous Drain Current, V 1V 63 A I T C = 25 C Continuous Drain Current, V 1V (Package Limited) 42 I DM Pulsed Drain Current c 36 P C = 25 C Power Dissipation 13 W Linear Derating Factor.88 W/ C V GS Gate-to-Source Voltage ± 16 V E AS (Thermally limited) Single Pulse Avalanche Energyd 11 mj E AS (Tested ) Single Pulse Avalanche Energy Tested Value h 19 I AR Avalanche Currentc See Fig.12a, 12b, 15, 16 A E AR Repetitive Avalanche Energy g mj T J Operating Junction and -55 to T STG Storage Temperature Range C Soldering Temperature, for 1 seconds 3 (1.6mm from case ) 1 lbfyin (1.1Nym) Mounting Torque, 6-32 or M3 screw Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case j 1.14 R θja Junction-to-Ambient (PCB mount) ij 4 C/W R θja Junction-to-Ambient j 11 Max. 89 9/29/4

2 IRLR/U375Z Electrical T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 55 V V GS = V, I D = 25µA V (BR)DSS / T J Breakdown Voltage Temp. Coefficient.53 V/ C Reference to 25 C, I D = 1mA R DS(on) Static Drain-to-Source On-Resistance mω V GS = 1V, I D = 42A e 11 V GS = 5.V, I D = 34A e 12 V GS = 4.5V, I D = 21A e V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 25µA gfs Forward Transconductance 89 S V DS = 25V, I D = 42A I DSS Drain-to-Source Leakage Current 2 µa V DS = 55V, V GS = V 25 V DS = 55V, V GS = V, T J = 125 C I GSS Gate-to-Source Forward Leakage 2 na V GS = 16V Gate-to-Source Reverse Leakage -2 V GS = -16V Q g Total Gate Charge I D = 42A Q gs Gate-to-Source Charge 13 nc V DS = 44V Q gd Gate-to-Drain ("Miller") Charge 22 V GS = 5.V e t d(on) Turn-On Delay Time 17 V DD = 28V t r Rise Time 15 I D = 42A t d(off) Turn-Off Delay Time 33 ns R G = 4.2 Ω t f Fall Time 7 V GS = 5.V e L D Internal Drain Inductance 4.5 Between lead, D nh 6mm (.25in.) G L S Internal Source Inductance 7.5 from package S and center of die contact C iss Input Capacitance 29 V GS = V C oss Output Capacitance 42 V DS = 25V C rss Reverse Transfer Capacitance 23 pf ƒ = 1.MHz C oss Output Capacitance 155 V GS = V, V DS = 1.V, ƒ = 1.MHz C oss Output Capacitance 32 V GS = V, V DS = 44V, ƒ = 1.MHz C oss eff. Effective Output Capacitance 5 V GS = V, V DS = V to 44V f Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions I S Continuous Source Current 42 MOSFET symbol (Body Diode) A showing the I SM Pulsed Source Current 36 integral reverse (Body Diode)Ãc V SD Diode Forward Voltage 1.3 V t rr Reverse Recovery Time ns Q rr Reverse Recovery Charge nc p-n junction diode. T J = 25 C, I S = 42A, V GS = V e T J = 25 C, I F = 42A, V DD = 28V di/dt = A/µs e t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) 2

3 I D, Drain-to-Source Current (Α) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) IRLR/U375Z VGS TOP 12V 1V 8.V 5.V 4.5V 3.5V 3.V BOTTOM 2.8V VGS TOP 12V 1V 8.V 5.V 4.5V 3.5V 3.V BOTTOM 2.8V 2.8V 1 2.8V 1 6µs PULSE WIDTH Tj = 25 C V DS, Drain-to-Source Voltage (V) 1 6µs PULSE WIDTH Tj = 175 C V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics. T J = 25 C T J = 175 C. 1. V DS = 15V 6µs PULSE WIDTH V GS, Gate-to-Source Voltage (V) Gfs, Forward Transconductance (S) T J = 25 C T J = 175 C V DS = 8.V 38µs PULSE WIDTH I D, Drain-to-Source Current (A) Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance vs. Drain Current 3

4 I D, Drain-to-Source Current (A) C, Capacitance (pf) V GS, Gate-to-Source Voltage (V) IRLR/U375Z V GS = V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd Ciss I D = 42A V DS = 44V VDS= 28V VDS= 11V Coss 2 Crss 1 1 V DS, Drain-to-Source Voltage (V) Q G Total Gate Charge (nc) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage. OPERATION IN THIS AREA LIMITED BY R DS (on) I SD, Reverse Drain Current (A). T J = 175 C 1. T J = 25 C 1. V GS = V V SD, Source-to-Drain Voltage (V) Tc = 25 C Tj = 175 C Single Pulse 1msec 1msec µsec DC 1 1 V DS, Drain-toSource Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4

5 I D, Drain Current (A) R DS(on), Drain-to-Source On Resistance (Normalized) IRLR/U375Z 8 LIMITED BY PACKAGE I D = 42A V GS = 1V T C, Case Temperature ( C) T J, Junction Temperature ( C) Fig 9. Maximum Drain Current vs. Case Temperature Fig 1. Normalized On-Resistance vs. Temperature 1 1 D =.5 Thermal Response ( Z thjc ) SINGLE PULSE ( THERMAL RESPONSE ) R 1 R 2 R 1 R 2 τ J τ J τ 1 τ τ 2 1 τ 2 Ci= τi/ri Ci i/ri 1E-6 1E t 1, Rectangular Pulse Duration (sec) τ C τ Ri ( C/W) τi (sec) Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case 5

6 V GS (th) Gate threshold Voltage (V) E AS, Single Pulse Avalanche Energy (mj) IRLR/U375Z V DS L 15V DRIVER 5 4 I D TOP 5.3A 7.A BOTTOM 42A R G 2V V GS tp D.U.T IAS.1Ω + - V DD A 3 2 Fig 12a. Unclamped Inductive Test Circuit tp V (BR)DSS Starting T J, Junction Temperature ( C) I AS Fig 12b. Unclamped Inductive Waveforms Q G Fig 12c. Maximum Avalanche Energy vs. Drain Current 1 V Q GS Q GD 2.5 V G 2. I D = 25µA I D = 15µA I D = 5µA Charge Fig 13a. Basic Gate Charge Waveform K DUT L VCC T J, Temperature ( C ) Fig 13b. Gate Charge Test Circuit Fig 14. Threshold Voltage vs. Temperature 6

7 E AR, Avalanche Energy (mj) Avalanche Current (A) IRLR/U375Z Duty Cycle = Single Pulse Allowed avalanche Current vs avalanche pulsewidth, tav assuming Tj = 25 C due to avalanche losses. Note: In no case should Tj be allowed to exceed Tjmax E-6 1.E-5 1.E-4 1.E-3 1.E-2 1.E-1 tav (sec) Fig 15. Typical Avalanche Current vs.pulsewidth TOP Single Pulse BOTTOM 1% Duty Cycle I D = 42A Starting T J, Junction Temperature ( C) Notes on Repetitive Avalanche Curves, Figures 15, 16: (For further info, see AN-5 at 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long ast jmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 12a, 12b. 4. P D (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed T jmax (assumed as 25 C in Figure 15, 16). t av = Average time in avalanche. D = Duty cycle in avalanche = t av f Z thjc (D, t av ) = Transient thermal resistance, see figure 11) P D (ave) = 1/2 ( 1.3 BV I av ) = DT/ Z thjc Fig 16. Maximum Avalanche Energy I av = 2DT/ [1.3 BV Z th ] vs. Temperature E AS (AR) = P D (ave) t av 7

8 IRLR/U375Z + - D.U.T + ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - + Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =1V V DD * R G dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD + - Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET Power MOSFETs V DS R D R G V GS D.U.T. + - V DD 1V Pulse Width 1 µs Duty Factor.1 % Fig 18a. Switching Time Test Circuit V DS 9% 1% V GS t d(on) t r t d(off) t f Fig 18b. Switching Time Waveforms 8

9 IRLR/U375Z D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches) 5.46 (.215) 5.21 (.25) 6.73 (.265) 6.35 (.25) - A (.5).88 (.35) 2.38 (.94) 2.19 (.86) 1.14 (.45).89 (.35).58 (.23).46 (.18) (.4) 1.64 (.25) 1.52 (.6) 1.15 (.45) 2X 1.14 (.45).76 (.3) (.245) 5.97 (.235) - B -.89 (.35) 3X.64 (.25).25 (.1) M A M B 1.42 (.41) 9.4 (.37) 6.45 (.245) 5.68 (.224).51 (.2) MIN..58 (.23).46 (.18) LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN 2.28 (.9) 4.57 (.18) NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX (.6). D-Pak (TO-252AA) Part Marking Information EXAMPLE: THIS IS AN IRFR12 WITH ASSEMBLY LOT CODE 1234 ASSEMBLED ON WW 16, 1999 IN THE ASSEMBLY LINE "A" Note: "P" in assembly line position indicates "Lead-Free" INTERNATIONAL RECTIFIER LOGO AS S E MBL Y LOT CODE IRFR12 916A PART NUMBER DATE CODE YEAR 9 = 1999 WEEK 16 LINE A OR INTERNATIONAL RECTIFIER LOGO AS S E MBLY LOT CODE IRFR12 P916A PART NUMBER DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 9 = 1999 WEEK 16 A = AS S EMBLY S IT E CODE 9

10 IRLR/U375Z I-Pak (TO-251AA) Package Outline Dimensions are shown in millimeters (inches) 5.46 (.215) 5.21 (.25) 1.52 (.6) 1.15 (.45) 6.73 (.265) 6.35 (.25) - A (.245) 5.97 (.235) 1.27 (.5).88 (.35) 2.38 (.94) 2.19 (.86).58 (.23).46 (.18) 6.45 (.245) 5.68 (.224) LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN B (.9) 1.91 (.75) 9.65 (.38) 8.89 (.35) NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX (.6). 3X 1.14 (.45).76 (.3) 2.28 (.9) 2X 3X.89 (.35).64 (.25).25 (.1) M A M B 1.14 (.45).89 (.35).58 (.23).46 (.18) I-Pak (TO-251AA) Part Marking Information EXAMPLE: THIS IS AN IRFU12 WITH ASSEMBLY LOT CODE 5678 ASSEMBLED ON WW 19, 1999 IN THE ASSEMBLY LINE "A" Note: "P" in ass embly line position indicates "Lead-Free" INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE IRFU12 919A PART NUMBER DATE CODE YEAR 9 = 1999 WEEK 19 LINE A OR INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE IRFU PART NUMBER DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 9 = 1999 WEEK 19 A = AS S E MB LY S IT E CODE 1

11 IRLR/U375Z D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR TRL 16.3 (.641 ) 15.7 (.619 ) 16.3 (.641 ) 15.7 (.619 ) 12.1 (.476 ) 11.9 (.469 ) FEED DIRECTION 8.1 (.318 ) 7.9 (.312 ) FEED DIRECTION NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA INCH NOTES : 1. OUTLINE CONFORMS TO EIA mm Notes: Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11). Limited by T Jmax, starting T J = 25 C, L =.12mH R G = 25Ω, I AS = 42A, V GS =1V. Part not recommended for use above this value. ƒ Pulse width 1.ms; duty cycle 2%. C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from to 8% V DSS. Limited by T Jmax, see Fig.12a, 12b, 15, 16 for typical repetitive avalanche performance. This value determined from sample failure population. % tested to this value in production. When mounted on 1" square PCB (FR-4 or G-1 Material). For recommended footprint and soldering techniques refer to application note #AN-994 ˆ R θ is measured at T J approximately 9 C Data and specifications subject to change without notice. This product has been designed for the Automotive [Q11] market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 9245, USA Tel: (31) TAC Fax: (31) Visit us at for sales contact information.9/4 11

12 Note: For the most current drawings please refer to the IR website at: