Introduction. A digital circuit design is just an idea, perhaps drawn on paper We eventually need to implement the circuit on a physical device

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1 i Digitl Deign Chter : Phyicl Imlementtion Slie to ccomny the tetoo Digitl Deign, Firt Eition, y Frn Vhi, John Wiley n Son Puliher,. htt://.vhi.com Coyright Frn Vhi Intructor of coure requiring Vhi' Digitl Deign tetoo (ulihe y John Wiley n Son) hve ermiion to moify n ue thee lie for cutomry coure-relte ctivitie, uject to eeing Digitl thi coyright Deign notice in lce n unmoifie. Thee lie my e ote unnimte f verion on ulicly-cceile coure eite.. PoerPoint ource (or f ith nimtion) my not e ote to ulicly-cceile eite, ut my e ote for tuent on internl rotecte ite or itriute irectly to tuent y other electronic men. Coyright Intructor my me rintout of the lie ville to tuent for reonle hotocoying chrge, ithout incurring royltie. Any other ue require elicit ermiion. Intructor my otin PoerPoint Frn ource Vhi or otin ecil ue ermiion from Wiley ee htt://.vhi.com for informtion. Introuction. A igitl circuit eign i jut n ie, erh rn on er We eventully nee to imlement the circuit on hyicl evice Ho o e get from () to ()? Belt Wrn IC Digitl Deign Coyright Frn Vhi () Digitl circuit eign () Phyicl imlementtion Note: Slie ith nimtion re enote ith mll re "" ner the nimte item

2 Mnufcture IC Technologie. We cn mnufcture our on IC Month of time n million of ollr () Full-cutom or () emicutom () Full-cutom IC We me full cutom lyout Uing CAD tool Lyout ecrie the loction n ize of every trnitor n ire A f (friction lnt) uil IC for lyout Hr! F etu cot ("non-recurring engineering", or NRE, cot) high Error rone (everl "rein") Firly uncommon Reerve for ecil IC tht emn the very et erformnce or the very mllet Digitl Deign ize/oer Coyright Frn Vhi BeltWrn IC month Cut om lyout F Mnufcture IC Technologie Gte Arry ASIC () Semicutom IC "Aliction-ecific IC" (ASIC) () Gte rry or () tnr cell () Gte rry Serie of gte lrey lye out on chi We jut ire them together Uing CAD tool V. full-cutom Cheer n quicer to eign But ore erformnce, ize, oer Very oulr () () BeltWrn IC F ee (jut iring) () Digitl Deign Coyright Frn Vhi

3 Mnufcture IC Technologie Gte Arry ASIC () Gte rry Emle: Ming hlf-er to gte rry Hlf-er eqution: = ' + ' co = ' ' co Gte rry Digitl Deign Coyright Frn Vhi 5 Mnufcture IC Technologie Stnr Cell ASIC () Semicutom IC "Aliction-ecific IC" (ASIC) () Gte rry or () tnr cell () Stnr cell Pre-lye-out "cell" eit in lirry, not on chi Deigner intntite cell into re-efine ro, n connect V. gte rry Better erformnce/oer/ize A it hrer to eign V. full cutom Not goo of circuit, ut till fr eier to eign () () BeltWrn () IC F - month (cell n iring) Cell lirry cell ro cell ro cell ro Digitl Deign Coyright Frn Vhi

4 Mnufcture IC Technologie Stnr Cell ASIC () Stnr cell Emle: Ming hlf-er to tnr cell co = = ' + ' ' cell ro co ' cell ro ' ' co cell ro Gte rry Notice feer gte n horter ire for tnr cell veru gte rry, ut t cot of more eign effort Digitl Deign Coyright Frn Vhi Imlementing Circuit Uing NAND Gte Only Gte rry my hve NAND gte only NAND i univerl gte Any circuit cn e me to NAND only Convert AND/OR/NOT circuit to NAND-only circuit uing ming rule After converting, remove oule inverion F=' Inut F= Outut F ()' F=' F= Doule inverion F=+ Digitl Deign Coyright Frn Vhi F=('')'=''+''=+ 8

5 Imlementing Circuit Uing NAND Gte Only Emle: Hlf-er F=' F=' F= F=+ ()' F= F=('')'=''+''=+ Rule oule inverion (elete) Digitl Deign () Coyright Frn Vhi oule inverion (elete) () 9 Imlementing Circuit Uing NAND Gte Only Shortcut hen converting y hn Ue inverion ule rther thn ring inverter -inut NAND Then remove oule inverion efore oule inverion oule inverion () () oule inverion (elete) Digitl Deign Coyright Frn Vhi oule inverion (elete) 5

6 Imlementing Circuit Uing NOR Gte Only NOR gte i lo univerl Converting AND/OR/NOT to NOR i one uing imilr rule + + Digitl Deign Coyright Frn Vhi Imlementing Circuit Uing NOR Gte Only Emle: Hlf er oule inverion () oule inverion () Digitl Deign Coyright Frn Vhi

7 Imlementing Circuit Uing NOR Gte Only Emle: Set elt rning light on NOR-e gte rry Note: if uing -inut NOR gte, firt convert AND/OR gte to -inut () () 5 5 () Digitl Deign Coyright Frn Vhi Progrmmle IC Technology FPGA. Mnufcture IC technologie require ee to month to fricte An hve lrge (hunre thoun to million ollr) initil cot Progrmmle IC re re-mnufcture Cn imlement circuit toy Jut onlo it into evice Sloer/igger/more-oer thn mnufcture IC But get it toy, n no friction cot Poulr rogrmmle IC FPGA "Fiel-rogrmmle gte rry" Develoe lte 98 Though no "gte rry" inie Nme hen gte rry ere very oulr in the 98 Progrmmle in econ Digitl Deign Coyright Frn Vhi

8 FPGA Internl: Loou Tle (LUT) Bic ie: Memory cn imlement comintionl logic e.g., -re memory cn imlement -inut logic -it ie memory function; -it ie function Such memory in FPGA non Loou Tle (LUT) F = 'y' + y y () F y Mem. r D F () = y= Mem. r D F= F = 'y' + y G = y' y () F G y Mem. r D D F G (e) Digitl Deign Coyright Frn Vhi 5 FPGA Internl: Loou Tle (LUT) Emle: Set-elt rning light (gin) () BeltWrn 5 IC 8 Mem. D () Progrmming (econ) F - month Digitl Deign Coyright Frn Vhi 8

9 FPGA Internl: Loou Tle (LUT) Loou tle ecome inefficient for more inut inut only 8 or 8 inut 5 or; inut 5,5 or! FPGA thu hve numerou mll (,, 5, or even -inut) LUT If circuit h more inut, mut rtition circuit mong LUT Emle: Etene et-elt rning light ytem: t BeltWrn () 5-inut circuit, ut - inut LUT ville Digitl Deign Coyright Frn Vhi Su-circuit hve only -inut ech t inut outut =' BeltWrn () Prtition circuit into -inut u-circuit inut outut =+t+ ' +t+ t 5 8 Mem. M to -inut LUT D 5 8 Mem. D FPGA Internl: Loou Tle (LUT) Prtitioning mong mller LUT i more ize efficient Emle: 9-inut circuit c e f g h i Originl 9-inut circuit Digitl Deign Coyright Frn Vhi F c e f g h i () () Prtitione mong LUT F 5 Mem. 8 Mem. Require only -inut LUT (8 memorie) much mller thn 9-inut LUT (5 memory) 8 9

10 FPGA Internl: Loou Tle (LUT) LUT tyiclly h (or more) outut, not jut one Emle: Prtitioning circuit mong -inut -outut loou tle c e c e Digitl Deign Coyright Frn Vhi () (Note: ecomoe one - inut AND inut to mller AND to enle rtitioning into -inut u-circuit) t () F F c e Firt column unue; econ column imlement AND 8 Mem. 5 D D t 8 Mem. 5 D D F Secon column unue; firt column imlement AND/OR u-circuit 9 FPGA Internl: Loou Tle (LUT) Emle: Ming ecoer to -inut -outut LUT Su-circuit h inut, outut i i () Su-circuit h inut, outut i i 5 8 Mem. D D () 5 8 Mem. D D Digitl Deign Coyright Frn Vhi

11 P P P P P P5 Digitl Deign Coyright Frn Vhi FPGA Internl: Sitch Mtrice Previou lie h hrire connection eteen LUT Inte, nt to rogrm the connection too Ue itch mtrice (lo non rogrmmle interconnect) Simle mu-e verion ech outut cn e et to ny of the four inut jut y rogrmming it -it configurtion memory 8 Mem. 5 D D o m o m m m Sitch mtri () 8 Mem. 5 FPGA (rtil) D D P P P8 P9 m m m m Sitch mtri -it memory i i o i mu i -it memory i i o i mu i () i i i i 8 Mem. 5 D D FPGA Internl: Sitch Mtrice Ming ecoer onto n FPGA ith itch mtri o m o m m m Sitch mtri () 8 Mem. 5 FPGA (rtil) D D m m m m Sitch mtri i i i i () mu o i i i i mu o Thee it etlih the eire connection Digitl Deign Coyright Frn Vhi

12 FPGA Internl: Sitch Mtrice Ming the etene etelt rning light onto n FPGA ith itch mtri Recll erlier emle (let' ignore inut for imlicity) t BeltWrn 8 Mem. 5 D D o m o m m m Sitch mtri 8 Mem. 5 FPGA (rtil) t () () D D m m m m Sitch mtri i i i i mu o i i i i mu o Digitl Deign Coyright Frn Vhi FPGA Internl: Configurle Logic Bloc () LUT cn only imlement comintionl logic Nee fli-flo to imlement equentil logic A fli-flo to ech LUT outut Configurle Logic Bloc () LUT + fli-flo Cn rogrm outut to come from fli-flo or from LUT irectly P P P P outut fli-flo -it outut configurtion memory P P5 8 Mem. 5 D D FPGA o m o m m m Sitch mtri 8 Mem. D 5 D P P P8 P9 Digitl Deign Coyright Frn Vhi

13 FPGA Internl: Sequentil Circuit Emle uing c FPGA y () Left loou tle elo unue () Digitl Deign Coyright Frn Vhi z D D =' =' c 8 Mem. 5 D D o m o m m m Sitch mtri 8 Mem. 5 D D z y 5 FPGA Internl: Overll Architecture Conit of hunre or thoun of n itch mtrice (SM) rrnge in regulr ttern on chi Rereent chnnel ith ten of ire Connection for jut one hon, ut ll re oviouly connecte to chnnel SM SM SM SM Digitl Deign Coyright Frn Vhi

14 All configurtion memory it re connecte one ig hift regiter Knon cn chin Shift in "it file" of eire circuit Digitl Deign Coyright Frn Vhi FPGA Internl: Progrmming n FPGA () Pin Pcl c 8 Mem. 5 D D FPGA o m o m m m Sitch mtri 8 Mem. 5 D D () Pin Concetul vie of configurtion it cn chin i tht of -it hift regiter Pcl Bit file content for eire circuit: Thi in't rong. Although the it er "" ove, note tht the cn chin e through thoe it from right to left o "" i correct here. z y Other Technologie. Off-the-helf logic (SSI) IC Logic IC h fe gte, connecte to IC' in Knon Smll Scle Integrtion (SSI) Poulr logic IC erie: Originlly eveloe 9 Bc then, ech IC cot $ Toy, cot jut ten of cent VCC I I I I I I9 I8 IC I I I I I5 I I GND Digitl Deign Coyright Frn Vhi 8

15 -Serie Logic IC Digitl Deign Coyright Frn Vhi 9 Uing Logic IC Emle: Set elt rning light uing off-the-helf IC Otion : Ue one LS8 IC hving -inut AND gte, n one LS IC hving inverter () Deire circuit () I I I I I I9 I8 I LS8IC I I I I5 n I I I I I I I I9 I8 Connect IC to crete eire circuit n LSIC Digitl Deign Coyright Frn Vhi () () Decomoe into -inut AND gte I I I I I5 I I 5

Uing Logic IC Emle: Set elt rning light uing off-the-helf IC Otion : Ue ingle LS IC hving -inut NOR gte I I I I I I9 I8 Digitl Deign Coyright Frn Vhi () () Converting to -inut NOR gte I LS IC I I I

16 Uing Logic IC Emle: Set elt rning light uing off-the-helf IC Otion : Ue ingle LS IC hving -inut NOR gte I I I I I I9 I8 Digitl Deign Coyright Frn Vhi () () Converting to -inut NOR gte I LS IC I I I I5 I I Connecting the in to crete the eire circuit Other Technologie Simle Progrmmle Logic Device (SPLD) Develoe 9 (thu, re-te FPGA) Prefricte IC ith lrge AND- OR tructure Connection cn e "rogrmme" to crete cutom circuit Circuit hon cn imlement ny -inut function of u to term e.g., F = c + 'c' I I I O PLD IC rogrmmle noe Digitl Deign Coyright Frn Vhi

17 I I I Progrmmle Noe in n SPLD Fue e "lon" fue remove connection Memory e crete connection rogrmmle noe Fue e O () Fue "unlon" fue "lon" fue rogrmmle noe PLDIC mem Memory e mem () Digitl Deign Coyright Frn Vhi PLD Dring n PLD Imlementtion Emle Common y of ring PLD connection: Ue one ire to rereent ll inut of n AND Ue "" to rereent connection Croing ire re not connecte unle "" i reent Emle: Set elt rning light uing SPLD BeltWrn I I I ire AND I I' PLD IC ' O Digitl Deign Coyright Frn Vhi To y to generte term PLD IC

18 PLD Etenion I I I I I I rogrmmle it O O FF O O () Digitl Deign Coyright Frn Vhi PLD IC To-outut PLD () FF PLD IC PLD ith rogrmmle regitere outut cl 5 More on PLD Originlly (9) non Progrmmle Logic Arry PLA H rogrmmle AND n OR rry AMD crete "Progrmmle Arry Logic" "PAL" (tremr) Only AND rry rogrmmle (fue e) Lttice Semiconuctor Cor. crete "Generic Arry Logic "GAL" (tremr) Memory e A IC ccitie incree, comnie ut multile PLD tructure on one chi, interconnecting them Become non Comle PLD (CPLD), n oler PLD ecme non Simle PLD (SPLD) GENERALLY SPEAKING, ifference of SPLD v. CPLD v. FPGA: SPLD: ten to hunre of gte, n uully non-voltile (ve it ithout oer) CPLD: thoun of gte, n uully non-voltile FPGA: ten of thoun of gte n more, n uully voltile (ut no reon hy couln't e non-voltile) Digitl Deign Coyright Frn Vhi 8

19 r e r o g r m m le r e r o g r m m le Technology Comrion.5 PLD FPGA rerogrmmle Full-cutom Stnr cell (emicutom) Gte rry (emicutom) Quicer vilility Loer eign cot Eier eign Fter erformnce Higher enity Loer oer Lrger chi ccity More otimize Digitl Deign Coyright Frn Vhi Technology Comrion Proceor vrietie Cut om roceor Progrmmle roceor () PLD FPGA Gte Stnr rry cell Digitl Deign Coyright Frn Vhi () () More otimize Eier ei gn IC technologie () Full-cutom (): Cutom roceor in full-cutom IC Highly otimize (): Cutom roceor in FPGA Prllelize circuit, loer IC technology ut rogrmmle (): Progrmmle roceor in tnr cell IC Progrm run (motly) equentilly on moerte-coting IC (): Progrmmle roceor in FPGA Not only cn roceor e rogrmme, ut FPGA cn e rogrmme to imlement multile roceor/coroceor 8 9

20 Key Tren in Imlementtion Technologie Trnitor er IC ouling every 8 month for t three ece Knon "Moore' L" Tremenou imliction liction infeile t one time ue to outrgeou roceing requirement ecome feile fe yer lter Cn Moore' L continue? Digitl Deign Coyright Frn Vhi Trnitor er IC (million),,, Chter Summry Mny y to get from eign to hyicl imlementtion Mnufcture IC technologie Full-cutom IC Decie on every trnitor n ire Semi-cutom IC Trnitor etil re-eigne Stnr cell: Plce cell n ire them Gte rry: Jut ire eiting gte FPGA Fully rogrmmle Other technologie Logic IC, PLD Belt Wrn () Digitl circuit eign IC () Phyicl imlementtion Digitl Deign Coyright Frn Vhi

ECE 274 Digital Logic Fall Digital Design. RTL Design RTL Design Method: Preview Example. RTL Design RTL Design Method

ECE 274 Digital Logic Fall Digital Design. RTL Design RTL Design Method: Preview Example. RTL Design RTL Design Method ECE 274 igitl ogi Fll 2 ntroution to igitl eign 5. 5.2 igitl eign Chpter 5: lie to ompny the textbook igitl eign, Firt Eition, by Frnk Vhi, John Wiley n on Publiher, 27. http://www.vhi.om Copyright 27