Methodology: Interconnect examples

Transcription

1 Circuit-to-System to Design-Space Exploration Methodology: Interconnect examples Ranko Sredojević and Vladimir Stojanović Integrated Systems Group Massachusetts Institute of Technology

2 Convergence of platforms Only way to meet future system feature set, design cost, power, and performance requirements is by programming a processor array Multiple parallel general-purpose processors (GPPs) Multiple application-specific processors (ASPs) Intel Network Processor 1 GPP Core 16 ASPs (128 threads) 64b Stripe RDRA M 1 PCI (64b) 66 MHz RDRA M 2 Intel XScale Core 32K IC 32K DC RDRA M 3 Sun Niagara 8 GPP cores (32 threads) Intel 4004 (1971): 4-bit processor, 2312 transistors, ~100 KIPS, 10 micron PMOS, 11 mm 2 chip G A S K E T Cisco QDR QDR QDR QDR SRAM SRAM SRAM SRAM E/D Q E/D Q E/D Q E/D Q IXP280 S Rbuf 16b 128B 0 P I 4 or C S 16b I X Tbuf 128B Hash CSRs 48/64/1 -Scratc 28 Fast h_ wr -UART 16KB - Timers -GPIO - BootROM/Sl owport 1000s of processor cores per die IBM Cell 1 GPP (2 threads) 8 ASPs CSR Tensilica GPPs Picochip DSP 1 GPP core 248 ASPs The Processor is the new Transistor [Rowen] MIT ISG 2 2

3 Multi-core communication infrastructure IBM CELL Sun Niagara DIMM DIMM DIMM DIMM interface bus Centralized switch (Bus, Crossbar) Fast, but scales poorly Power hungry Distributed switch (e.g. Mesh) Slow, power hungry Other on-chip networks (fat tree, torus, etc) Compromise between density, power and latency/data rate Memory interfaces Power and density limit DIMM DIMM DIMM DIMM cross-bar mesh DIMM DIMM DIMM DIMM interfaces Intel Terascale rings MIT ISG 3 3

4 ISG playing field Interconnect Problem On-chip Network Off-chip I/O Network Architecture Design Optimization Communication (Eq., Mod, Coding) Energy/Bit (pj/bit) Equalized, 30mV Eye Equalized, 50mV Eye Equalized, 90mV Eye Repeated Link modeling, Characterization Circuits Tx, Rx, Ctrl, Meas inp inn I + Ithresh 2 clk outn outp inp outp I Ithresh clk 2 clk outn Q Q Data Rate Density y( (Gbps/um) pre-amp with offset comparator Interconnect technology CNTs Si-Photonics Cu [IBM] MIT ISG 4 4

5 High-speed link design is hard Designer s task minimize Power subject to Data rate SysClk TX Data RefClk 1/4 or 1/5 1 or 1/2 TX Parallel to Serial EQ Tclk Phase Mixer PLL Phase Mixer Mixer Rclk Vtt TXP TXN BER Area RX Data RX Clk Phase Control Serial to Parallel Rclk Vtt RXP RXN RX Equalizer Key questions Tap Selection Tap Weights Where to allocate the power and area? Which block has the most impact on data rate (BER)? Equalizers, PLL, CDR, precision samplers and pre-amps MIT ISG 5 5

6 Iterative design flow: HSL example Block interactions through system designer Assume enough design margin for flow to converge quickly Share: multidimensional i l performance tradeoff sets Integrated Systems Group 6

7 Optimization-driven design flow Optimization engine Block interactions handled simultaneously by solver Eliminate iterations due to multidimensional tradeoff comm. Share: interface variables (not the actual specifications!) Integrated Systems Group 7

8 Optimization-based design challenge Optimization engine Flexible, parameterized system level formulation is missing!! [Amsp:Hershenson 2001, Mandal 2001] Circuit optimization relatively mature [ADC: Hershenson 2002] Transistor sizing (since GP solvers) Biasing & improved accuracy (since Signomial solvers) Problem: system level formulation tractability Express system performance parameterized with all circuit parameters [PLL: Colleran 2003] Integrated Systems Group 8

9 Performance Metrics Tx FIR Rx IIR Parameterized filters Goal to parameterize performance metric (BER, eye opening) BER, eye opening

10 Seems straightforward Tx FIR Rx IIR Just need to find the parameterized symbol response! Each sample is a function of: TxEQ taps; RxEq gain, poles and zeroes; Channel response Parameterized symbol response BER Integrated Systems Group 10

11 A simple complexity example 2-taps Impulse response 20-bit sampled: 10x intervals long Oversampled: 10x Each sample is a function of: TxEQ taps; RxEq gain, poles and zeroes; Channel response IIR-type TF 2-real poles 30-term expansion (~3% accuracy) Parameterized symbol response BER Overal response length: =278 samples Number of total terms: 20x200x30x30=3.6e Average number of terms per sample: ~13,000 Hard to generate Integrated Systems Group 11

12 Math view Parameterized System Transfer Function Tx FIR Channel Rx Equalizer Transfer Function calculation is o.k. but FIR expansions for IIR explode the problem MIT ISG 12 12

13 Key idea: Fitting approach Easy to get parameterized transfer function Hard to get parameterized symbol response directly! Discover the symbol response samples by fitting Make this process a part of system optimization Parameterized system H(f,p) transfer function h(t,p) Fitted, sampled transfer function f Previous example (278 samples, 2 nd order IIR) 280 equations with 2 terms each (complexity hidden in this system) Integrated Systems Group 13 t

14 Math view H(f,p) Fitting Error Fitting variables h Make fitting part of system optimization f Compact representation Can generate symbolic formulation quickly Hard to solve Each constraint contains ALL optimization variables p,h Integrated Systems Group 14

15 Simplifying the equations Degree of IIR filters (r) << Number of samples (n) Use IDFT Easy to solve Only (r) h variables per constraint Integrated Systems Group 15

16 Verifying the idea Symbol response accuracy formulation parameter Tradeoff between accuracy and solver time 6.25Gb/s: Matching of Matlab simulation to a design instance Integrated Systems Group 16

17 Simultaneous system and circuit design Performance (eye) System formulation Specs ( block parameters) Specs (taps, swing) TxEq model: W, L, I, Vdd, Optimization engine RxEq model: W, L, I, Performance (power, area) Performance (power, area, common mode) Specs (gain, poles, zeros, dynamic range) Integrated Systems Group 17

18 Transmit Equalizer circuit formulation Circuit variables Specifications Swing, taps Performance Power, area W, L, I, vddout Biasing KVL, KCL vddout and swing dep. To keep M0 and M1 in sat. Integrated Systems Group 18

19 Transmit Equalizer circuit formulation Circuit variables Specifications Swing, taps Performance Power, area W, L, I, vddout Biasing KVL, KCL vddout and swing dep. To keep M0 and M1 in sat. Integrated Systems Group 19

20 Receive Equalizer circuit formulation Specifications Gain, poles, zeros Design variables Performance Biasing WLIbias W, L, Ibias, Cs, Rs, Power, area Input DR and sizing of M1 and M2 for sat. Integrated Systems Group 20

21 Receive Equalizer circuit formulation Tustin s approx best for discretization DR Specifications Gain, poles, zeros Linearity Design variables Performance Biasing WLI W, L, bias, C s, R s, Power, area Input DR and sizing of M 1 and M 2 for sat. Integrated Systems Group 21

22 Putting it all together code sample DC-coupled biasing Performance Objective Integrated Systems Group

23 A look under the hood Integrated Systems Group

24 Optimization results: Setup Channel 32 ATCA Minimize link power s.t. eye>100mv Integrated Systems Group 24

25 Optimization results: Power vs. timing Timing and equalization a chicken and egg problem CDR/equalization interaction Filters burn more power to achieve less phase delay! Integrated Systems Group 25

26 Optimization results: Power vs. data-rate Added DFE w/o power penalty to keep eye>100mv Transmit/receive equalizer interaction At lower speeds: equalization in transmitter At higher h speeds: Tx reduces Rx input dynamic range Integrated Systems Group 26

27 Optimization results: Paremeter values Rate [Gb/s] swingin [mv] afr None [1 -.42] [1 -.52] [ ] [ ] RxEq gain RxEq zero [GHz] RxEq dp [GHz] RxEq sp [GHz] RxEq has no significant peaking below Nyquist frequency At 8 and 10 Gb/s (with DFE) TxEq mostly dynamic range limiter for receiver wideband amplifier Integrated Systems Group 27

28 Verification and Run-time Good matching with Spectre 30% in V dsat (often solved with multiple corner optimization) 10% in gain, swing, power, 25% in pole/zero locations (traced to model and derivation) Very efficient flow Size: variables, 4500 to 5500 constraints Parsing: 15min to 1hr Solving: 50min to 3hrs Generating system level: 10mins MIT ISG 28 28

29 Conclusions Circuit-to-system design of HSLs is iterative and inefficient Tractable system formulation main problem in circuitto-system optimization-based flow Key insights No need for explicit expressions Apply fitting approach to reduce complexity First joint system and circuit design attempt in optimization environment Results verified and match intuition TxEq/RxEq interaction discovered (equalization, biasing) Not obvious to link designers Integrated Systems Group 29

30 Acknowledgments Tool/solver support Sabio Labs/Magma DA and MOSEK Sponsors Lincoln Labs, MIT CICS and MARCO C2S2 MIT ISG 30 30

31 Summer Short courses High-Speed I/O Design Techniques V. Stojanovic June 23-25, 2008 (registration deadline: May 23) MIT Campus Cambridge, MA Explore the circuit and system design of equalized high-speed I/Os. Following an introduction to the basics, focus on different link equalization techniques, comparing them from a system perspective and from the performance of resulting circuit implementations. Course includes one day of hands-on lab experience. Learn more at: Professionalinstitute.mit.edu