56+ Gb/s Serial Transmission using Duobinary Signaling

Transcription

1 56+ Gb/s Serial Transmission using Duobinary Signaling

2 Jan De Geest Senior Staff R&D Signal Integrity Engineer, FCI Timothy De Keulenaer Doctoral Researcher, Ghent University, INTEC-IMEC

3 Introduction

4 Motivation Standard groups looking into serial data rates of 50 Gb/s and above IEEE 802.3bs 400 GbE NRZ and PAM4 OIF CEI-56G-VSR/SR (< 100 mm) NRZ and PAM4 OIF CEI-56G-MR (500 mm) PAM4 Duobinary signaling presented as alternative for 56+ Gb/s serial data rates

5 Overview Duobinary signaling Duobinary demonstrator Design of duobinary chipset Measurements Conclusions

6 Duobinary Signaling

7 Duobinary Signaling NRZ signaling Requires extensive pre-emphasis or equalization T A Difficult to scale to data rates beyond 40 Gb/s PAM4 signaling Reduces spectral requirements compared to NRZ Requires less pre-emphasis and equalization than NRZ 2T More complex multi-level transmitter and receiver Reduced level spacing less tolerance to noise A/3 Duobinary signaling 3-level modulation scheme Leverages passive channel frequency response for signal shaping T A/2 Reduces spectral requirements compared to NRZ Requires less pre-emphasis and equalization than NRZ

8 Duobinary Signaling Duobinary transmission system: Data source (binary data transmitter) Duobinary precoder Feed-forward equalizer (FIR filter) Passive channel (backplane) Duobinary to binary converter (rectifier) Binary data receiver Equalization effort reduced Main shaping takes place in the channel Duobinary spectrum has null at ½ data rate FIR filter limited to 5-taps Emphasize high-frequency components Flatten group delay response

9 Duobinary Signaling Duobinary correlative coding Each symbol conveys information corresponding to the previous and current bit partial response Combination results in 3 level waveform Forbidden transitions form rudimentary error detection not considered here Requires simple precoding at transmitter Duobinary PSD Spectrum compressed compared to NRZ Same spectrum as PAM4 Relaxes channel design criteria and bandwidth requirements of transceiver IC s

10 Duobinary Demonstrator

11 Duobinary Demonstrator Scope/BERT 56 Gb/s PPG 28 GHz clock 56 Gb/s 56 Gb/s 14 Gb/s TX FFE RX TX board CHANNEL RX board

12 Duobinary Demonstrator Backplane Channel 56 Gb/s PPG 28 GHz clock Scope/BERT 56 Gb/s 56 Gb/s 14 Gb/s Figure 18: ExaMAX backplane demonstrator. TX FFE RX TX board CHANNEL RX board

13 Duobinary Demonstrator Backplane Channel db db db db ExaMAX connector system Figure 18: ExaMAX backplane demonstrator. 24 lay 160 mil backpanel 18 lay 94 mil daughter cards Megtron 6 board material Daughter card trace length = 6 Backpanel trace length = 1.7 to Total length = 13.7 to db loss per inch at 28 GHz

14 Duobinary Demonstrator Loss Scope/BERT 56 Gb/s PPG 1.05 db at 28 GHz 28 GHz clock 1.05 db at 28 GHz 56 Gb/s 56 Gb/s 5.6 db at 28 GHz 3.8 db at 28 GHz 14 Gb/s TX FFE RX TX board CHANNEL RX board

15 Duobinary Demonstrator Total Channel Loss COMPONENT LOSS at 28 GHz TX board 5.60 db Coax TX board to channel 1.05 db Channel loss IL [db] Coax channel to RX board 1.05 db RX board 3.80 db Total loss IL db

16 Chip Design

17 Chip Design Overview Transceiver chain Transmitter overview Receiver overview FFE parameter optimization

18 Transceiver Chain

19 Transmitter Building Blocks

20 Transmitter Building Blocks

21 Transmitter Building Blocks

22 Transmitter Building Blocks

23 Transmitter Building Blocks

24 Transmitter Building Blocks

25 Transmitter Building Blocks

26 Receiver Overview

27 FFE Parameter Estimation FFE impulse response calculated from frequency response FFE impulse response after channel propagation Channel delays, attenuates and reduces the bandwidth of the impulse response

28 duobinary response is done. The idealized response consists of two bit-spaced na Generating sinc pulses. Least-square-error The LSE fit matches the 5 normalized Fit FFE parameters as well as the timing. In this way, it selects the optimal number of pre- and post-cursors in the F Making a linear combination result to obtain of such the a fit best is shown match in figure 8. Figure 8: Fitting the FFE output to the ideal duobinary response.

29 1-tap FFE Parameters 56 Gb/s NRZ 56 Gb/s Duobinary 56 Gb/s PAM4 Impulse response desired - obtained Desired eye pattern normalized Obtained eye pattern normalized at output of FFE

30 2-tap FFE Parameters 56 Gb/s NRZ 56 Gb/s Duobinary 56 Gb/s PAM4 Impulse response desired - obtained Desired eye pattern normalized Obtained eye pattern normalized at output of FFE

31 3-tap FFE Parameters 56 Gb/s NRZ 56 Gb/s Duobinary 56 Gb/s PAM4 Impulse response desired - obtained Desired eye pattern normalized Obtained eye pattern normalized at output of FFE

32 4-tap FFE Parameters 56 Gb/s NRZ 56 Gb/s Duobinary 56 Gb/s PAM4 Impulse response desired - obtained Desired eye pattern normalized Obtained eye pattern normalized at output of FFE

33 5-tap FFE Parameters 56 Gb/s NRZ 56 Gb/s Duobinary 56 Gb/s PAM4 Impulse response desired - obtained Desired eye pattern normalized Obtained eye pattern normalized at output of FFE

34 Chip Design Conclusions Design of a 5-tap FFE capable of equalizing a backplane channel into a 56 Gb/s duobinary channel Design of a sensitive 56 Gb/s duobinary receiver with built-in DEMUX Optimized FFE parameters estimation methodology based on fast frequency-domain measurements and Matlab optimization techniques

35 Measurements

36 Measurements Overview Test setup 40 Gb/s BER vs. insertion loss 56 Gb/s BER measurements

37 Test Setup Scope/BERT 56 Gb/s PPG 28 GHz clock 56 Gb/s 56 Gb/s 14 Gb/s TX FFE RX TX board CHANNEL RX board

38 BER Measurement Results 40 Gb/s 40 Gb/s transmission across channels ranging from 13.7 to Gb/s Gb/s db at 20 GHz BER < 1E db at 20 GHz BER 1E-9

39 Figure 20: 40 Gb/s output eye-pattern at the transmitter (left) and after a 13.7 in BER Measurement Results backplane 40 channel Gb/s (right). Error-free (BER < 1E-12) up to about 37 db total link loss (20 channel + test setup) at Nyquist (20 GHz) BER 1E-9 up to about 42 db total link loss (26.25 channel + test setup) at Nyquist (20 GHz) Figure 21: Chart showing the BER (blue) and the vertical eye-opening (red) as a fun 10-TH3 of 56+ the Gb/s loss Serial at the Transmission Nyquist frequency using Duobinary for a Signaling 40 Gb/s signal measured across the ExaMA

40 an eye-opening of 6.8 mv as shown on the left in figure 23. By increasing BER the speed Measurement to 56 Gb/s the loss at Results the Nyquist frequency 56 Gb/s increases further, and the vertical eye-opening at the input of the receiver decreases to about 6 mv as Error-free shown on (BER the right < 1E-12) in figure operation 23. The at BER 56 Gb/s obtained across at Gb/s channel is better with than a 5E-9, total which link loss of about is more 41 than db at sufficient 28 GHz assuming FEC is applied. 56 Gb/s db at 28 GHz Figure 23: Eye-diagrams of the 50 Gb/s (left) and 56 Gb/s (right) BER < signal 1E-12 after a 13.7 in backplane channel. 4.3 Design of active daughter cards

41 Conclusions

42 Conclusions Selection of duobinary signaling as a modulation format for high-speed serial transmission Duobinary demonstrator Design of duobinary transceiver chipset Measurement results demonstrate 56 Gb/s serial transmission over a state-of-the-art backplane channel is possible using duobinary signaling Limited equalization: 5-taps FFE, no CTLE or DFE

43 Visit us at booth 817 for a live demo