High-speed Integrated Circuits for Silicon Photonics

Transcription

1 High-speed Integrated Circuits for Silicon Photonics Institute of Semiconductor, CAS Outline Introduction High-Speed Signaling Fundamentals TX Design Techniques RX Design Techniques Design Examples 2 1

2 Datacenter (towards 100/400G) Within the Rack (<10m) - Largest volume: 10GbE - To be mainstream: 25GbE - Next step: 50GbE Racks Among the Racks (<100m) - Largest volume: 40GbE - To be mainstream: 100GbE - Next step: 400GbE Datacenter Racks Long Spans/Inter-Datacenter (100-1km) - Largest volume: 100GbE - To be mainstream: 400GbE - Next step: 1TbE Datacenter Datacenter (towards 100/400G) Within the Rack (<10m) - Largest volume: 10GbE - To be mainstream: 25GbE - Next step: 50GbE Among the Racks (<100m) - Largest volume: 40GbE - To be mainstream: 100GbE - Next step: 400GbE Long Spans/Inter-Datacenter (100-1km) - Largest volume: 100GbE - To be mainstream: 400GbE - Next step: 1TbE 2

3 Optical Interconnects Optical Interconnects: Si-Photonics 3

4 Router: link among servers Line Cards (8-16 per system) Passive Backplane Switch Cards (2-4 per system) Optical interface 40Gb/s (Laser driver link) Serial Links 4x10Gb/s (chip-to-chip) Backplane Serial Links Gb/s Need higher bandwidth -> more channels in optic Bandwidth bottleneck: all serial electrical links 7 High-Performance Computer (HPC) [Sun, et al. Nature 2015] Communication between CPU and Memory 4

5 Limitation of the Electrical Link Channel loss degrades the signal (>10Gb/s) significantly Electrical EQ consumes unacceptable large power Hard to achieve high-density integration 9 What s in an Optical Module 100GBase-LR4 (4x25G) 5

6 What a Link Needs to Do Signaling: send out bits through transmitter (TX), get the bits in the receiver (RX). Timing: determine which bit is which (sequentially) 11 What s Wrong with this? In principle, nothing As long as the wire is short enough And we can get the right clock at both TX and RX 12 6

7 To Satisfy the Real Link TX: E/O conversion (Compensate for BW) Fiber with E/O and O/E nonideality RX: O/E conversion (Recover data and clk) PLL/CDR: generate and find the right clock 13 Introduction Outline High-Speed Signaling Fundamentals TX Design Techniques RX Design Techniques Design Examples 14 7

8 Random Bit Sequence (RBS) RBS is the best signal to emulate the real data Equal probability of logic 1 and 0 Spectrum of the RBS Fourier transform Dual side-band spectrum Null at 1/T b 15 Pseudo-Random Bit Sequence(PRBS) In reality, it s hard to generate true RBS Infinite sequence length, non-repeatable bit pattern PRBS keeps random only for a certain length, which is repeated periodically for the complete data sequence The length of PRBS-m is 2 m -1 bits The longest constant 0 or 1 is m bits PRBS is DC-balanced, the difference of 1 and 0 number is 1 PRBS-m sequences share the same pattern Starting phases are different (different seed), useful for BER check 16 8

9 Pseudo-Random Bit Sequence(PRBS) PRBS Spectrum Simplified as the sum of multiple (the number of logic 1 s) periodical pulses period = PRBS length X i (t) is the convolution between probability of the signal pulse and the periodical impulse function Fourier Trans. Conclusion: the longer the sequence, the finer resolution, the closer to the RBS sequence 1 7T b 17 BW Estimation based on Transient Waveform Single-pole LPF Emulation Apply 0-1V step signal to V in V out can be Define the 10%-90% rising time as T r 18 9

10 BW Estimation based on Transient Waveform Single-pole LPF Emulation Frequency response of the LPF the -3dB BW is Use T r to represent τ r Conclusion:The signal s -3dB BW can be estimated as 0.35/T r 19 Nyquist Frequency Nyquist Frequency = R b /2 The highest frequency of a PRBS takes place during 0-1 short-transitions The sequence equals to a clock with R b /2 frequency, or the Nyquist frequency BW=Nyquist frequency cannot guarantee a clear eye-diagram Hand calculation! Typically a TIA needs 0.7R b BW 20 10

11 Inter-Symbol Interference (ISI) Interferences to current and future bits, introduced by the prior-bit Origin: insufficient BW, signal reflection, channel self-resonance Mostly comes from the insufficient BW 21 BW Influence on PRBS: low-pass Low-pass filtering limits the rising and falling speed Clock signal: trivial change on the shape and amplitude PRBS signal: ISI 0 / 1 run can settle, but single-bit cannot Transition starting point varies according to different data-pattern Fixed decision threshold may lead to error Clock signal PRBS signal 22 11

12 BW Influence on PRBS: high-pass High-pass filtering happens in AC coupling to isolate the common-mode High-frequency part passes, low-frequency is filtered-out The output tries to build a common-mode to maintain DC balanced (the covered area keeps equal) DC Wander closes the eye-diagram: RC-constant must be MUCH LARGER than the longest 0 and 1 23 Eye Diagram Convenient to analyze signal integrity Information included: BW, reflection, noise, jitter Generate a eye-diagram Signal must be PRBS/RBS sequence containing all type transitions 24 12

13 Non-ideal Eye-Diagrams Sufficient BW Insufficient BW Seriously insufficient BW 25 Non-ideal Eye-Diagrams Noise: logic 1 and 0 become thick, reduced vertical opening Jitter: transition becomes thick, reduced horizontal opening Duty-cycle: asymmetric transitions; 26 13

14 Signal Reflection Mainly due to the Discontinuous Impedance Basic principle: voltage and current keep continuous at the boundary Impedance change needs to reflect part of voltage (or current), to keep Ohm s Law valid Reflection coefficient Special cases:open and short lead to fullreflection 27 Signal Reflection: Matched Impedance Termination=50Ω, T-line 50Ω Reflection at load Reflection at source 28 14

15 Signal Reflection: Open-Circuit Load Termination=1MΩ, emulating open-circuit Reflection at load Reflection at source 29 Signal Reflection: Short-Circuit Load Termination = 0 Reflection at load Reflection at source 30 15

16 Signal Reflection: Practical Case Termination=600Ω,t-line 50Ω Reflection at load Reflection at source 31 Multiple Reflection Driver output impedance 10Ω,T-line 50Ω,high-Z loading (cap) Voltage split to node-a: Calculate each reflection according to the Reflection Coefficient 32 16

17 Multiple Reflection Driver output impedance 10Ω,T-line 50Ω,high-Z loading (cap) Voltage split to node-a: Calculate each reflection according to the Reflection Coefficient 33 Introduction Outline High-Speed Signaling Fundamentals TX Design Techniques TX fundamentals Laser driver Modulator driver TX equalization RX Design Techniques Design Examples 34 17

18 What s in an Optical TX Integrated Gearbox Parallel to serial D1 D2 D3 D1 D2 D3 Dn Clock D1 D2 D3 External Gearbox Retime D1 D2 D3 D1 D2 D3 CDR System Design Consideration EML Link RX sensitivity defined by OMA High ER -> higher OMA at same laser power -> save laser power High ER -> larger driver swing -> consume driver power DML Link How to choose common-mode, or DC-bias Low common-mode -> low BW, significant relaxation oscillation High common-mode -> high power consumption 18

19 Current-Mode vs. Voltage-Mode Driver RS Modulator RS Modulator RP CP RP CP BW <->1/RS CP BW <->IMAX/CP IMAX<->RP Both voltage and current run on the T-line To determine current or voltage mode Output impedance: high or low, what defines the Zo What defines the output swing 37 Current-Mode vs. Voltage-Mode Driver Judging from the Z out and V swing Inverter SST(output R in series) CML 38 19

20 Termination Single and Double Termination When is it necessary? 39 Introduction Outline High-Speed Signaling Fundamentals TX Design Techniques TX fundamentals Laser driver Modulator driver TX equalization RX Design Techniques Design Examples 40 20

21 Circuit Model of Lasers VCSEL: ~90 ohm Rs+Ra, direct wire-bonding 41 Circuit Model of Lasers DFB Laser: smaller resistance, direct wire-bonding or TOSA 42 21

22 Driving Strategy Need to Provide both AC and DC current Current-mode driver DC current for common-mode AC current for modulation DFB needs 10x current than VCSEL 43 Introduction Outline High-Speed Signaling Fundamentals TX Design Techniques TX fundamentals Laser driver Modulator driver TX equalization RX Design Techniques Design Examples 44 22

23 Modulators Up-convertor for Light Plasma Dispersion Effect - Change carrier concentration, thus the refraction index - Change optical propagation speed (and phase) Phase Shifter Carrier injection forward bias Slow carrier recombine (few GHz BW) High optical loss Low impedance load, low voltage swing Carrier depletion - reverse bias Reduced cap ( fF/um) Low optical loss Needs relatively high voltage Travelling-Wave MZM Single-piece modulator (2-3mm) Drive at the very beginning and travel to the end Match the E/O velocity: LRC delay in the T-line Match the impedance 23

24 Travelling-Wave MZM Driver Design Challenge Need a large output swing (fixed V π *L) Attenuation along the T-line Travelling-Wave MZM Driver Design Challenge Need to drive a low impedance load Power hungry (6V swing on a 50ohm load) 24

25 Lumped Segments MZM P P P N N N P P P N N N Multiple Segments Individual P/N junctions and electrodes Short segments, lumped capacitor, no termination Lumped Segments MZM P P P N N N P P P N N N Driver design challenge Manually match the E/O velocity: BW, power Multiple PADs: need flip-chip or monolithic realization 25

26 MZM Driver Design Challenge Electrical-optical velocity match Ring Driver Design Depletion Mode Ring 26

27 Ring Driver Design Challenge Wavelength Stability Ring Driver Design Challenge Wavelength Stability 27

28 Outline Introduction High-Speed Signaling Fundamentals TX Design Techniques TX fundamentals Laser driver Modulator driver TX equalization RX Design Techniques Design Examples 55 ISI due to Insufficient BW Pre-cursor, Post-cursor, taps In optical TX, ISI comes from bond-wire, PCB trace and optical devices (E/O conversion) 56 28

29 Frequency Equalization (EQ) EQ maintains the flat amplitude response above Nyquist frequency, and remove the ISI 57 FIR Pre-emphasis: Time Domain 58 29

30 FIR Pre-emphasis: Frequency Domain For low frequency (f=0) For Nyquist frequency (f=1/2ts) Equivalent 14.4dB boost at Nyquist frequency 59 FIR Pre-emphasis Implementation Parallel weighted branches, driven by different taps delayed signals Save power, but large parasitics at output nodes 60 30

31 Outline Introduction High-Speed Signaling Fundamentals TX Design Techniques RX Design Techniques Design Examples 61 Photo Detector Electrical Current i PD, linearly related to input optical power Noise current i n,pd, uniform-distributed noise spectrum, its power density is data-dependent 62 31

32 RX Linear Channel: TIA+MA Linear transfer function H(f), including both amplitude and phase For signal with high-order modulation, AGC is needed prior to the DEC Input referred noise current i n,amp v o back calculated TIA noise dominates the whole RX 63 Decision Circuit Compare to a reference (threshold), to decide if it is logic high or low Typically implemented as the CDR Can be an ADC for complex modulation 64 32

33 输出噪声 : 放大器噪声组成部分 Output noise PSD Integrated across the decision circuit BW D (can be measured) Evaluate the RX by input referred noise, back-calculated 65 TIA Converts PD current to voltage Design Considerations Large trans-impedance gain Low resistance and low capacitance for BW 66 33

34 TIA Dynamic Range Overload current Max. peak-to-peak current to meet the BER, push TIA to saturation Dynamic Range Lower limit: sensitivity Upper limit: overload limit 67 Why not a Simple Resistor R L trades-off between BW and noise, cannot decouple 68 34

35 Shunt-Feedback TIA: with Ideal OTA Bandwidth is spread by (A+1) times Trans-impedance gain ~ R F R F can be further increased, without worrying about voltage headroom 69 Shunt-Feedback TIA: with Single-Pole OTA Additional pole is introduced by OTA 2 nd order low-pass transfer function 70 35

36 Shunt-Feedback TIA: with Single-Pole OTA Butterworth LPF: Q = 1,flat in-band 2 amplitude Bessel LPF:Q = 1, flat in-band group delay 3 71 Shunt-Feedback TIA: with Single-Pole OTA Butterworth LPF: Q = 1,flat in-band 2 amplitude Bessel LPF:Q = 1, flat in-band group delay 3 Transient step-response 72 36

37 DC Offset Compensation TIA common-mode varies with the optical average power DC-offset accumulates along the amplification path Negative feedback loop is necessary to leak any excessive DC current 73 Balanced Differential TIA Matched dummy cap Best common-mode rejection, due to balanced transfer function of positive and negative path 2 times larger RMS noise current due to additional amplification path (mainly from R F ) 74 37

38 Pseudo-Differential TIA Large shunt cap, AC ground Degraded common-mode rejection Filter-out the R F noise Almost doubled Z T 75 38