Low-Power Communications and Neural Spike Sorting

Transcription

1 CASPER Workshop 2010 Low-Power Communications and Neural Spike Sorting CASPER Tools in Front-to-Back DSP ASIC Development Henry Chen August, 2010

2 Introduction Parallel Data Architectures UCLA EE Prof. Dejan Marković + 14 grad students Effective handling of power efficiency and design complexity issues in scaled CMOS technologies Emphasis on DSP algorithms for communications and neuroscience

3 Energy-Delay Design Tradeoff suboptimal infeasible

4 Energy-Delay Optimization

5 Design Freedoms Algorithm Architecture (parallelize, pipeline, time-multiplex) Circuit (static/dynamic, DVFS, high/low V T, etc.) Design choices have cross-level implications

6 Hierarchical Optimization

7 Multi-Step Development Cycle Multiple engineering teams & design descriptions Algorithm (Matlab, C, C++) Architecture (Verilog, VHDL) Circuit (RTL, schematic/layout, standard cells) Test (pattern generator, logic analyzer) Each step requires translation & re-verification I.e., floating-point to fixed-point

8 Approach Unified Matlab/Simulink description Algorithm design and verification FPGA hardware emulation Optimized ASIC implementation ASIC test and verification Sounds like a familiar tune

9 Front-to-Back Solution Architectural & algorithmic exploration/optimization High-performance/high-throughput computation Closed-loop test environment

10 Neural Spike Sorting Design Optimization for khz-rate DSP Sarah Gibson, Vaibhav Karkare

11 Spike Sorting Neural microelectrodes often pick up signals from multiple neurons surrounding probe Each action potential needs to be resolved to its originating neuron Single-unit activity needed for basic neuroscience and biomedical applications

12 Spike Sorting Process Absolute value threshold Nonlinear energy operator Stationary wavelet transform product Principle component analysis Discrete wavelet transform Discrete derivatives Integral transform

13 On-chip Spike Sorting Conventional method: wired, software post-process Proposed: implantable wireless spike sorting

14 Need for khz-rate DSPs Signal bandwidths ~20kHz in biomedical apps. Implantable chips need to be << 800µW/mm 2 to prevent tissue damage Must have long battery life (~5-10yrs) or scavenge energy

15 Algorithm Selection Spike Detection MOPS Area (mm 2 ) Absolute Val NEO SWTP Feature Extraction MOPS Area (mm 2 ) PCA DWT DD IT

16 Interleaved Architecture

17 Multi-mode Spike Sorting Chip Power 130µW for 64 channels 52µW for 16 channels Area Die: 7.07mm 2 Core: 4mm 2 Classification accuracy: Over 90% for SNR > 0dB Power Density: 30µW/mm 2 91% data reduction

18 Flexible Radio Digital Front-Ends Chip Testing for GHz-rate DSP Rashmi Nanda

19 Why Flexible DFEs? Multi-radio integration (cellular, WiFi, GPS) Cognitive radios Evolving wireless standards WiMAX Cellular LTE

20 Conventional RX Architecture Downsides: No reconfigurability for multi-standard support Analog components don t get same power/area benefits from technology scaling

21 Replacing the RX Front-End

22 RX DFE Convert from ADC frequency F S1 to modem frequency F S2 with negligible SNR degradation

23 ASIC BWRC, ca. 2006

24 ASIC Testing w/ ROACH

25 Test Setup Matlab 1GbE PowerPC QDR SRAM BRAM FPGA LVDS IO ASIC Test Board ASIC

26 Testing Requirements High TX clock rate (400MHz target) Beyond practical limits of IBOB s V2P Long test vectors (~4Mb) Asynchronous clock domains for TX and RX

27 Asynchronous Clock Domains Manually merged separate designs for test vector and readback datapaths Fixed 60MHz RX MHz TX

28 Results Tested to 315MHz (1.89GHz RF) w/ loadable vectors in QDR Up to 340MHz (2.04GHz RF) with pre-compiled vectors in ROMs Tech. / V DD 0.13µm/1.5V 65 nm / 1.0V Area??? 0.4 mm 2 Maximum 104 MHz 2.52 GHz input sample rate Maximum 5 MHz 20 MHz signal bandwidth Current consumption 21 ma 13 ma Maximum SNR 84 db (5MHz bandwidth) 55 db (20 MHz bandwidth)

29 Limitations DDR output FF critical 340MHz (clock out) QDR SRAM bus interface critical 315MHz Output clock jitter?

30 Summary Unified description for DSP design allows multi-level iterative optimization Can be applied to any power/performance specs Matlab + BORPH/KATCP provides great test environment for DSP applications

31 Thank you!