CHAPTER 4 FIELD PROGRAMMABLE GATE ARRAY IMPLEMENTATION OF FIVE LEVEL CASCADED MULTILEVEL INVERTER

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1 87 CHAPTER 4 FIELD PROGRAMMABLE GATE ARRAY IMPLEMENTATION OF FIVE LEVEL CASCADED MULTILEVEL INVERTER 4.1 INTRODUCTION The Field Programmable Gate Array (FPGA) is a high performance data processing general purpose integrated circuit that is programmed by the designer rather than the device manufacturer. Unlike an Application Specific Integrated Circuit (ASIC), which can perform a similar function in an electronic system, an FPGA can be reprogrammed even after it has been deployed into a system meant for the specific applications. A FPGA is programmed by downloading a configuration program called a bitstream into static on chip Random Access Memory (RAM). Much like to the object code for a microprocessor, this bitstream is the product of compilation tools that translate the high level abstractions produced by a designer into equivalent but low level codes which is executable. An FPGA is similar to a Programmable Logic Device (PLD) whereas PLD is generally limited to hundreds of gates while FPGA supports thousands of gates. It is especially popular for prototyping integrated circuit designs. Once the design is finalized, hardwired chips are produced for faster performance. The inherent parallelism of the logic resources on FPGA allows considerable computational throughput even at low MHz clock rates.

2 88 The flexibility of the FPGA allows for even high performance by trading off precision and range in the number format, for an increased number of parallel arithmetic units. This has driven a new type of digital processing called reconfigurable computing, where time intensive tasks are offloaded from software to FPGA processor for real time implementations with the minimal time for processor configurations in any product development cycle discussed by Cecati et al (2002). 4.2 SYSTEM GENERATOR System Generator is a Digital Signal Processing (DSP) design tool from Xilinx that enables the use of The Mathworks model based design environment Simulink for FPGA design. Previous experience with Xilinx FPGAs or RTL, design methodologies are not required when using System Generator. Designs are captured in the DSP friendly Simulink modeling environment using a Xilinx specific blockset. Simulink provides a powerful high level modeling environment for DSP systems, and consequently is ideally used for algorithm development and verification. System Generator maintains an abstraction level very much in keeping with the traditional Simulink block sets, but at the same time automatically translates designs into hardware implementations that are faithful, synthesizable, and efficient by Cecati et al (2002) and Berto et al (2003). System generator works within the Simulink model based design methodology.

3 89 Figure 4.1 System generator flow graph Often an executable spec is created using the standard Simulink block sets. This spec can be designed using floating point numerical precision and without hardware detail. Once the functionality and basic dataflow issues have been defined, system generator can be used to specify the hardware implementation details for the Xilinx devices. The process of developing the codes for FPGA using the system generator is shown in Figure 4.1. System generator uses the Xilinx DSP blockset for Simulink and will automatically invoke Xilinx core generator to generate highly optimized netlists for the DSP building blocks. System generator can execute all the downstream implementation tools to product a bitstream for programming the FPGA. An optional test bench can be created using test vectors extracted from the Simulink environment for use with ModelSim or the Xilinx ISE Simulator. Every system generator diagram requires that at least one system generator token be placed on the diagram. This block is not connected to

4 90 anything but serves to drive the FPGA implementation process. The property editor for this block allows specification of the target netlist, device, performance targets and system period. System generator will issue an error if this block is absent. Once the FPGA boundaries have been established using the gateway blocks, the DSP design can be constructed using blocks from the Xilinx DSP blockset. Each of these blocks is cycle and bit accurate. 4.3 MODELING WITH SYSTEM GENERATOR Over ninety DSP building blocks are provided in the Xilinx DSP blockset for Simulink. These blocks include the common DSP building blocks such as adders, multipliers, registers, complex DSP building blocks such as forward error correction blocks, FFTs, filters and memories. These blocks leverage the Xilinx IP core generators to deliver optimized results for the selected device. System generator provides accelerated simulation through hardware co-simulation. System generator will automatically create a hardware simulation token for a design captured in the Xilinx DSP blockset that will run on one of over twenty supported hardware platforms. Before realizing the proposed hardware circuit for power, control and isolation circuit based on the FPGA, the entire system is simulated with the aid of simulation package simulink/system generator for specific processor in order to verify the pulses and the patterns of the output pulses. This helps to fix the switching pattern for all the switches in the power circuit. The creation of a DSP design begins with a mathematical description of the operations needed and concludes with a hardware realization of the algorithm. 4.4 SYSTEM GENERATOR SIMULATION BLOCKS The proposed algorithm is generated in front end with the aid of system generator editor, the SVM blocks with the necessary supporting blocks and the associated blocks for individual phases are interconnected and

5 91 the sampling frequency is set to 5kHz. The entire control algorithm based on SVPWM in the system generator environment is shown in Figure 4.2. For simulation of the system the output supply frequency is varied from 10Hz to 60Hz which is decided by the user input value. The wide range of frequency is considered to analyze the output variations with respect to the input and the pulse patterns for all the desired frequencies. The pulse generation process is initiated with the aid of the input frequency value through the switch and the ADC input to the processor. The complete system is designed on the Xilinx system generator environment using the blocks for the proposed FPGA based three phase five level cascaded multilevel inverter for analysis purpose at simulation level. The complete blocksets used for FPGA implementation are as shown in Figure 4.2. Figure 4.2 Block diagram for generation of firing pulses for CMLI using system generator

6 92 The input parameters for the simulations are the desired output frequency of the inverter system and the sampled phase voltages of the output. The output AC frequency is decided by the user according to the requirement on the load side of the drive system. The range of inverter output AC supply frequency is from 10Hz to 60Hz. The AC frequency is given at input1 (IN 1 ) and sampled input of phase voltage is at input (IN 2 ). From these inputs the frequency and amplitude levels are obtained and fixed for further levels. The fixed amplitude is fetched as reference to all the phases i.e. R, Y and B in order to obtain the symmetry on the three phase AC voltages on the output side of the multilevel inverter. From the desired frequency, sine waveform is generated and it is compared with the carrier waveforms, the centering of individual sampled voltages are done and the time instances T a, T b and T not are obtained as described in previous chapter. The T a, T b and T not are the corresponding phase voltages. The four carrier waveforms are generated with the variation of sample counts of The upper two carrier triangular waveforms are generated with the aid of two up counters, one is from 0 to 4000 and other is from 4000 to The magnitude is varied from zero to maximum for both the triangular carrier waveforms. The another two set of waveforms are generated with the aid another pair of down counters, one is decremented to zero from 4000 and other counter is decremented from 8000 to 4000 and thus (n-1) carrier waveforms are generated with the aid of blocks as shown in Figure 4.3. The sampled amplitudes of phase voltages V RN, V YN and V BN are used to obtain time equivalents of phase voltages. The obtained time equivalents are T as,t bs and T cs. The maximum time interval T max and minimum time interval T min are obtained from the obtained time equivalents T as, T bs and T cs. T effective is calculated once the offset time period is calculated from T max and T min. The corresponding individual phase crosses are T A cross, T B cross and T C cross, phase crosses are sorted to find T first cross,t second cross and T third

7 93 cross. Assign first_cross_phase, second_cross_phase and third_cross_phase, the sequence at which the crossings occurred, and according to the phase which determines T first cross,t second cross and T third cross and time intervals T ga, T gb and T gc as described earlier. The obtained time intervals are referred as T a, T b and T not for understanding. Figure 4.3 System generator sub block for n-1 carrier generation The time equivalents of the generated phase voltages are combined with (n-1) carrier and sine wave for the given input frequency and output pulses from out1 to out8 are generated as shown in Figure 4.4. For all the three phases the pulses are obtained in the same pattern except time delays for three phase voltages. The sub block used for R phase pulse generation is as shown in Figure 4.6. In the same pattern for Y and B phase sub blocks are designed.

8 94 Figure 4.4 System generator subblock for generation of T a, T b and T not Figure 4.5 Subblock for sine wave generation to find individual crosses The generated pulse patterns are viewed with the scope. The pulses 1 to 4 for power switches are as shown in Figure 4.7. The other set of pulses from 5 to 8 are as shown in Figure 4.8. The pulse patterns are sufficient in phase displacements and suitable for application to the power switches.

9 95 Figure 4.6 R phase sub block for T a, T b and T not Figure 4.7 Pulses 1-4 for power switches

10 96 Figure 4.8 Pulses 5-8 for power switches 4.5 SYSTEM GENERATOR SIMULATION FOR FPGA IMPLEMENTATION The obtained pulses are linked to the individual H bridges of various phases of different levels with the aid of linker block as shown in Figure 4.9. From the linker block the gate pulses are linked to the individual IGBTs gate terminal to trigger. Once the power switches at different levels are supplied with the triggering pulses it will get turned ON and OFF according to the pulse patterns. The output voltage starts to build up across the bridges corresponding to the phase sequence of the pulse patterns. The voltages built up across the phases are captured with the aid of scopes. The three phase voltages and line to line voltages are capture and presented.

11 97 Figure 4.9 Connection of system generator blocks with single H bridge Figure 4.10 Output phase voltage for R phase Figure 4.10 shows the output voltage across the R phase, similarly Figure 4.11 and Figure 4.12 shows the output phase voltages across Y and B phases respectively. Figure 4.13 shows the output five level three phase line voltages across the output of the five level cascaded multilevel inverter. The individual lines are phase shifted by as shown. Figure 4.14 and

12 98 Figure 4.15 shows the output five level phase voltages for cascaded multilevel inverter configuration. Figure 4.11 Output phase voltage for Y phase Figure 4.12 Output phase voltage for B phase

13 99 Figure 4.13 Three phase five level output line voltages for cascaded multilevel configuration Figure 4.14 Three phase voltages across the output phases for five level cascaded configuration

14 100 Figure 4.15 Output three phase five level phase voltages for cascaded configuration The three phase five level cascaded multilevel inverter is simulated using the system generator environment for Spartan FPGA processor which enables the design to make easy, fast and flexible in design and code generation. The code can be designed for any levels for the cascaded configuration with diminutive changes on the overall system blocks. The same can be converted into the equivalent coding and can be downloaded in to the processor for practical implementation. The control technique employed here for the pulse generation is modified SVPWM technique discussed in the previous chapters. The pulses were generated; patterns are verified and applied to the respective switches. The stepped output waveforms are obtained across the different phases of the multilevel inverter. The obtained output waveforms are at the correct phase displacements. The codes are downloaded into the FPGA processor and the hardware designs are initiated for the desired topology and level.

15 CONCLUSION The implementation of a FPGA based SVPWM switching strategy for the cascaded multilevel inverter was discussed. The various stages of the design for the specific FPGA processor are presented with the blocks on the system generator environment. The individual blocks outputs were presented for verification. The final phase and line stepped output voltage waveforms were also presented. The stepped waveforms confirm the required parameters like phase displacement, phase sequence and equal peak voltages for the proposed hardware of three phase multilevel inverter. The proposed SVPWM was implemented and the patterns were verified. The main advantage of this technique is the ability to generate SVPWM waveform generation in real time using the proposed algorithm in the XILINX FPGA processor. This reduces the computation time required to determine the switching times for inverter leg and memory requirement of the digital processors. This makes the proposed algorithm suitable for real time implementation and coding can be developed for the different levels with minimum time for design. Furthermore it also results in higher fundamental component magnitude with higher inverter levels. Based on the blocks designed for the proposed algorithm the codes were downloaded in to the XILINX FPGA processor and the control pulses for three phase five level cascaded multilevel inverter were generated using the same.