ΕΠΛ 605: Προχωρημένη Αρχιτεκτονική

Transcription

1 ΕΠΛ 605: Προχωρημένη Αρχιτεκτονική Υπολογιστών Presentation of UniServer Horizon 2020 European project findings: X-Gene server chips, voltage-noise characterization, high-bandwidth voltage measurements, di/dt viruses, V MIN characterization UCY CS department - Zacharias Hadjilambrou 1

2 UniServer Project Overview 3.5 years major research project funded by European Community s Horizon 2020 research program. Project budget 4.8 million Started in February 2016 to finish in July 2019 Aims to develop universal system and software architecture for servers targeting cloud and edge computing market Key principle behind Uniserver approach is exposing the hardware intrinsic variations by pushing the operating voltage, frequency, refresh rates points beyond the pessimistic nominal values UCY CS department - Zacharias Hadjilambrou 2

3 UniServer Partners Applied Micro provides the hardware, the X-Gene2 and X-Gene3 state-of-the-art ARM 64bit server CPUs QUB, UCY, UOA, ARM lead the hardware characterization effort that will reveal the pessimistic operating points UTH and IBM lead the effort of developing fault-tolerant hypervisor and resource managers (e.g. open stack) WSE, MER and SPA provide the application where the Uniserver software hardware ecosystem will be evaluated on UCY CS department - Zacharias Hadjilambrou 3

4 UniServer Hardware X-Gene2 server board 8 2.4GHz, 0.98V at 28nm 8MB LLC cache 32 GB DDR3 X-Gene3 server board 32 3GHz, 0.87V at 16nm 32MB LLC cache 128GB DDR4 UCY CS department - Zacharias Hadjilambrou 4

5 X-Gene 2/3 chip layout Source HotChips 2014 Cores are packed into PMD (processor modules) Each PMD has two cores and one shared among the two cores L2 cache (256KB) Each core has private 32KB L1I and L1D L1 cache is write through to L2. Questions: What is the optimal allocation strategy of threads to cores for performance? Is this like SMT? 8MB L3 is shared among all cores UCY CS department - Zacharias Hadjilambrou 5

6 X-Gene2 uarch block diagram Branch predictor 4 wide superscalar 1 pipeline for SIMD and float instructions One ALU for simple int One for complex int UCY CS department - Zacharias Hadjilambrou 6

7 X-Gene Voltage knobs X-Gene2/3 servers offer 3 voltage domains CPU, LLC, DRAM Hence we can optimize the voltage for CPU, LLC and DRAM Moreover we can optimize the DRAM refresh-rate UCY CS department - Zacharias Hadjilambrou 7

8 Power Supply Voltage UniServer Motivation - Dennard scaling 1,2 1 0,8 0,6 0,4 0,2 ITRS 2001 Projections Voltage used to scale linearly with transistor dimensions following Dennard s Rule Year SOURCE ITRS UCY CS department - Zacharias Hadjilambrou 8

9 Power Supply Voltage End of Dennard Scaling 1,2 1 0,8 ITRS 2001 Projections ITRS 2015 Projections 0,6 0,4 0,2 15 years shift Year Limited voltage scaling since ~2005 ITRS 2001 projections fell significantly off SOURCE ITRS UCY CS department - Zacharias Hadjilambrou 9

10 Limited Energy Efficiency Gains Based on [HEsm.ISCA11, ITRS13, JKoo.AHC11], UCY CS department - Zacharias Hadjilambrou 10

11 Limited Voltage Scaling Factors Unpredictable issues at small technology nodes Leakage Vthreshold Voltage margins for Process variations Voltage Noise UCY CS department - Zacharias Hadjilambrou 11

12 Process Variations CPU Products Names: Across Chips X100 X200 X300 Intra-Chip Frequency F req1 (2.7GHz) < F req2 (3GHz) < F req3 (3.3GHz) UCY CS department - Zacharias Hadjilambrou 12

13 UniServer approach Depart from pessimistic operating points by revealing and exploiting at runtime the true capabilities of each CPU, DRAM, core,... UCY CS department - Zacharias Hadjilambrou 13

14 Dealing with hardware variations across chips/drams How to set the optimal voltage/refresh-rate for a given frequency for each chip/drams individually? Characterize each chip with V MIN testing. Apply a different voltage to each chip based on the V MIN test results UCY CS department - Zacharias Hadjilambrou 14

15 VMIN (mv) How to V MIN test? Test many benchmarks lu mg ep is cg bt sp ua dc benchmarks The highest Vmin is the chip s Vmin UCY CS department - Zacharias Hadjilambrou 15

16 How to V MIN test? Test one worst-case benchmark/stress-test/virus Craft a virus that creates worst-case conditions and do a V MIN run for the virus only We need CPU, LLC (last level cache) and DRAM viruses DRAM and LLC viruses: Attempt to fill the SRAM/DRAM cells within patterns that maximize the probability of bit-flips CPU viruses: Attempt to maximize voltage-noise. Note this is different from maximizing power e.g. Prime95 UCY CS department - Zacharias Hadjilambrou 16

17 Limited Voltage Scaling Factors Unpredictable issues at small technology nodes Leakage Vthreshold Voltage margins for Process variations Voltage Noise UCY CS department - Zacharias Hadjilambrou 17

18 Voltage-Noise in CPUs Caused by sudden variations in CPU power consumption Voltage-noise sources: Low-power techniques e.g. clock-gating and power-gating Pipeline flushes (e.g. due to branch miss prediction) followed by high power activity cause Activity switching between high and lower power at a rate equal to the PDN 1 st resonance frequency UCY CS department - Zacharias Hadjilambrou 18

19 Power-Delivery-Networks 101 ~2 us ~10 ns ~5 us PDN reacts to large current stimulus with a response that has 3 dominant frequencies (resonance frequencies) The largest droop (1 st order resonance droop) occurs at ~10 ns Repeated large current (I) draw at 10ns amplify voltage-noise. This is what voltage-noise (di/dt) viruses attempt to do. Time (us) UCY CS department - Zacharias Hadjilambrou 19

20 CPU Voltage (mv) Why voltage-noise is bad? 1000 Nominal Voltage 950 Voltage droop time (ns) UCY CS department - Zacharias Hadjilambrou 20

21 How to deal with voltage-noise? Nominal Voltage set by manufacturer Needed voltage margin V MIN Extra Margin Needed Margin Excessive Margining Heat issues Energy inefficiency Intrinsic V MIN How to shave the unnecessary margin? Use di/dt stress-tests, they are good stability tests for V MIN testing because they drop the voltage very low The V MIN of the virus can dictate the nominal voltage UCY CS department - Zacharias Hadjilambrou 21

22 Voltage-noise (di/dt) viruses development On-Chip Circuits High-bandwidth voltage-measurements On-Package Measurement Points SOURCE [ARM ISSCC 2015] To develop di/dt viruses high-bandwidth voltage-measurements are required to measure the virus effectiveness and progress. Otherwise have to rely on V MIN (which is very time consuming) Genetic algorithms (GA) to find the type and order of instructions that maximize voltage-noise. Manual virus crafting is possible but time-consuming UCY CS department - Zacharias Hadjilambrou 22

23 Genetic-algorithm for di/dt virus generation Generate initial population (random assembly instruction sequences) Measure population (run each instruction sequence on the target-machine and measure the voltage droop) Select two parents (Pick two of the fittest instruction sequences that cause the largest voltage-droop) Create two children by crossover (exchange instructions between parents) Mutate children (randomly change some instructions) Whole process repeats until we are happy with the results.. Or the metric of interests does not improve over generations No Yes Population size reached? UCY CS department - Zacharias Hadjilambrou 23

24 max voltage droop (mv) Vmin (mv) GA di/dt virus vs SPEC benchmarks on Cortex-A GA optimization was driven by high-bandwidth voltagemeasurements from an on-chip oscilloscope available for Cortex-A72 VMIN (mv) maxdroop (mv) Chip has a nominal voltage of 1000mV virus V MIN is at 850mV -> potential to shave 150mV GA virus has higher V MIN and causes higher voltage droop UCY CS department - Zacharias Hadjilambrou 24

25 Novel methodology for high-bandwidth voltage-noise measurements Spectrum analyzer Antenna CPU X-Gene2 validation board doesn t support high-bandwidth voltagemeasurements, had to find an alternative approach for generating di/dt viruses UCY CS department - Zacharias Hadjilambrou 25

26 Cortex-A72 Cluster Voltage (mv) Voltage-noise oscillations manifest as EM spikes Voltage oscillations at 15ns This manifests as spectrum spike at 67MHz (1/15ns) time (ns) Higher-Amplitude EM signals => Higher voltage noise UCY CS department - Zacharias Hadjilambrou 26

27 EM Amplitude (nw) max voltage droop (mv) GA driven by EM peak_amplitude (nw) maxdroop (mv) As EM amplitude increases voltage droop increases GA driven by EM amplitude converges to di/dt virus GA optimization iterations UCY CS department - Zacharias Hadjilambrou 27

28 VMIN (mv) EM virus on X-Gene2 V MIN vs NAS benchmarks EM virus has the highest V MIN UCY CS department - Zacharias Hadjilambrou 28

29 Exposing hardware heterogeneity with EM virus Stress-test (mv) nominal zero margin mV margin 20mV margin CHIP#1 TTT CHIP#2 TSS CHIP#3TFF We can lower the voltage on chips #1 and #2 to save power UCY CS department - Zacharias Hadjilambrou 29

30 Power (W) Overall savings by undervolting all components PMD LLC DRAM Total Component PMD voltage reduced 50mV LLC voltage 30mV DRAM refresh rate relaxed 35X 20% overall power savings Nominal Undervolted UCY CS department - Zacharias Hadjilambrou 30