On the Rules of Low-Power Design

Transcription

1 On the Rules of Low-Power Design (and Why You Should Break Them) Prof. Todd Austin University of Michigan

2 A long time ago, in a not so far away place

3 The Rules of Low-Power Design P = acv 2 f + VIV I leak V 2 1.2v Noise margin 1. Minimize switching activity 2. Design for lower load capacitance 3. Reduce frequency 4. Reduce leakage Ambient margin Process margin 0.8v V th and the most important of all: 5. Decrease supply voltage! Critical voltage (determined by critical path)

4 Goals of This Presentation Review some of the rules of low-power design Show how clever designs can break these rules Razor resilient circuits Subliminal subthreshold voltage processor Highlight the benefits of taking a rule-breaking approach to technical research

5 Overclockers Break the Rules 1.2v Noise margin Ambient margin Process margin 0.8v V th

6 Investigating Overclocking

7 Two Slow Pipelines Check a Fast Pipeline Slow Pipeline A 48-bit LFSR 48-bit LFSR clk/2 clk/2 X 18x18 45 MHz Slow Pipeline B X 18x18 45 MHz Fast Pipeline clk/2 clk/2 clk/2!= 40-bit Error Counter X 18x18 36 stabilize clk 90 MHz clk clk

8 Discovery: Voltage Margins Are Plentiful 18x18-bit Multiplier Block at 90 MHz and 27 C 35% energy savings with 1.3% errors 20% energy savings Supply Voltage (V) 1.69 V 1.54 V % % % % % % % % % % % One error every 20 seconds! Margin grows if a few (~1%) errors can be tolerated Error rate

9 Razor Resilient Circuits [MICRO 03] Main FF Main FF MEM clk clk Shadow Latch 9 clk_del Double-sampling metastability tolerant latches detect timing errors Second sample is correct-by-design Microarchitectural support restores program state Timing errors treated like branch mispredictions

10 Distributed Pipeline Recovery Cycle: inst1 inst2 inst5 inst6 inst7 inst8 inst3 inst4 inst2 PC IF Razor FF error ID bubble Razor FF error EX bubble Razor FF error MEM (read-only) bubble Razor FF error bubble Stabilizer FF WB (reg/mem) recover recover recover recover Flush Control flushid flushid flushid flushid Builds on existing branch prediction framework Multiple cycle penalty for timing failure Scalable design as all communication is local

11 Razor-Based Dynamic Voltage Scaling E diff = E ref - E sample reset E ref - E diff Voltage Control Function Voltage Regulator V dd Pipeline error signals... E sample Current design utilizes a very simple proportional control function Control algorithm implemented in software

12 Effects of Razor Voltage Scaling Energy Pipeline Throughput 1% IPC Total Energy, E total = E proc + E recovery 44% Optimal E total Energy of Processor Operations, E proc Energy of Processor w/o Razor Support Decreasing Supply Voltage Energy of Pipeline Recovery, E recovery

13 Razor (and Razor-like) Prototypes UMich Razor Prototype 2005: 44% energy savings Intel Razor Prototype 2008: 32% power savings ARM Razor Prototype 2010: 52% power savings IBM Power7 Deployment 2011: 24% power savings

14 How Razor Breaks the Rules Traditional worst-case design techniques observe margin rules for reliable operation Incorporating timing-error correction mechanisms allow margins to be erased 1.2v Noise margin Ambient margin Process margin 0.8v Infrequent use of critical paths allow for even deeper cuts in V dd V th

15 What I Really Learned A rule-breaking approach to technical research is effective and engaging You will often find yourself on very fertile ground The rules create artificial barriers that hide good ideas You will more fully engage your community One half will think your crazy idea will never work One half will be intrigued (with your crazy idea)

16 Back to the Rules 1. Minimize switching activity 2. Design for lower load capacitance 3. Reduce frequency 4. Reduce leakage P = acv V 2 f + VIV I leak and the most important of all: 5. Decrease supply voltage! V th Critical voltage (determined by critical path) 1.2v Noise margin Ambient margin Process margin 0.8v

17 Subthreshold Circuits Break The Rules Superthreshold Subthreshold 1.2V IN P OUT 1.2V 0.2V IN P OUT 0.2V 0V N 0V 0V N 0V Static logic still works below V th Differences in I leak continue to (dis)charge outputs But diminished I on /I off ratio results in big delays

18 The Basics of Subthreshold Circuit Operation A Short Animation by Leyla Virginia Tech

19 Episode 1: Inverter operation in superthreshold domain

20 Superthreshold IN P N OUT 1.2V 0V P N 20

21 Superthreshold 1.2V IN P OUT 1.2V 0V N 0V P N 21

22 Superthreshold 1.2V IN P OUT 1.2V 0V N 0V P N 22

23 Superthreshold 1.2V IN P OUT 1.2V 0V N 0V P N 23

24 Episode 2: Inverter operation in subthreshold domain

25 Subthreshold IN P OUT 0.2V 0V N P N 25

26 Subthreshold 0.2V IN P OUT 0.2V 0V N 0V P N 26

27 Subthreshold 0.2V IN P OUT 0.2V 0V N 0V P N 27

28 Subthreshold 0.2V IN P OUT 0.2V 0V N 0V Key takeaway: subthreshold Pcircuits are SLOW, they are useful primarily for energy-conscious applications with low performance demands N 28

29 (Not Too Demanding) Sensing Applications Security Biomedical Environmental Industrial

30 Sensor Processing Data Rates

31 Sensing Performance Demands are Low xrt: # times faster than real-time Platform ARM 720T ARM 7TDMI ARM 920T ARM 1020T Voltage (V) Speed (Hz) 100M 133M 250M 325M

32 Fast Growing Leakage Complicates Design E inst = E cycle CPI Cycles per Instruction Energy per Instruction Energy per Cycle 2 E cycle = ½ C s V dd + V dd I leak t clk Activity factor - average number of transistor switches per transistor per cycle Total circuit capacitance Supply Voltage Leakage current Clock period

33 Fast Growing Leakage Complicates Design 2 E cycle = ½ C s V dd + V dd I leak t clk Activity factor - average number of transistor switches per transistor per cycle Total circuit capacitance Supply Voltage Leakage current Clock period Impact of voltage reduction I leak t clk E leak E dyn E cycle Superthreshold linear linear ~const. quad. quad. Subthreshold linear exp. ~exp. quad.??? Tension

34 Fast Growing Leakage Complicates Design Impact of voltage reduction I leak t clk E leak E dyn E cycle Superthreshold linear linear ~const. quad. quad. Subthreshold linear exp. ~exp. quad.??? Tension

35 Lessons from Architectural Studies [ISCA 05] To minimize energy at subthreshold voltages, architects must: Minimize area Maximize Transistor utility Minimize CPI To reduce leakage energy per cycle To reduce V min and energy per cycle To reduce Energy per instruction Winning designs tend to be compromising designs that balance area, transistor utility and CPI Memory comprises the largest leakage energy, therefore, efficient designs must minimize storage

36 Subliminal Architecture Overview IF/ID Stage EX/MEM Stage WB Stage 8 Imem 4x16x2x12 24 Prefetch Buffer 2x2x12 12 Register File 32-bit Timer OpA Control OpB Control 8 ALU 8 8 Carry Zero Register Write Control Flag Control μoperation Decoder External Interrupts Scheduler Page Control 8 Dmem 128x8 8 Fetch Control Jump Control

37 First Subliminal Chip [JSSC 08] Large solar cell Solar cell for processor Custom memories Solar cell for discrete cells Discrete cells Mux-based memories Test memory level converter array Test module Level converter array Solar cell for adders Discrete adders Subliminal processors

38 Pareto Analysis of Sensor Network Processors Energy/Inst (pj) Hempstead (Harvard) 0.85 pj/inst@0.04 MIPS CleverDust (Berkeley) 2.25 pj/inst@1mips MIPS SNAP/LE (Cornell) Subliminal (Michigan)

39 How Subliminal Breaks the Rules Traditional circuit design relies an transistor switching to perform computation Static logic circuits continue to operate below V th by modulating leakage currents Approach lends itself to low-demand sensor apps, as long as care is taken to build an efficient processor

40 More Thoughts on Research A rule-breaking approach is more prone to failure If you're not failing every now and again, it's a sign you're not doing anything very innovative. -Woody Allen Getting the word out is critical to an idea s success Be an evangelist for your project Name your project so the community can talk about it Building H/W (ASICs) is a double-edged sword + Sometimes you can t be convincing w/o a physical demo + If you build it, they (i.e., industry) will come - ASICs are hungry: they eat money, time people, opportunity - Often physical demos render limited insights

41 Concluding Thoughts The rules of low-power design guide much of the work in academia and industry today Breaking these rules, can lead to significant benefits Razor resilient circuits use resiliency mechanisms to eliminate voltage margins Subliminal subthreshold voltage processor minimizes energy by deftly operating below the threshold voltage To me, research is all about breaking the rules, perhaps you too might find it a great way to identify new and exciting opportunities

42 Questions????????????