EE241 - Spring 2013 Advanced Digital Integrated Circuits. Announcements. Lecture 16: Power and Performance

Transcription

1 EE241 - Spring 2013 Advanced Digital Integrated Circuits Lecture 16: Power and Performance Announcements Homework 3 due on Monday Quiz #3 on Monday Makeup lecture on Friday, 3pm, in 540AB 2 1

2 Outline Last lecture Flip-flops This lecture Finish flip-flops Power issues 3 4. Design for performance C. Latches and flip-flops (continued) 2

3 Pulse-Triggered Latches 7474, from mid-1960 s Clk S R Q Q D 5 Pulse-Triggered Latches Sense-amplifier-based flip-flop, Matsui DEC Alpha 21264, StrongARM 110 First stage is a sense amplifier, precharged to high, when Clk = 0 After rising edge of the clock senseamplifier generates the pulse on S or R The pulse is captured in S-R latch Cross-coupled NAND has different propagation delays of rising and falling edges 6 3

4 Sense Amplifier-Based Flip-Flop Courtesy of IEEE Press, New York Sampling Window Comparison Naffziger, JSSC 11/02 8 4

5 Some Interesting Questions How to compare delays analytically? Similar to LE Analytical setup time How to evaluate robustness analytically? 9 4. Design for Performance D. Robustness in Timing 5

6 Shadow Latch Concept Razor Ernst, MICRO 03 If flip-flop fails to capture the data, there will be an error signal generated by the latch 11 Razor I Issues Good idea but has a few issues: Improved idea: 12 6

7 Other Realizations Razor II Das, JSSC 09 Transition detector with time borrowing (TDTB) Bowman, JSSC 09 Several other ideas Low Power Design 7

8 Energy Performance Optimization Increasing performance increases power! 1/Performance 15 Energy Performance Optimization Mircoarchitecture A Mircoarchitecture B 1/Performance 16 8

9 How to Increase Performance? Scale technology Circuit level: Transistor sizing, buffering Wire optimization, repeaters Supply voltage Threshold voltage Logic styles Timing, latches Microarchitecture Block topologies (adders, multipliers) Pipelining Parallelism 17 Sizing Logic Paths for Speed Remember the method of logical effort For minimum delay, all gates should have the same effort (fg) Optimal effort for a gate is around

10 5. Low Power Design A. Power and Energy Basics Importance of Power Awareness Energy: Crucial for Portable Applications Determines battery lifetime Amount of computation Performance is what sells products Power: Crucial for High-Performance Applications Determines cooling and energy costs Many designs today are power limited Still need maximum performance 20 10

11 Portability: Battery Limits Little change in basic technology store energy using a chemical reaction Battery capacity doubles every 10 years Has slowed down Energy density/size, safe handling are limiting factor Energy density KWH/kg of material Gasoline 14 Lead-Acid 0.04 Li polymer Battery Progress Energy Density (Wh/kg) Trend Line First Commercial Use NiCd SLA NiMH Li-Ion Reusable Alkaline Li- Polymer 22 11

12 Know Your Enemy Where does power go in CMOS? Switching (dynamic) power Charging capacitors Leakage power Transistors are imperfect switches Short-circuit power Both pull-up and pull-down on during transition Static currents Biasing currents Low Power Design B. Power-Performance Tradeoffs 12

13 Power-Performance Optimization Energy/op Unoptimized design E max E min D min D max Achieve the highest performance under the power cap 25 Power-Performance Optimization E max E min Energy/op D min Unoptimized design Var1 D max Design optimization curves Achieve the highest performance under the power cap 26 13

14 Power-Performance Optimization E max E min Energy/op D min Unoptimized design Var2 Var1 D max Design optimization curves Achieve the highest performance under the power cap 27 Power-Performance Optimization E max E min Energy/op D min Unoptimized design Var2 Var1 Var1 + Var2 D max Design optimization curves How far away are we from the optimal solution? 28 14

15 Power-Performance Optimization Energy/op Unoptimized design Var1 E max E min Global Var2 Var1 + Var2 Design optimization curves D min D max Global optimum best performance 29 Power-Performance Optimization Energy/op Unoptimized design E max E min D min D max Maximize throughput for given energy or Minimize energy for given throughput 30 15

16 Power-Performance Optimization There are many sets of parameters to adjust Tuning variables Circuit (sizing, supply, threshold) Logic style (std. cells, custom, ) Block topology (adder: CLA, CSA, ) Micro-architecture (parallel, pipelined) Energy/op topology A topology B 31 Power-Performance Optimization There are many sets of parameters to adjust Tuning variables Circuit topology A (sizing, supply, threshold) Logic style (std. cells, custom, ) Block topology topology B (adder: CLA, CSA, ) Micro-architecture (parallel, pipelined) Globally optimal power-performance curve for a given function Energy/op 32 16

17 Energy- Sensitivity Energy S A (A 0,B 0 ) f (A,B 0 ) S A E D A A A A 0 S B f (A 0,B) f (A nom,b) D * 0 33 Solution: Equal Sensitivities E = S A ( D) + S B D Energy (A 0,B 0 ) f (A,B 0 ) D f (A 0,B) f (A 1,B) D 0 At the solution point all sensitivities should be equal 34 17

18 Optimum Across Hierarchy Layers Zyuban et al, TComp Next Lecture Power-performance tradeoffs at circuit level 36 18